CN115360171A - Fan-in type packaging structure and preparation method thereof - Google Patents
Fan-in type packaging structure and preparation method thereof Download PDFInfo
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- CN115360171A CN115360171A CN202211283322.2A CN202211283322A CN115360171A CN 115360171 A CN115360171 A CN 115360171A CN 202211283322 A CN202211283322 A CN 202211283322A CN 115360171 A CN115360171 A CN 115360171A
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
The fan-in type packaging structure comprises a first chip, a supporting carrier, a second chip, a wiring combination layer and a welding ball, wherein the second chip is arranged corresponding to the first chip, the wiring combination layer is electrically connected with the first chip and the second chip at the same time, the welding ball is electrically connected with the wiring combination layer, the supporting carrier on two sides of the second chip is provided with a buffer groove, and the buffer groove extends towards the direction close to the second chip and is used for buffering the structural stress between the first chip and the wiring combination layer. Compared with the prior art, the fan-in type packaging structure and the preparation method thereof can effectively solve the problem of plastic package warpage, realize chip stacking, improve the integration level of chips and reduce the volume of products. Meanwhile, the stress of the internal structure can be effectively eliminated, and a good buffering effect and a good heat dissipation effect are achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-in type packaging structure and a preparation method thereof.
Background
With the rapid development of the semiconductor industry, wafer level packages are classified into fan-out type (fan-out) and fan-in type (fan-in), wherein the fan-out type packages are formed by cutting a wafer into single dies, mounting the dies again, and re-wiring the dies, so that more wiring areas are obtained, and the density of more I/O pads is increased.
However, the fan-out package requires higher requirements for laser drilling and die attachment (e.g., device precision and package flatness) and more molding compound and filler, and the package warpage problem is always a problem in product yield. In addition, the existing fan-in type packaging structure is easy to generate local stress in the process of manufacturing or the process of loading a board, and the product safety is affected. Meanwhile, the multi-surface plastic package structure is adopted, so that the heat dissipation effect is poor. Moreover, in the conventional fan-in type package structure, it is difficult to realize a chip stacking structure, and when a plurality of chips are required to be packaged simultaneously, the chips can only be tiled and packaged, so that the package size is large, and the miniaturization of the product is not facilitated.
Disclosure of Invention
The invention provides a fan-in package structure and a manufacturing method thereof, which can effectively solve the problem of plastic package warpage, realize chip stacking, improve the chip integration level, and reduce the product volume. Meanwhile, the stress of the internal structure can be effectively eliminated, and a good buffering effect and a good heat dissipation effect are achieved.
Embodiments of the invention may be implemented as follows:
in one aspect, an embodiment of the present invention provides a fan-in package structure, including:
a first chip;
the supporting carrier is arranged on one side of the first chip and provided with a mounting groove;
the second chip is arranged in the mounting groove;
the wiring combination layer is arranged on one side of the supporting carrier far away from the first chip;
the solder balls are arranged on one side, far away from the first chip, of the wiring combination layer;
the second chip is arranged corresponding to the first chip, the wiring combination layer is electrically connected with the first chip and the second chip at the same time, the solder balls are electrically connected with the wiring combination layer, the supporting carriers on two sides of the second chip are provided with buffer grooves, and the buffer grooves extend towards the direction close to the second chip and are used for buffering the structural stress between the first chip and the wiring combination layer.
Further, the wiring combination layer includes a first wiring layer, a second wiring layer, a first dielectric layer, a conductive layer and a second dielectric layer, the first dielectric layer is disposed on a side surface of the support carrier away from the first chip, the first wiring layer and the second wiring layer are disposed in the first dielectric layer, the first wiring layer and the second chip are disposed correspondingly and are electrically connected with the first chip and the second chip, the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed on the second dielectric layer, and the conductive layer is electrically connected with the first wiring layer and the second wiring layer.
Furthermore, the supporting carrier is further provided with a conductive column in a penetrating manner, the conductive column is located on two sides of the second chip and located between the second chip and the buffer groove, one end of the conductive column is connected with the first wiring layer, and the other end of the conductive column is connected with the first chip, so that the first wiring layer is electrically connected with the first chip through the conductive column.
Furthermore, an adhesive film layer is further arranged between the supporting carrier and the first chip, and the conductive column penetrates through the adhesive film layer to be connected with the first chip.
Further, the front surface of the first chip is provided with a first bonding pad, the conductive column extends to the first bonding pad and is connected with the first bonding pad, and the projection of one end of the buffer groove close to the second chip on the front surface of the first chip is located between the first bonding pad and the edge of the side wall of the first chip.
Furthermore, the fan-in type packaging structure further comprises a plastic package body, wherein the plastic package body is arranged on one side of the supporting carrier, which is far away from the wiring combination layer, and is wrapped outside the first chip.
Furthermore, the fan-in package structure further includes a substrate carrier, the first chip is disposed on the substrate carrier, and the substrate carrier is located on a side of the first chip away from the support carrier.
Furthermore, a buffer glue layer is filled in the mounting groove and covers the second chip.
In another aspect, an embodiment of the present invention provides a method for manufacturing a fan-in package structure, where the method is used to manufacture the fan-in package structure, and the method includes:
providing a wafer with crystal grains;
a substrate carrier is pasted on the back of the wafer;
mounting a support carrier on the front surface of the wafer, wherein a sacrificial groove is prepared in advance on the support carrier;
removing the substrate carrier;
cutting the wafer to form a first chip;
slotting on the supporting carrier to form a mounting groove;
mounting a second chip in the mounting groove;
forming a wiring combination layer on the support carrier;
forming solder balls on the wiring combination layer;
cutting the sacrificial groove along two staggered cutting lines, and forming a buffer groove on the supporting carrier after the sacrificial groove is broken;
the two cutting channels correspond to the sacrificial grooves, the second chip corresponds to the first chip, the wiring combination layer is electrically connected with the first chip and the second chip at the same time, the solder balls are electrically connected with the wiring combination layer, the buffer grooves are located on the supporting carriers on two sides of the second chip, extend towards the direction close to the second chip and are used for buffering structural stress between the first chip and the wiring combination layer.
Further, after the step of cutting the wafer, the preparation method further comprises:
and forming a plastic package body at one side of the first chip attached to the support carrier, wherein the plastic package body is wrapped outside the first chip.
Further, the step of cutting to the sacrificial trench along two staggered cutting lines includes:
cutting the wiring combination layer to the sacrificial groove along a first cutting path;
cutting the plastic package body to the sacrificial groove along a second cutting path;
the first cutting channels and the second cutting channels are arranged in a staggered mode and correspond to the sacrificial grooves, and the distance between every two adjacent first cutting channels is larger than the distance between every two adjacent second cutting channels.
The beneficial effects of the embodiment of the invention include, for example:
according to the fan-in type packaging structure and the preparation method thereof provided by the embodiment of the invention, the supporting carrier is arranged on one side of the first chip, the mounting groove is formed in the supporting carrier, and then the second chip is arranged in the mounting groove, so that a stacking structure of the first chip and the second chip is realized, the chip integration level is improved, the stacking height is reduced, the whole product is small in size, and the miniaturization of the product is facilitated. Meanwhile, the second chip is arranged corresponding to the first chip, the wiring combination layer is electrically connected with the first chip and the second chip at the same time, the solder balls are electrically connected with the wiring combination layer, the supporting carriers on two sides of the second chip are provided with buffering grooves, the buffering grooves extend towards the direction close to the second chip and are used for buffering the structural stress between the first chip and the wiring combination layer, the structural stress generated in the manufacturing process and the upper plate process can be effectively buffered, the product safety is ensured, and the warping problem is effectively solved. Meanwhile, the arrangement of the buffer grooves enables the heat dissipation area of the surface of the product to be increased, and therefore the heat dissipation capacity of the product is enhanced. Compared with the prior art, the fan-in type packaging structure and the preparation method thereof can effectively solve the problem of plastic package warpage, realize chip stacking, improve the integration level of chips and reduce the volume of products. Meanwhile, the stress of the internal structure can be effectively eliminated, and a good buffering effect and a good heat dissipation effect are achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a fan-in package structure according to an embodiment of the present invention;
fig. 2 to 12 are process flow diagrams of a fan-in package structure according to an embodiment of the invention.
Icon: 100-fan-in type package structure; 110-a first chip; 111-a first pad; 113-a wafer; 130-a support carrier; 131-a buffer trench; 133-conductive pillars; 135-a glue film layer; 137-sacrificial trench; 140-mounting a groove; 141-a buffer glue layer; 150-a second chip; 160-a substrate carrier; 170-wiring combination layer; 171-a first wiring layer; 173-a second wiring layer; 175-first dielectric layer; 177-a conductive layer; 179-second dielectric layer; 180-plastic package body; 190-solder balls.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background, the warpage problem of the plastic package has always plagued the yield of the product when the fan-out package is used in the prior art, which requires higher requirements for laser drilling and die attachment (e.g., device precision and package flatness) and more molding compound and filler.
In addition, conventional fan-in packaging is employed in which, after the entire wafer is molded, the die on the wafer are individually routed, with the I/O pads of each die being limited to the area directly above the surface of the respective die. In the case of a limited area of a die, the number of I/O pads is limited due to the limited pitch of the I/O pads, which in turn limits the number of I/O terminal solder balls that can be packaged on the surface of the die, resulting in some impact on product performance.
Moreover, the existing fan-in type packaging structure is difficult to realize a stacking structure, and the integration level of a chip is low, so that the product volume is large. Meanwhile, the existing fan-in type packaging structure is easy to generate local stress in the process of manufacturing or the process of loading a plate, and the product safety is influenced. Meanwhile, the multi-surface plastic package structure is adopted, so that the heat dissipation effect is poor.
In order to solve the above problems, the present invention provides a novel fan-in package structure and a method for manufacturing the same, and it should be noted that, in the case of no conflict, the features in the embodiments of the present invention may be combined with each other.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Referring to fig. 1, the embodiment provides a fan-in type package structure 100, which can effectively solve the problem of plastic package warpage, and achieve chip stacking, improve chip integration, and reduce product volume. Meanwhile, the stress of the internal structure can be effectively eliminated, and a good buffering effect and a good heat dissipation effect are achieved. Meanwhile, the wiring density and the wiring area are improved, and the product performance is further improved.
The fan-in package structure 100 provided by this embodiment includes a first chip 110, a supporting carrier 130, a second chip 150, a wiring combination layer 170, and solder balls 190, wherein the first chip 110 is formed by cutting a wafer 113, the supporting carrier 130 is disposed on one side of the first chip 110, a mounting groove 140 is formed on the supporting carrier 130, the second chip 150 is disposed in the mounting groove 140, the wiring combination layer 170 is disposed on one side of the supporting carrier 130 away from the first chip 110, and the solder balls 190 are disposed on one side of the wiring combination layer 170 away from the first chip 110; the second chip 150 is disposed corresponding to the first chip 110, the wiring combination layer 170 is electrically connected to the first chip 110 and the second chip 150 at the same time, the solder balls 190 are electrically connected to the wiring combination layer 170, the supporting carrier 130 on both sides of the second chip 150 is provided with buffer grooves 131, and the buffer grooves 131 extend toward a direction close to the second chip 150 for buffering the structural stress between the first chip 110 and the wiring combination layer 170.
In this embodiment, the supporting carrier 130 is disposed on one side of the first chip 110, the mounting groove 140 is disposed on the supporting carrier, and the second chip 150 is disposed in the mounting groove 140, so that the stacking structure of the first chip 110 and the second chip 150 is realized, the chip integration level is improved, and the stacking height is reduced, so that the whole product has a smaller volume, which is beneficial to the miniaturization of the product. Meanwhile, the second chip 150 is disposed corresponding to the first chip 110, the wiring combination layer 170 is electrically connected to the first chip 110 and the second chip 150 at the same time, the solder balls 190 are electrically connected to the wiring combination layer 170, the supporting carrier 130 on both sides of the second chip 150 is provided with the buffer grooves 131, and the buffer grooves 131 extend toward a direction close to the second chip 150, so as to buffer the structural stress between the first chip 110 and the wiring combination layer 170, thereby effectively buffering the structural stress generated in the manufacturing process and the board mounting process, and ensuring the product safety. Meanwhile, the arrangement of the buffer groove 131 also improves the heat dissipation area of the surface of the product, thereby enhancing the heat dissipation capability of the product.
In the embodiment, the supporting carrier 130 is a plate-shaped structure, and the buffering grooves 131 are formed on two sides of the supporting carrier 130, and the buffering grooves 131 thin the supporting carrier 130 and extend toward the second chip 150, so as to greatly increase the heat dissipation area and form a buffering structure to absorb the structural stress to achieve the buffering effect. By providing the buffer groove 131, the cross section of the support carrier 130 can be made to be i-shaped, and the width between the upper end points of the support carrier 130 is much larger than the width between the lower end points.
It should be noted that the fan-in package structure 100 employs a fan-in process in the manufacturing process, so that the substrate carrier 160 is first mounted at the bottom of the wafer 113, the supporting carrier 130 is mounted at the top, and after the substrate carrier 160 is removed and the wafer 113 is cut, the first chip 110 is formed. The process can avoid the warping problem due to the support of the carrier.
The wiring combination layer 170 includes a first wiring layer 171, a second wiring layer 173, a first dielectric layer 175, a conductive layer 177 and a second dielectric layer 179, the first dielectric layer 175 is disposed on a side surface of the support carrier 130 away from the first chip 110, the first wiring layer 171 and the second wiring layer 173 are disposed in the first dielectric layer 175, the first wiring layer 171 is disposed corresponding to the second chip 150 and is electrically connected to the first chip 110 and the second chip 150, the second dielectric layer 179 is disposed on the first dielectric layer 175, the conductive layer 177 is disposed on the second dielectric layer 179, and the conductive layer 177 is electrically connected to the first wiring layer 171 and the second wiring layer 173 at the same time. Specifically, the second wiring layer 173 is disposed in a staggered manner with respect to the first chip 110, and the width of the second wiring layer 173 is greater than that of the first chip 110, so that the wiring area can be greatly increased by disposing the first wiring layer 171 and the second wiring layer 173, and the product performance can be improved. The wiring space of the first wiring layer 171 and the second wiring layer 173 can be expanded by a smart cutting means, so that the wiring range of the second wiring layer 173 is far larger than the upper space corresponding to the first chip 110, and the first wiring layer 171 and the second wiring layer 173 are arranged above the supporting carrier 130, so that the second wiring layer 173 can increase the line integration level, and the problem of small wiring area caused by the fact that the wiring layers are manufactured on the unit chip area of the conventional fan-in type packaging structure 100 is solved.
In the present embodiment, the first wiring layer 171, the second wiring layer 173, and the conductive layer 177 may be copper layers, and the first dielectric layer 175 and the second dielectric layer 179 may be dielectric materials, such as polyimide, silicon nitride, silicon oxynitride, benzocyclobutene, and the like. The conductive layer 177 can be disposed on the first wiring layer 171 and the second wiring layer 173 independently of each other and exposed to the second dielectric layer 179, and the plurality of solder balls 190 are separately disposed on the conductive layer 177.
In the present embodiment, the supporting carrier 130 further has a conductive pillar 133 disposed through the supporting carrier 130, the conductive pillar 133 is located at two sides of the second chip 150 and located between the second chip 150 and the buffer trench 131, one end of the conductive pillar 133 is connected to the first wiring layer 171, and the other end is connected to the first chip 110, so that the first wiring layer 171 is electrically connected to the first chip 110 through the conductive pillar 133. Specifically, the conductive pillars 133 may be a copper electroplating layer, and in actual manufacturing, a conductive hole may be formed by opening a groove on the support carrier 130 by a laser drilling method, and then the copper electroplating layer is plated in the conductive hole to form the conductive pillars 133, where the conductive hole needs to be opened to the first chip 110, so that the conductive pillars 133 can be directly electrically connected to the first chip 110.
In the present embodiment, an adhesive film layer 135 is further disposed between the supporting carrier 130 and the first chip 110, and the conductive pillar 133 passes through the adhesive film layer 135 and is connected to the first chip 110. Specifically, the adhesive film 135 may function as an adhesive support carrier 130, and when the first chip 110 and the support carrier 130 are mounted, a layer of the adhesive film 135 may be coated first, and then the support carrier 130 is mounted, where the conductive pillar 133 needs to penetrate through the adhesive film 135 and directly contact the first chip 110. In addition, the adhesive film layer 135 can also play a role in buffering, the conductive posts 133 are formed in a laser grooving manner, and the adhesive film layer 135 plays a role in buffering. The adhesive layer 135 is a thermosetting material, such as a high molecular epoxy polymer or phenolic aldehyde, melamine formaldehyde, epoxy, unsaturated polyester, silicone, etc.
In this embodiment, the front surface of the first chip 110 is provided with the first pad 111, the conductive pillar 133 extends to the first pad 111 and is connected to the first pad 111, and a projection of one end of the buffer trench 131 close to the second chip 150 on the front surface of the first chip 110 falls between the first pad 111 and the edge of the sidewall of the first chip 110. Specifically, the conductive pillar 133 is directly connected to the first pad 111, so that the conductive pillar 133 is connected to the wiring structure of the first chip 110, and here the buffer trench 131 extends into a position close to the first pad 111 in the horizontal direction, so that the buffer trench 131 partially overlaps with the first chip 110 in the vertical direction, and when the package structure is mounted on an external PCB, the buffer trench 131 can further relieve the structural stress caused by the first chip 110, so as to achieve a better buffer effect.
Further, the fan-in package structure 100 further includes a molding compound 180, and the molding compound 180 is disposed on a side of the supporting carrier 130 away from the wiring combination layer 170 and covers the first chip 110. Specifically, the molding width of the molding body 180 is smaller than the width between the upper end points of the support carriers 130, and is the same as the width between the lower end points of the support carriers 130. Through the plastic package body 180, the first chip 110 can be effectively protected, and meanwhile, the bearing performance of the whole structure is better.
In other preferred embodiments of the present invention, the fan-in package structure 100 further includes a substrate carrier 160, i.e. the substrate carrier 160 replaces the molding compound 180, the first chip 110 is disposed on the substrate carrier 160, and the substrate carrier 160 is located on a side of the first chip 110 away from the supporting carrier 130. The substrate carrier 160 replaces the plastic package body 180, so that the process steps of removing the substrate carrier 160 can be reduced, and the preparation process is simplified.
In the embodiment, the mounting groove 140 is filled with a buffer glue layer 141, and the buffer glue layer 141 wraps around the second chip 150. Specifically, after the mounting groove 140 is formed, the second chip 150 may be mounted, and then the colloid is poured into the mounting groove 140, after curing, the buffer adhesive layer 141 is formed around the second chip 150, and the buffer adhesive layer 141 can play a role in protection and buffering, thereby effectively ensuring the structural integrity of the second chip 150. The thermal expansion coefficient of the buffer adhesive layer 141 is smaller than the thermal expansion coefficient of the second chip 150 and the thermal expansion coefficient of the plastic package body 180, so that the buffer adhesive layer preferentially deforms, absorbs stress, and improves the accuracy of the wiring layer.
In this embodiment, can form through laser trompil mode and paste dress recess 140, when the laser trompil formed and pastes dress recess 140, can solve single product laser trompil displacement deviation problem among the prior art, because there is the subsides dress offset the mode of pasting first chip 110 to the table avoids the skew of the conductive post 133 that subsequent electroplated metal formed, has avoided influencing its electric conductive property.
The embodiment further provides a method for manufacturing the fan-in package structure 100, which is used to manufacture the fan-in package structure 100, and the method includes the following steps:
s1: a wafer 113 with die is provided.
Specifically, referring to fig. 2, a wafer 113 is taken, the wafer 113 is prepared in advance, and a plurality of first pads 111 are further disposed on the front surface of the wafer 113. The first pads 111 and the internal wiring may also be prepared in advance.
S2: a substrate carrier 160 is attached to the back surface of the wafer 113.
Specifically, referring to fig. 3, when mounting the wafer 113 on the substrate carrier 160, a glue layer may be first coated on the substrate carrier 160, and the wafer 113 and the substrate carrier 160 are bonded and fixed by the glue layer, where the substrate carrier 160 may be glass, silicon oxide, metal, or other material, and the glue layer may be a UV glue layer, and the material may be separated by irradiating UV light. Specifically, the adhesive layer may be one of Epoxy (Epoxy) and Polyimide (PI), and may be used as a separation layer of a chip package structure formed subsequently after UV curing or thermal curing, so as to remove the substrate carrier 160.
S3: a support carrier 130 is attached to the front surface of the wafer 113.
Specifically, referring collectively to fig. 4, a sacrificial trench 137 is pre-fabricated on support carrier 130. After the substrate carrier 160 is mounted, the support carrier 130 may be mounted on the front surface of the wafer 113, and a layer of adhesive is also applied, and cured to form the adhesive layer 135, so that the support carrier 130 and the wafer 113 can be firmly fixed together by the adhesive layer 135. The supporting carrier 130 may be made of glass, silicon oxide, metal, etc., and the adhesive film layer 135 is made of a thermosetting material, such as a high molecular epoxy polymer or a material such as phenol, melamine formaldehyde, unsaturated polyester, or silicone.
It should be noted that, the sacrificial trench 137 is designed on the support carrier 130 in advance, wherein the sacrificial trench 137 may be a through-trench structure, and a laser grooving method is used to groove on the sidewall of the support carrier 130, and in the subsequent process, the sacrificial trench 137 is directly conducted with the outside, so that the heat dissipation effect can be achieved.
It should be noted that the supporting carrier 130 can play a role of supporting and limiting, so as to prevent warpage in subsequent plastic packaging and other processes.
S4: the substrate carrier 160 is removed.
Specifically, referring to fig. 5 in combination, the substrate carrier 160 is turned over, and then the surface of the substrate carrier 160 is irradiated with UV to separate the adhesive layer from the wafer 113, remove the substrate carrier 160, and expose the back surface of the wafer 113.
S5: the wafer 113 is diced to form the first chip 110.
Specifically, referring to fig. 6 in combination, after the wafer 113 is exposed, the wafer may be separated from the back side scribe line position of the wafer 113 by laser cutting or mechanical cutting, so as to form the first chip 110. The cutting line position of the back of the wafer is cut according to the cutting line position atlas of the surface of the wafer, the cutting position of the wafer and the cutting line position are scanned before the wafer is fed, the atlas is formed and uploaded to a server, and when the back of the wafer is cut, the cutting atlas position is downloaded from the server, so that back cutting is facilitated. When the wafer is cut, the adhesive film layer 135 can be used as a cutting stop layer to prevent the cutting from affecting the structure carrier 130.
Referring to fig. 7, after the first chip 110 is formed, a plastic package body 180 may be further formed on the side of the supporting carrier 130 where the first chip 110 is attached, and the plastic package body 180 covers the first chip 110.
It should be noted that the cutting process may also be placed in a subsequent cutting process to perform 2 times of cutting, and the plastic package body 180 may also be replaced by the substrate carrier 160, that is, step S4 is removed, the substrate carrier 160 and the wafer 113 are cut together in the subsequent cutting process, and the substrate carrier 160 is shipped with the substrate carrier 160, so that the preparation of the plastic package body 180 is omitted, the subsequent plastic package process is reduced, wherein the structures of the substrate carrier 160 and the support carrier 130 are stable, the process is stable, the package warpage is small, and the accuracy of laser drilling and wiring layer can be improved.
S6: the supporting carrier 130 is grooved to form a mounting groove 140.
Referring to fig. 8 in combination, before the step of mounting the groove 140 is completed, the conductive post 133 may be prepared. Specifically, the supporting carrier 130 and the adhesive film layer 135 are burned to form a conductive hole by a laser grooving method, the first pad 111 on the first chip 110 is exposed, and then a copper layer is electroplated in the conductive hole by an electroplating method again to form the conductive post 133. Here, the width of two adjacent conductive pillars 133 should be greater than the width of the mounting groove 140.
Specifically, referring to fig. 9 in combination, when forming the mounting groove 140, the supporting carrier 130 is grooved by etching or laser grooving to form the mounting groove 140, wherein the size of the mounting groove 140 needs to be larger than that of the second chip 150.
It should be noted that, in the process of using the ion gas to bombard the support carrier 130 to perform the slot, since the sacrificial groove 137 is disposed around the bombarding region, the gas flow rate in the cavity can be increased, which is helpful for improving the ion bombardment effect, and ensures the forming accuracy and forming efficiency of the mounting groove 140.
In addition, in the process of forming the mounting groove by etching or laser grooving, the adhesive film layer 135 can serve as a stop layer to prevent the etching or laser grooving action from affecting the underlying first chip 110.
S7: the second chip 150 is mounted in the mounting recess 140.
Specifically, referring to fig. 10 in combination, after the preparation of the mounting groove 140 is completed, the second chip 150 is mounted in the mounting groove 140, during mounting, an adhesive layer or a silver paste may be coated at the bottom of the second chip 150, the second chip 150 is fixed in the mounting groove 140 by using the adhesive layer or the silver paste, and then the mounting groove 140 is filled with the colloid again, which coats the side wall and the periphery of the second chip 150, so as to protect the second chip 150.
S8: a wiring combination layer 170 is formed on the support carrier 130.
Specifically, referring collectively to fig. 11, first a first dielectric layer 175 is formed on the support carrier 130, then a first wiring layer 171 and a second wiring layer 173 are formed on the first dielectric layer 175, then a second dielectric layer 179 is formed, and a conductive layer 177 is formed on the second dielectric layer 179.
In actual manufacturing, a liquid dielectric material, such as Polyimide, may be uniformly coated on the supporting carrier 130 by a spin coating method using a coater, and then the liquid dielectric material is shaped into a film by soft baking (soft cake) through a Hot plate (Hot plate), and finally the dielectric material is heated by an Oven (Oven) to be cured to a completely cured stable state to form the first dielectric layer 175, where the dielectric material may also be silicon nitride or silicon nitride. Then, a patterned trench is formed on the first dielectric layer 175, for example, by exposure and development to form a patterned opening, and a metal layer, which may be a copper layer, is plated in the patterned trench to form a first wiring layer 171 and a second wiring layer 173. Wherein the copper layer may also be prepared by one of a physical vapor deposition Process (PVD), a chemical vapor deposition process (CVD), sputtering or electroless plating. A second dielectric layer 179 is formed on the first dielectric layer 175 by spin coating, and then a conductive layer 177 is formed by slotting and electroplating.
The second chip 150 is disposed corresponding to the first chip 110, the first wiring layer 171 is electrically connected to the first chip 110 and the second chip 150, and the second wiring layer 173 is disposed in a staggered manner from the first chip 110.
S9: a solder ball 190 is formed on the wiring combination layer 170.
Specifically, referring to fig. 12, a ball-mounting process is performed on the conductive layer 177 by a steel-mesh printing method or a ball-mounting method to form a solder ball 190, where the solder ball 190 may be SnAg, snAgCu, or the like.
S10: the sacrificial grooves 137 are cut along two staggered cutting lines, and after fracture, buffer grooves are formed on the support carrier 130.
Specifically, please refer to fig. 12 (the vertical dashed lines indicate the scribe lines in the figure) two scribe lines correspond to the sacrificial trench 137, the buffer trench 131 is located on the support carrier 130 at two sides of the second chip 150, and the buffer trench 131 extends toward a direction close to the second chip 150 for buffering the structural stress between the first chip 110 and the wiring assembly layer 170.
During cutting, the sacrificial trench 137 is cut from the wiring combination layer 170 along a first cutting path, and then the sacrificial trench 137 is cut from the plastic package body 180 along a second cutting path, wherein the first cutting path and the second cutting path are arranged in a staggered manner and both correspond to the sacrificial trench 137, and a distance between adjacent first cutting paths is greater than a distance between adjacent second cutting paths.
Specifically, the first scribe line is a scribe line of the support carrier 130, and the second scribe line is a scribe line of the wafer 113. The width between the first cutting streets is W1, for example 40 μm, and the width between the second cutting streets is W2, for example 25 μm, so that the upper and lower portions of the cut product can be made larger and smaller by the difference in the widths of the cutting streets, the width of the upper support carrier 130 is much larger than the width of the lower molding body 180, and the wiring area is increased by rewiring on the support carrier 130.
In summary, in the fan-in package structure 100 and the manufacturing method thereof provided by the embodiment, the supporting carrier 130 is disposed on one side of the first chip 110, the mounting groove 140 is disposed on the supporting carrier, and then the second chip 150 is disposed in the mounting groove 140, so that a stacked structure of the first chip 110 and the second chip 150 is realized, the chip integration level is improved, the stacking height is also reduced, the volume of the whole product is smaller, and the miniaturization of the product is facilitated. Meanwhile, the second chip 150 is disposed corresponding to the first chip 110, the wiring combination layer 170 is electrically connected to the first chip 110 and the second chip 150 at the same time, the solder balls 190 are electrically connected to the wiring combination layer 170, the supporting carrier 130 on both sides of the second chip 150 is provided with the buffer grooves 131, and the buffer grooves 131 extend toward a direction close to the second chip 150, so as to buffer the structural stress between the first chip 110 and the wiring combination layer 170, thereby effectively buffering the structural stress generated in the manufacturing process and the board mounting process, and ensuring the product safety. Meanwhile, the arrangement of the buffer groove 131 also improves the heat dissipation area of the surface of the product, thereby enhancing the heat dissipation capability of the product. Compared with the prior art, the fan-in type package structure 100 and the manufacturing method thereof provided by the embodiment can effectively solve the problem of plastic package warpage, realize chip stacking, improve the chip integration level, and reduce the product volume. Meanwhile, the stress of the internal structure can be effectively eliminated, and a good buffering effect and a good heat dissipation effect are achieved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A fan-in package structure, comprising:
a first chip;
the supporting carrier is arranged on one side of the first chip and provided with a mounting groove;
the second chip is arranged in the mounting groove;
the wiring combination layer is arranged on one side of the supporting carrier far away from the first chip;
the solder balls are arranged on one side, far away from the first chip, of the wiring combination layer;
the second chip is arranged corresponding to the first chip, the wiring combination layer is electrically connected with the first chip and the second chip at the same time, the solder balls are electrically connected with the wiring combination layer, the supporting carriers on two sides of the second chip are provided with buffer grooves, and the buffer grooves extend towards the direction close to the second chip and are used for buffering the structural stress between the first chip and the wiring combination layer.
2. The fan-in package structure of claim 1, wherein the wiring combination layer comprises a first wiring layer, a second wiring layer, a first dielectric layer, a conductive layer and a second dielectric layer, the first dielectric layer is disposed on a side surface of the support carrier away from the first chip, the first wiring layer and the second wiring layer are disposed in the first dielectric layer, the first wiring layer and the second chip are disposed correspondingly and electrically connected to the first chip and the second chip, the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed on the second dielectric layer, and the conductive layer is electrically connected to the first wiring layer and the second wiring layer.
3. The fan-in package structure according to claim 2, wherein the supporting carrier further has a conductive pillar penetrating therethrough, the conductive pillar is located at two sides of the second chip and located between the second chip and the buffer trench, one end of the conductive pillar is connected to the first wiring layer, and the other end of the conductive pillar is connected to the first chip, so that the first wiring layer is electrically connected to the first chip through the conductive pillar.
4. The fan-in package structure according to claim 3, wherein an adhesive layer is further disposed between the supporting carrier and the first chip, and the conductive pillar penetrates through the adhesive layer and is connected to the first chip.
5. The fan-in package structure according to claim 3, wherein a first pad is disposed on the front surface of the first chip, the conductive pillar extends to the first pad and is connected to the first pad, and a projection of one end of the buffer trench close to the second chip on the front surface of the first chip falls between the first pad and a sidewall edge of the first chip.
6. The fan-in package structure of claim 1, further comprising a molding compound disposed on a side of the supporting carrier away from the wiring combination layer and covering the first chip.
7. The fan-in package structure of claim 1 further comprising a substrate carrier, wherein the first chip is disposed on the substrate carrier, and wherein the substrate carrier is located on a side of the first chip away from the support carrier.
8. The fan-in package structure of claim 1, wherein a buffer glue layer is filled in the mounting groove and covers the second chip.
9. A method for manufacturing a fan-in package structure, for manufacturing a fan-in package structure according to any one of claims 1 to 8, the method comprising:
providing a wafer with crystal grains;
mounting a substrate carrier on the back of the wafer;
mounting a support carrier on the front surface of the wafer, wherein a sacrificial groove is prepared in advance on the support carrier;
removing the substrate carrier;
cutting the wafer to form a first chip;
slotting the support carrier to form a mounting groove;
mounting a second chip in the mounting groove;
forming a wiring combination layer on the support carrier;
forming solder balls on the wiring combination layer;
cutting the sacrificial grooves along the two staggered cutting lines, and forming buffer grooves on the supporting carrier after the sacrificial grooves are broken;
the two cutting channels correspond to the sacrificial grooves, the second chip corresponds to the first chip, the wiring combination layer is electrically connected with the first chip and the second chip at the same time, the solder balls are electrically connected with the wiring combination layer, the buffer grooves are located on the supporting carriers on two sides of the second chip, and the buffer grooves extend towards the direction close to the second chip and are used for buffering the structural stress between the first chip and the wiring combination layer.
10. The method for manufacturing a fan-in package structure as claimed in claim 9, wherein after the step of cutting the wafer, the method further comprises:
and forming a plastic package body at one side of the first chip attached to the support carrier, wherein the plastic package body is wrapped outside the first chip.
11. The method of claim 10, wherein the step of cutting along two staggered scribe lines to the sacrificial trench comprises:
cutting the wiring combination layer to the sacrificial groove along a first cutting path;
cutting the plastic package body to the sacrificial groove along a second cutting path;
the first cutting channels and the second cutting channels are arranged in a staggered mode and correspond to the sacrificial grooves, and the distance between every two adjacent first cutting channels is larger than the distance between every two adjacent second cutting channels.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116190349A (en) * | 2023-04-25 | 2023-05-30 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure and preparation method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130292845A1 (en) * | 2012-05-03 | 2013-11-07 | SK Hynix Inc. | Stacked semiconductor package and method for manufacturing the same |
| CN104347528A (en) * | 2013-08-02 | 2015-02-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105280567A (en) * | 2014-06-19 | 2016-01-27 | 株式会社吉帝伟士 | Semiconductor package and manufacturing method therefor |
| US20170040290A1 (en) * | 2012-09-28 | 2017-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel three dimensional integrated circuits stacking approach |
| WO2017095094A2 (en) * | 2015-11-30 | 2017-06-08 | 하나마이크론(주) | Metal core solder ball interconnector fan-out wafer level package and manufacturing method therefor |
| US20170229426A1 (en) * | 2016-02-05 | 2017-08-10 | Powertech Technology Inc. | Fan-out back-to-back chip stacked packages and the method for manufacturing the same |
| CN107039407A (en) * | 2015-10-21 | 2017-08-11 | 三星电子株式会社 | Stacked semiconductor package part and its manufacture method |
| CN109786262A (en) * | 2017-11-15 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Interconnection die |
| CN114093861A (en) * | 2021-11-19 | 2022-02-25 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional fan-out type integrated packaging structure, packaging method thereof and wireless earphone |
| CN114256170A (en) * | 2021-12-10 | 2022-03-29 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and preparation method thereof |
| US20220102236A1 (en) * | 2020-09-29 | 2022-03-31 | Samsung Electronics Co., Ltd. | Semiconductor package including heat spreader layer |
| CN114725035A (en) * | 2022-04-06 | 2022-07-08 | 甬矽半导体(宁波)有限公司 | Fan-out type double-sided packaging structure and preparation method thereof |
-
2022
- 2022-10-20 CN CN202211283322.2A patent/CN115360171B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130292845A1 (en) * | 2012-05-03 | 2013-11-07 | SK Hynix Inc. | Stacked semiconductor package and method for manufacturing the same |
| US20170040290A1 (en) * | 2012-09-28 | 2017-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel three dimensional integrated circuits stacking approach |
| CN104347528A (en) * | 2013-08-02 | 2015-02-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105280567A (en) * | 2014-06-19 | 2016-01-27 | 株式会社吉帝伟士 | Semiconductor package and manufacturing method therefor |
| CN107039407A (en) * | 2015-10-21 | 2017-08-11 | 三星电子株式会社 | Stacked semiconductor package part and its manufacture method |
| WO2017095094A2 (en) * | 2015-11-30 | 2017-06-08 | 하나마이크론(주) | Metal core solder ball interconnector fan-out wafer level package and manufacturing method therefor |
| US20170229426A1 (en) * | 2016-02-05 | 2017-08-10 | Powertech Technology Inc. | Fan-out back-to-back chip stacked packages and the method for manufacturing the same |
| CN109786262A (en) * | 2017-11-15 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Interconnection die |
| US20220102236A1 (en) * | 2020-09-29 | 2022-03-31 | Samsung Electronics Co., Ltd. | Semiconductor package including heat spreader layer |
| CN114093861A (en) * | 2021-11-19 | 2022-02-25 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional fan-out type integrated packaging structure, packaging method thereof and wireless earphone |
| CN114256170A (en) * | 2021-12-10 | 2022-03-29 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and preparation method thereof |
| CN114725035A (en) * | 2022-04-06 | 2022-07-08 | 甬矽半导体(宁波)有限公司 | Fan-out type double-sided packaging structure and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116190349A (en) * | 2023-04-25 | 2023-05-30 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure and preparation method thereof |
| CN116190349B (en) * | 2023-04-25 | 2023-06-30 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure and preparation method thereof |
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| Publication number | Publication date |
|---|---|
| CN115360171B (en) | 2023-01-31 |
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