CN115357441A - Universal verification assembly based on UVM and feedback control method - Google Patents
Universal verification assembly based on UVM and feedback control method Download PDFInfo
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- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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Abstract
The invention discloses a universal verification component based on UVM and a feedback control method. The core of the general verification component design is a feedback control logic which is jointly constructed by a transaction monitor, a protocol manager, a virtual sequence arbiter and a virtual sequence, and the feedback control method is divided into two paths: firstly, the control of blocking the virtual sequence transmission is carried out through the validity check constructed by a protocol manager and a virtual sequence arbiter; the second is a protocol handshake flow constructed by the transaction monitor and the virtual sequence arbiter together. The bus protocol behavior simulation system aims to control the simulation of the bus protocol behavior in the universal verification assembly, provide a more flexible mode for the test case to construct the verification scene, save development time for a verification platform and improve the verification efficiency and completeness.
Description
Technical Field
The invention belongs to the technical field of chip verification, and particularly relates to a universal verification assembly based on UVM and a feedback control method.
Background
With the development of the mobile internet era, in order to meet various market demands, different kinds of IP cores are integrated, and the design based on the SOC development platform becomes the mainstream of the chip design at present. The increase of SOC integration level also makes the functional verification as an important ring in the chip development process face many challenges.
The simulation verification is the mainstream technology of the current chip function verification, and the basic steps of the simulation verification are that an input signal of a design to be tested is driven through a verification platform, an output signal of the design to be tested is sampled to be compared with an expectation, and finally the correctness of the function of the design to be tested is verified. In this process, development and debugging of the verification platform consumes a lot of time and effort of the verification personnel.
The existing Verification strategy is to develop a Verification platform based on UVM (Universal Verification Methodology) through the advantages of the UVM Verification Methodology in standardization, automation and reusability, and reuse the Verification platform into the Verification of designs to be tested of different layers or projects, so that the Verification time is shortened.
The problems in the prior art are that:
1. in the verification of the bus bridge type interface, because the interface is usually realized by switching from one protocol to another protocol, the verification personnel is required to more efficiently complete the realization of the proxy verification component only by thoroughly understanding various bus protocols on the market, and finally complete the bus interface verification for switching a specific two protocols (such as ICB protocol to SPI protocol), so that the scenario that the interface can be reused in the future is limited.
2. On the verification of complex bus interfaces. The interface is characterized in that the signal types are more, the information comprises information such as an upstream request item release label and the like, and a set of flow from request initiation to request termination is provided. A typical scenario is that the verification platform needs to simulate that an upstream entry is full and cannot send a new request, while it needs to monitor a downstream release signal, waiting for the release entry to drive the new request. The current scheme mostly completes the feedback control through a test case cooperation agent, and is not flexible in control.
Disclosure of Invention
The invention provides a universal verification component based on UVM and a feedback control method, which are used for solving one or more technical problems in the prior art.
The invention designs a universal verification component based on UVM verification methodology and SystemVerilog language, the verification component is used for simulating a bus protocol layer, the functions of driving, sampling and collecting coverage rate under different modes are configured according to the top layer of a verification platform, the universal verification component can be multiplexed into any verification platform with a protocol interface module according to the granularity of a set of bus protocols, and the universal verification component has more flexible reusability.
The technical scheme of the invention is as follows:
a universal verification component based on UVM, comprising: a protocol transaction package, a transaction driver, a sequencer, a protocol agent, a transaction monitor, a coverage collector, a component configurator, a virtual sequence arbiter, a protocol manager, a virtual sequence, a component interface, and a component top level, wherein:
the protocol transaction packet encapsulates input signals and output signals which are usually possessed by the bus module, and comprises five input variables and three output variables, wherein the five input variables are request marks, request preparations, request commands, request addresses and request data, and the three output variables are response marks, response preparations and response data; wherein the input variables are all random variables that can be randomized;
the transaction driver acquires a protocol transaction packet through the sequencer, and can drive the interface module to be tested through the component interface according to a specific protocol mode set by the component configurator;
the sequencer is used as a bridge between the sequence arbiter and the transaction driver and is used for transmitting a protocol transaction packet and response return information;
the protocol agent instantiates a connection sequence initiator and a transaction driver and transmits a component configurator pointer representing a bus protocol standard of minimum granularity;
the transaction monitor samples protocol transaction packets through a component interface and transmits the protocol transaction packets to other components in a coverage rate collector, a virtual sequence arbiter and a verification platform through a UVM port;
the coverage rate collector is provided with a function coverage group, is triggered by a transaction monitor when a transaction is effective, and collects and counts the function coverage rate through a sampling function;
the component configurator is used for verifying the top-level control of the platform and determining a driving sampling mode and a feedback control path of the universal verification component;
the virtual sequence arbitration is a sequence sending and feedback control node of the universal verification component, wherein the instantiated protocol manager is provided with a sequence generator pointer object and a transaction monitor receiving port, controls all sequence transmission, transaction registration and release operations in the universal verification component, and provides accessible variables and queues for a test case of a verification platform to use;
the protocol manager is responsible for registering transaction requests initiated by the universal verification component and distributing corresponding entries, blocking all subsequent transaction requests when the entries are full, releasing requests corresponding to entry numbers when a release signal from a bus is acquired through the virtual sequence arbiter, and simultaneously running new transaction requests to occupy the entries;
the virtual sequence is a window for sending transaction requests to the test cases, and a single test case can construct a functional scene corresponding to the bus protocol according to multiple sets of virtual sequences provided by different universal verification components;
the verification interface is used for realizing communication between the universal verification component and the bus module to be tested, a verification platform is required to realize a corresponding binding function, and interactive data can be acquired through a pointer object;
all sub-components in the general verification component are packaged at the component top layer, are the minimum level of instantiation and reuse of a verification platform and are managed by a higher-level verification environment component;
the system comprises two feedback paths consisting of a protocol manager, a virtual sequence arbiter and a transaction monitor, wherein the two feedback paths are used for encapsulating the functional scenes which are managed by test cases in the prior art into a general verification component to independently realize hierarchical management;
the feedback path I consists of a virtual sequence, a virtual sequence arbiter and a protocol manager, wherein the virtual sequence is called by a test case written by a verifier, and a control function (the control function is a known function and is not designed by the invention) comprising blocking control, flow control and condition control is integrated inside the virtual sequence; the virtual sequence arbiter integrates the real-time state of the current bus signal and is used for providing an arbitrated condition variable; the protocol manager records the transaction initiated by the virtual sequence before, integrates a condition function (the condition function is a known function and is not designed by the invention) and is used for providing arbitration condition judgment; the first feedback path influences the effectiveness and priority of the test case on a simulation time axis, and a new support method is provided for excitation generation and control;
the transaction monitor integrates a sampling function, provides a real-time bus signal to the condition variable assignment in the virtual sequence arbiter, and completes handshake with the request in the protocol manager through the configuration (the sampling function is a known function, not designed by the invention) so as to influence the condition judgment logic in the feedback path I.
The feedback control method based on the UVM specifically comprises the following steps:
step 1, instantiating the universal verification component in the top layer of a verification platform, binding the universal verification component with an interface module to be tested by using a universal interface, connecting the universal verification component with other verification components by using a UVM port, controlling a component configurator according to a register value of the module to be tested, completing virtual sequence creation, and finally starting the verification platform;
step 2, the virtual sequence sends a protocol transaction packet with access request information to a sequence arbiter, the sequence arbiter inquires that the entry of a protocol manager is not empty, allocates a new entry and sends the protocol transaction packet to a transaction driver through a sequence generator, the transaction driver transmits a time sequence signal which accords with the bus protocol specification according to a working mode set by a current component configurator, and finally, a component interface drives an interface module to be tested;
step 3, a plurality of subsequent continuous access requests are created through a virtual sequence, a sequence arbiter inquires that the protocol manager entry is full and cannot allocate a new entry, and a protocol transaction packet generated by all subsequent access requests is blocked until a receiving port acquires a completion response transmitted by a transaction monitor;
step 4, the transaction monitor accesses the bus signal of the interface module to be tested in each clock cycle, when the transaction completion response is observed, the coverage rate collector is triggered to collect the function coverage rate, and simultaneously the response is respectively sent to the sequence arbiter and other components of the verification platform through the UVM port, after the sequence arbiter receives the completion response, the corresponding entry space is released, and the previously blocked access request is reprocessed;
further, in the step 1, the verification platform sets a component configurator in the verification component in the simulation initialization process;
further, in step 3, the virtual sequence arbiter queries the protocol manager before passing the protocol transaction packet, and allocates a free entry in the protocol manager according to the bus transaction ID number
Further, in step 4, the transaction monitor sends the sampled protocol transaction packet to the virtual sequence arbiter for completing the bus request handshake process;
the invention has the following technical characteristics:
1. compared with the traditional mode of improving the verification efficiency by building a verification platform and repeating, the universal verification component takes the bus protocol layer as the granularity, has a clearer hierarchical structure, improves reusability, and can be flexibly reused in the verification platform needing to verify a plurality of bus protocols;
2. the feedback control method provided by the invention based on the universal verification component cuts the bus protocol control and the test case, the feedback control method realized by the universal verification component can automatically complete a set of bus protocol handshake behaviors without test case intervention, and a verifier can independently complete the compiling of the test case without paying attention to the bus behaviors, thereby greatly improving the verification efficiency; at the same time, the virtual arbiter provides a function for external access to provide flexibility for user-defined scene authentication.
Drawings
FIG. 1 is a block diagram of a universal authentication component of the present invention
FIG. 2 is a flow chart of a feedback control method of the present invention
FIG. 3 is a diagram illustrating a multiplexing of a universal authentication component according to the present invention
FIG. 4 is an expanded view of a universal authentication component of the present invention
Detailed Description
The present invention provides a universal verification assembly based on UVM, as shown in fig. 1, the universal verification assembly is composed of a plurality of UVM assemblies, and the UVM assemblies include: the system comprises a protocol transaction packet, a transaction driver, a sequencer, a protocol agent, a transaction monitor, a coverage rate collector, a component configurator, a virtual sequence arbiter, a protocol manager, a virtual sequence, a component interface and a component top layer, wherein UVM components are connected through instantiations and UVM ports to form a structural hierarchical relationship, and the specific functions of the modules are as follows:
the protocol transaction packet is derived from a uvm _ sequence _ item class, is a class which encapsulates all information of a request mark, a request preparation, a request command, a request address, request data and a response mark, a response preparation and response data in a bus protocol, and has 5 input variables and 3 output variables in total, wherein the input variables are random variables and can be randomized;
the transaction driver is derived from a uvm _ driver class, acquires a protocol transaction packet from the sequencer through a get _ next _ item () function, and can drive an interface module to be tested through a component interface in a run _ phase () task according to a specific protocol mode through the get () function of the component configurator;
the sequencer is derived from a uvm _ sequence class and used as a bridge between a sequence arbiter and a transaction driver, and a protocol transaction packet and response return information are transferred through a start () function;
the protocol agent is derived from the uv _ agent class, instantiates and connects the sequence initiator and the transaction driver through a connect () function, and passes the component configurator pointer;
the transaction monitor is derived from the uvm _ monitor class, samples protocol transaction packets in run _ phase () tasks through component interfaces, and passes them to the coverage collector, virtual sequence arbiter, and other components in the validation platform through the analysis _ port;
the coverage collector is derived from a uvm _ substriber class, a function coverage group is set through a coverage method, a transaction monitor triggers when a transaction is effective, and the function coverage is collected through a sample () function and is subjected to function coverage statistics;
the component configurator is derived from a uv _ object class, subject certificate platform top-level control, and set () and get () functions are built in to be used by other components for configuration and obtaining internal variables;
the virtual sequence arbitration is derived from a uvm _ virtual _ sequence class and is a sequence sending and feedback control node of the universal verification component, wherein the instantiated protocol manager is provided with a sequence generator pointer object and a transaction monitor receiving port, controls all sequence transmission, transaction registration and release operations in the universal verification component, and provides an access () function for test case access of a verification platform;
the protocol manager is derived from a uvm _ object class and is responsible for registering transaction requests initiated by a general verification component and allocating corresponding entries, providing an allocate () function and a release () function for the virtual sequence arbiter to allocate release entries, and also providing full and empty variables to indicate the emptiness and fullness of the protocol manager entries;
the virtual sequence is derived from a uvm _ sequence class, is a window for sending a transaction request for a test case, and is internally provided with a protocol transaction packet for calling the test case to realize an expected scene;
the verification interface is of an interface type and is used for realizing communication between the universal verification component and the bus module to be tested, the verification platform is required to realize a corresponding binding function, and interactive data can be acquired through the pointer object;
the top layer of the component is derived from a uv _ component class, encapsulates all sub-components in the universal verification component, establishes the connection relation of internal components through a connect () function, and transmits a protocol transaction packet sampled by a transaction monitor to a verification platform through an analysis _ export port;
the two feedback paths are composed of the protocol manager, the virtual sequence arbiter and the transaction monitor and are used for encapsulating the functional scenes which are managed by the test cases in the prior art into a general verification component to independently realize hierarchical management;
the feedback path I consists of a virtual sequence, a virtual sequence arbiter and a protocol manager, wherein the virtual sequence is called by a test case written by a verifier, and a control function comprising block control, flow control and condition control is integrated inside the virtual sequence (the control function is a known function and is not designed by the invention); the virtual sequence arbiter integrates the real-time state of the current bus signal and is used for providing an arbitrated condition variable; the protocol manager records the transaction initiated by the virtual sequence before, integrates a condition function (the condition function is a known function and is not designed by the invention) and is used for providing arbitration condition judgment; the first feedback path influences the effectiveness and priority of the test case on a simulation time axis, and a new support method is provided for excitation generation and control;
the second feedback path consists of a virtual sequence arbiter, a transaction monitor and a protocol manager, wherein the transaction monitor integrates a sampling function, provides a real-time bus signal for the assignment of a condition variable in the virtual sequence arbiter, and completes handshake with a request in the protocol manager through the configuration (the sampling function is a known function, which is not designed by the invention) so as to influence the condition judgment logic in the first feedback path.
According to an embodiment of the present invention, there is provided a UVM-based feedback control method, as shown in fig. 2, including the following steps:
step 1, instantiating the universal verification component in the top layer of a verification platform, binding the universal verification component with an interface module to be tested by using a universal interface, connecting the universal verification component with other verification components by using a UVM port, controlling a component configurator according to a register value of the module to be tested, completing virtual sequence creation, and finally starting the verification platform;
step 2, the virtual sequence sends a protocol transaction packet with access request information to a sequence arbiter, the sequence arbiter inquires that the entry of a protocol manager is not empty, allocates a new entry and sends the protocol transaction packet to a transaction driver through a sequence generator, the transaction driver transmits a time sequence signal which accords with the bus protocol specification according to a working mode set by a current component configurator, and finally, a component interface drives an interface module to be tested;
step 3, a plurality of continuous access requests are created through the virtual sequence, the sequence arbiter inquires that the entry of the protocol manager is full and cannot allocate a new entry, and the protocol transaction packets generated by all subsequent access requests are blocked until the receiving port acquires a completion response transmitted by the transaction monitor;
step 4, the transaction monitor accesses the bus signal of the interface module to be tested in each clock cycle, when the transaction completion response is observed, the coverage rate collector is triggered to collect the function coverage rate, and simultaneously the response is respectively sent to the sequence arbiter and other components of the verification platform through the UVM port, after the sequence arbiter receives the completion response, the corresponding entry space is released, and the previously blocked access request is reprocessed;
in this embodiment, the verification platform in step 1 sets a component configurator in the verification component to be performed in the simulation initialization process;
in this embodiment, the virtual sequencer arbiter in step 3 will query the protocol manager before passing the protocol transaction packet, and allocate a free entry in the protocol manager according to the bus transaction ID number
In this embodiment, the transaction monitor in step 4 will send the protocol transaction packet to the virtual sequence arbiter for completing the bus request handshake process;
fig. 3 shows an exemplary diagram of multiplexing of the universal verification component according to the present invention, assuming that universal verification components for the ICB bus protocol, the SPI bus protocol, and the AXI bus protocol have been developed, due to the independence of component packaging, these three sets of universal verification components can be combined two by two for use in a verification platform with six sets of bus bridge modules, which reduces the overhead of repeated development of the verification platform;
fig. 4 shows an exemplary diagram of the extension of the universal authentication component of the present invention, assuming that the universal authentication component based on the AXI bus protocol has been developed, because the universal authentication component needs to extend to support the ACE bus protocol in a project, and because of the similarity between the AXI protocol and the ACE protocol, the ACE protocol broker, the ACE protocol manager, the ACE transaction monitor, and the ACE virtual sequence can be extended on the basis of the original universal authentication component, which reduces the overhead of the additional extension of the authentication component.
The invention has the following technical characteristics:
1. compared with the traditional mode of improving the verification efficiency by building a verification platform and repeating, the universal verification component takes the bus protocol layer as the granularity, has a clearer hierarchical structure, improves reusability, and can be flexibly reused in the verification platform needing to verify a plurality of bus protocols;
2. the feedback control method provided based on the universal verification component cuts the bus protocol control and the test cases, the feedback control method realized by the universal verification component can automatically complete a set of bus protocol handshake behaviors without test case intervention, and a verifier can independently complete the compiling of the test cases without paying attention to the bus behaviors, thereby greatly improving the verification efficiency; at the same time, the virtual arbiter provides a function for external access to provide flexibility for user-defined scene authentication.
Claims (6)
1. A universal verification component based on UVM, comprising: a protocol transaction package, a transaction driver, a sequencer, a protocol agent, a transaction monitor, a coverage collector, a component configurator, a virtual sequence arbiter, a protocol manager, a virtual sequence, a component interface, and a component top level, wherein:
the protocol transaction packet encapsulates input signals and output signals which are usually possessed by the bus module, and comprises five input variables and three output variables, wherein the five input variables are request marks, request preparations, request commands, request addresses and request data, and the three output variables are response marks, response preparations and response data; wherein the input variables are all random variables, which can be randomized;
the transaction driver acquires a protocol transaction packet through the sequencer, and can drive the interface module to be tested through the component interface according to a specific protocol mode set by the component configurator;
the sequencer is used as a bridge between the sequence arbiter and the transaction driver and is used for transmitting a protocol transaction packet and response return information;
the protocol agent instantiates a connection sequence initiator and a transaction driver and transmits a component configurator pointer, which represents a single bus protocol standard;
the transaction monitor samples protocol transaction packets through a component interface and transmits the protocol transaction packets to other components in a coverage rate collector, a virtual sequence arbiter and a verification platform through a UVM port;
the coverage rate collector is provided with a function coverage group, is triggered by a transaction monitor when a transaction is effective, collects and carries out function coverage rate statistics by a sampling function
The component configurator is controlled by the top layer of the verification platform to determine a driving sampling mode and a feedback control path executed by the general verification component;
the virtual sequence arbitration is a sequence sending and feedback control node of the universal verification component, wherein the instantiated protocol manager is provided with a sequence generator pointer object and a transaction monitor receiving port, controls all sequence transmission, transaction registration and release operations in the universal verification component, and provides accessible variables and queues for a test case of a verification platform to use;
the protocol manager is responsible for registering transaction requests initiated by the universal verification component and distributing corresponding entries, blocking all subsequent transaction requests when the entries are full, and releasing the requests corresponding to the entry numbers and allowing new entries to be distributed when a release signal from the bus is acquired through the virtual sequence arbiter;
the virtual sequence is a window for sending transaction requests to the test cases, and a single test case can construct a functional scene corresponding to the bus protocol according to multiple sets of virtual sequences provided by different universal verification components;
the verification interface is used for realizing communication between the universal verification component and the bus module to be tested, a verification platform is required to realize a corresponding binding function, and interactive data can be acquired through a pointer object;
the component top layer encapsulates all sub-components in the universal verification component, is the minimum level of verification platform instantiation and reuse, and is managed by a higher level verification environment component.
2. The universal verification component based on UVM of claim 1, wherein, two feedback paths composed of protocol manager, virtual sequence arbitrator and transaction monitor are used to encapsulate the functional scenes managed by test case in the universal verification component to realize hierarchical management independently;
the first feedback path consists of a virtual sequence, a virtual sequence arbiter and a protocol manager, wherein the virtual sequence is called by a test case written by a verifier, and control functions including blocking control, flow control and condition control are integrated inside the virtual sequence; the virtual sequence arbiter integrates the real-time state of the current bus signal and is used for providing an arbitrated condition variable; the protocol manager records the transaction initiated by the virtual sequence before, integrates a condition function and is used for providing arbitration condition judgment; the first feedback path influences the effectiveness and priority of the test case on a simulation time axis, and a new support method is provided for excitation generation and control;
the transaction monitor integrates a sampling function, provides real-time bus signals for condition variable assignment in the virtual sequence arbiter, completes handshake through configuration and a request in the protocol manager, and further influences condition judgment logic in the feedback path I.
3. A feedback control method based on UVM is characterized by comprising the following steps:
step 1, instantiating the general verification component in the top layer of a verification platform, binding the component interface with an interface module to be tested, connecting the component interface with other verification components by using a UVM port, controlling a component configurator according to a register value of the module to be tested, completing virtual sequence creation, and finally starting the verification platform;
step 2, the virtual sequence sends a protocol transaction packet with access request information to a sequence arbiter, the sequence arbiter inquires that the entry of a protocol manager is not empty, allocates a new entry and sends the protocol transaction packet to a transaction driver through a sequence generator, the transaction driver transmits a time sequence signal which accords with the bus protocol specification according to a working mode set by a current component configurator, and finally, a component interface drives an interface module to be tested;
step 3, a plurality of subsequent continuous access requests are created through a virtual sequence, a sequence arbiter inquires that the protocol manager entry is full and cannot allocate a new entry, and a protocol transaction packet generated by all subsequent access requests is blocked until a receiving port acquires a completion response transmitted by a transaction monitor;
and 4, the transaction monitor acquires a bus signal of the interface module to be tested in each clock cycle, when a transaction completion response is observed, the coverage rate collector is triggered to collect the function coverage rate, meanwhile, the response is respectively sent to the sequence arbiter and other components of the verification platform through the UVM port, and after the sequence arbiter receives the completion response, the corresponding entry space is released, and the previously blocked access request is reprocessed.
4. The UVM-based feedback control method of claim 2, wherein in step 1, the verification platform setting verifies that the component configurator in the component is performed during a simulation initialization process.
5. The UVM-based feedback control method of claim 2, wherein in step 3, the virtual sequencer queries the protocol manager before passing the protocol transaction packet and allocates a free entry in the protocol manager based on the bus transaction ID number.
6. A UVM-based feedback control method according to claim 2 wherein in step 4, the transaction monitor, after sampling a protocol transaction packet, sends the transaction packet to a virtual sequence arbiter for completing a bus request handshake procedure.
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| CN116775394A (en) * | 2023-08-18 | 2023-09-19 | 腾讯科技（深圳）有限公司 | Chip verification method, device, apparatus, storage medium and computer program product |
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| CN116775394A (en) * | 2023-08-18 | 2023-09-19 | 腾讯科技（深圳）有限公司 | Chip verification method, device, apparatus, storage medium and computer program product |
| CN116775394B (en) * | 2023-08-18 | 2024-04-26 | 腾讯科技（深圳）有限公司 | Chip verification method, device, apparatus, storage medium and computer program product |
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