CN115348363A - Encryption/decryption chip, method, equipment and medium based on state cryptographic algorithm - Google Patents
Encryption/decryption chip, method, equipment and medium based on state cryptographic algorithm Download PDFInfo
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- CN115348363A CN115348363A CN202210975761.3A CN202210975761A CN115348363A CN 115348363 A CN115348363 A CN 115348363A CN 202210975761 A CN202210975761 A CN 202210975761A CN 115348363 A CN115348363 A CN 115348363A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/44—Secrecy systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
The invention relates to an encryption/decryption chip, a method, equipment and a medium based on a cryptographic algorithm. The chip includes: the central processing unit is used for sending first data information of data to be encrypted/decrypted; the cryptographic algorithm hardware computing unit is used for receiving the first data information, acquiring data to be encrypted/decrypted from the memory according to the first data information and encrypting/decrypting the data to be encrypted/decrypted to obtain encrypted/decrypted data; the cryptographic algorithm hardware computing unit is also used for storing the encrypted/decrypted data to the memory and sending second data information of the encrypted/decrypted data to the central processing unit; the central processing unit is also used for controlling the communication unit to acquire the encrypted/decrypted data from the memory according to the second data information and transmitting the encrypted/decrypted data; the first data information comprises first data starting position information and first data size information, and the second data information comprises a second data starting position and second data size information.
Description
Technical Field
The invention relates to the technical field of real-time image transmission, mainly relates to image encryption and decryption transmission, and particularly relates to an encryption/decryption chip, method, equipment and medium based on a cryptographic algorithm.
Background
The SM series cipher algorithm introduced by the State cipher administration is used to radically get rid of the dependence of China on foreign cipher technology and realize the information security technology of controlling the core from the cipher algorithm level. The existing Unionpay bank card networking and Unionpay IC specifications introduce the relevant requirements of the national cryptographic algorithm.
In the existing chip, the national cryptographic algorithm is supported by most of the used software libraries of the national cryptographic algorithm, although certain application requirements can be met by using the method, the encryption and decryption of the algorithm are completed by the CPU (central processing unit) to calculate corresponding algorithm data, the method is low in efficiency and low in speed, and the requirements are difficult to meet for scenes with high real-time requirements. For example, in the field of real-time image transmission, since image data needs to be encrypted and decrypted, the data size of encryption and decryption is large and the real-time requirement is high, and the software library mode is difficult to meet the requirement.
Accordingly, there is a need to ameliorate one or more of the problems with the related art solutions described above.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide an encryption/decryption chip, a method, equipment and a medium based on a national encryption algorithm, and further solves the problem that an encryption/decryption mode in a software form cannot easily meet an encryption/decryption scene with high real-time requirement.
The purpose of the invention is realized by adopting the following technical scheme:
in a first aspect, the present invention provides an encryption/decryption chip based on a cryptographic algorithm, the chip comprising:
the central processing unit is used for sending first data information of data to be encrypted/decrypted;
the cryptographic algorithm hardware computing unit is used for receiving the first data information, acquiring the data to be encrypted/decrypted from a memory according to the first data information, and encrypting/decrypting the data to be encrypted/decrypted to obtain encrypted/decrypted data;
the cryptographic algorithm hardware computing unit is also used for storing encrypted/decrypted data to the memory and sending second data information of the encrypted/decrypted data to the central processing unit;
the central processing unit is also used for controlling a communication unit to acquire the encrypted/decrypted data from the memory and transmit the encrypted/decrypted data according to the second data information;
the first data information comprises first data starting position information and first data size information, and the second data information comprises a second data starting position and second data size information.
In the embodiment of the invention, the cryptographic algorithm hardware computing unit is a hardware IP core.
In an embodiment of the present invention, the hardware IP core is an integrated circuit disposed on the cryptographic/decryption chip based on the cryptographic algorithm in a wiring manner.
In the embodiment of the invention, the hardware IP core is an integrated circuit chip and is embedded and installed on the encryption/decryption chip based on the cryptographic algorithm.
In an embodiment of the present invention, the memory is a double rate synchronous dynamic random access memory.
In an embodiment of the present invention, the cryptographic algorithm hardware computing unit obtains the data to be encrypted/decrypted from the memory through a direct memory access device, and stores the encrypted/decrypted data in the memory.
In a second aspect, the present invention provides an encryption/decryption method based on a cryptographic algorithm, the method comprising:
a cryptographic algorithm hardware computing unit receives first data information of data to be encrypted/decrypted, which is sent by a central processing unit, wherein the first data information comprises first data initial position information and first data size information;
the cryptographic algorithm hardware computing unit acquires the data to be encrypted/decrypted from a memory according to the first data information;
the cryptographic algorithm hardware computing unit encrypts/decrypts the data to be encrypted/decrypted to obtain encrypted/decrypted data;
the cryptographic algorithm hardware calculation unit stores the encrypted/decrypted data to the memory;
and the cryptographic algorithm hardware computing unit sends second data information of the encrypted/decrypted data in the memory to a central processing unit, wherein the second data information comprises a second data starting position and second data size information.
In a third aspect, the present invention provides an encryption/decryption method based on a cryptographic algorithm, including:
the central processing unit sends first data information of data to be encrypted/decrypted to a cryptographic algorithm hardware computing unit, wherein the first data information comprises first data initial position information and first data size information;
the central processing unit receives second data information of the encrypted/decrypted data sent by the cryptographic algorithm hardware computing unit, wherein the second data information comprises a second data starting position and second data size information;
and the central processor controls the communication unit to acquire the encrypted/decrypted data from the memory and transmit the encrypted/decrypted data according to the second data information.
In a fourth aspect, the present invention provides an electronic device, where the electronic device includes a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the cryptographic algorithm-based encryption/decryption method according to any one of the above embodiments when executing the computer program.
In a fifth aspect, the present invention provides a computer-readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps of the encryption/decryption method based on the cryptographic algorithm according to any of the above embodiments.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
in the embodiment of the invention, the encryption/decryption chip and the encryption/decryption method based on the national cryptographic algorithm adopt the national cryptographic algorithm hardware computing unit to encrypt and decrypt data, so that the data encryption and decryption speed is greatly improved, the encryption and decryption speed requirement of the data under the real-time transmission condition can be better met, and the national cryptographic algorithm can be more widely applied in multiple fields.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a schematic diagram of an encryption/decryption chip based on a cryptographic algorithm according to an embodiment of the present invention;
FIG. 2 is a flow chart of an encryption/decryption method based on a cryptographic algorithm according to an embodiment of the present invention;
FIG. 3 is a flow chart of another encryption/decryption method based on a cryptographic algorithm according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a program product for an encryption/decryption method based on a cryptographic algorithm in an embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.
In the present exemplary embodiment, first, an encryption/decryption chip based on a cryptographic algorithm is provided, and referring to fig. 1, the chip includes: a Central Processing Unit (CPU) and a cryptographic algorithm hardware computing unit; the central processing unit is used for sending first data information of data to be encrypted/decrypted; the cryptographic algorithm hardware computing unit is used for receiving the first data information, acquiring the data to be encrypted/decrypted from a memory according to the first data information, and encrypting/decrypting the data to be encrypted/decrypted to obtain encrypted/decrypted data; the cryptographic algorithm hardware computing unit is also used for storing encrypted/decrypted data to the memory and sending second data information of the encrypted/decrypted data to the central processing unit; the central processor is also used for controlling the communication unit to acquire the encrypted/decrypted data from the memory according to the second data information and transmitting the encrypted/decrypted data; the first data information comprises first data starting position information and first data size information, and the second data information comprises a second data starting position and second data size information.
According to the encryption/decryption chip based on the national cryptographic algorithm, the data are encrypted and decrypted by the national cryptographic algorithm hardware computing unit, the data encryption and decryption speed is greatly increased, the encryption/decryption speed requirement of the data under the real-time transmission condition can be well met, and the national cryptographic algorithm can be widely applied to multiple fields.
Specifically, the encryption/decryption chip based on the cryptographic algorithm may be a Tequila chip, which is a chip applied to a zero terminal. When data to be encrypted/decrypted, such as image data to be encrypted/decrypted, needs to be encrypted/decrypted, the CPU may send first data information, that is, initial position information and data size information of the image data to be encrypted/decrypted, to the cryptographic algorithm hardware calculation unit in a manner of sending a control signaling, and the cryptographic algorithm hardware calculation unit locates an initial position of the data to be encrypted in the memory according to the initial position information of the data, and obtains a data segment to be encrypted according to the data size information. And the cryptographic algorithm hardware computing unit performs encryption/decryption processing on the data segment needing to be encrypted, stores the processed encryption/decryption data in the memory again after the processing is finished, and then sends second initial position information and second data size information of the encryption/decryption data in the memory to the CPU as second information through signaling. And after receiving the second information, the CPU controls the communication unit to acquire the encrypted/decrypted data from the memory and transmit the encrypted/decrypted data according to the content of the second information.
Next, each part of the above encryption/decryption chip based on the cryptographic algorithm in the present exemplary embodiment will be described in more detail with reference to fig. 1.
In one embodiment, the cryptographic hardware computation unit may be a hardware IP core. Specifically, the IP core is the meaning of the intellectual property core or intellectual property module, and has a very important position in the development of EDA technology. The U.S. famous Dataquest consultant company defines the IP of the semiconductor industry as "pre-designed circuit function modules for use in ASICs or FPGAs". The IP is mainly classified into soft IP, fixed IP, and hard IP.
In one embodiment, the hardware IP core may be an integrated circuit disposed on the cryptographic algorithm-based encryption/decryption chip by wiring. Specifically, the hardware IP core may be an integrated circuit disposed on an encryption/decryption chip based on the cryptographic algorithm by way of wiring, and the integrated circuit is electrically connected to the CPU, and the integrated circuit may support the SM4 algorithm in the cryptographic algorithm series.
In one embodiment, the hardware IP core is an integrated circuit chip mounted in a mosaic manner on the cryptographic algorithm based encryption/decryption chip. Specifically, the hardware IP core may be an integrated circuit board, which is mounted on an encryption/decryption chip of the cryptographic algorithm in a mosaic manner and is electrically connected to the CPU, and the integrated circuit board may support the SM4 algorithm in the cryptographic algorithm series.
In one embodiment, the memory is a Double data Rate synchronous dynamic random access memory (DDR). Specifically, the double-rate synchronous dynamic random access memory is a storage space which can be directly addressed by a CPU, is made of a semiconductor device and is characterized by high data access speed.
In one embodiment, the cryptographic algorithm hardware computing unit obtains the data to be encrypted/decrypted from the Memory through a Direct Memory Access (DMA), and stores the encrypted/decrypted data in the Memory. In particular, DMA devices allow hardware devices of different speeds to communicate without relying on a large interrupt load on the CPU. Otherwise, the CPU needs to copy each piece of data from the source to the register and then write them back to the new place again, during which time the CPU is unavailable for other work. Therefore, the direct memory access device is adopted to carry out data access and transmission, a CPU is not required to be relied on, and the throughput of the encryption and decryption data is further improved.
Secondly, in this exemplary embodiment, an encryption/decryption method based on a cryptographic algorithm is provided, please refer to fig. 2, and the method includes:
step S101: a cryptographic algorithm hardware computing unit receives first data information of data to be encrypted/decrypted, which is sent by a central processing unit, wherein the first data information comprises first data initial position information and first data size information;
step S102: the cryptographic algorithm hardware computing unit acquires the data to be encrypted/decrypted from a memory according to the first data information;
step S103: the cryptographic algorithm hardware computing unit encrypts/decrypts the data to be encrypted/decrypted to obtain encrypted/decrypted data;
step S104: the cryptographic algorithm hardware calculation unit stores the encrypted/decrypted data to the memory;
step S105: and the cryptographic algorithm hardware computing unit sends second data information of the encrypted/decrypted data in the memory to a central processing unit, wherein the second data information comprises a second data starting position and second data size information.
The present exemplary embodiment further provides an encryption/decryption method based on a cryptographic algorithm, please refer to fig. 3, which includes:
step S201: the central processing unit sends first data information of data to be encrypted/decrypted to a cryptographic algorithm hardware computing unit, wherein the first data information comprises first data initial position information and first data size information;
step S202: the central processing unit receives second data information of the encrypted/decrypted data sent by the cryptographic algorithm hardware computing unit, wherein the second data information comprises a second data starting position and second data size information;
step S203: and the central processor controls the communication unit to acquire the encrypted/decrypted data from the memory and transmit the encrypted/decrypted data according to the second data information.
According to the encryption/decryption method based on the national cryptographic algorithm, the data are encrypted and decrypted by the national cryptographic algorithm hardware computing unit, the data encryption and decryption speed is greatly increased, the encryption/decryption speed requirement of the data under the real-time transmission condition can be well met, and the national cryptographic algorithm can be widely applied to multiple fields.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units. The components shown as modules or units may or may not be physical units, i.e. may be located in one place or may also be distributed over a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the wood-disclosed scheme. One of ordinary skill in the art can understand and implement it without inventive effort.
Referring to fig. 4, an embodiment of the present invention further provides an electronic device 300, where the electronic device 300 includes at least one memory 310, at least one processor 320, and a bus 330 connecting different platform systems.
The memory 310 further stores a computer program, and the computer program can be executed by the processor 320, so that the processor 320 executes the steps of the encryption/decryption method based on the cryptographic algorithm in any embodiment of the present invention, and the specific implementation manner of the method is consistent with the implementation manner and the achieved technical effect described in the above embodiment of the encryption/decryption method based on the cryptographic algorithm, and some contents are not described again.
The memory 310 may also include a utility 314 having at least one program module 315, such program modules 315 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.
Accordingly, the processor 320 may execute the computer programs described above, and may execute the utility 314.
The electronic device 300 may also communicate with one or more external devices 340, such as a keyboard, pointing device, bluetooth device, etc., as well as one or more devices capable of interacting with the electronic device 300, and/or any device (e.g., router, modem, etc.) that enables the electronic device 300 to communicate with one or more other computing devices. Such communication may be through input-output interface 350. Also, the electronic device 300 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 360. Network adapter 360 may communicate with other modules of electronic device 300 via bus 330. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with electronic device 300, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms, to name a few.
The embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium is used for storing a computer program, and when the computer program is executed, the steps of the encryption/decryption method based on the cryptographic algorithm in the embodiment of the present invention are implemented, and a specific implementation manner of the method is consistent with the implementation manner and the achieved technical effect described in the embodiment of the encryption/decryption method based on the cryptographic algorithm, and some contents are not described in detail again.
Fig. 5 shows a program product 400 provided by the present embodiment for implementing the encryption/decryption method based on the cryptographic algorithm, which may employ a portable compact disc read only memory (CD-ROM) and include program codes, and may be run on a terminal device, such as a personal computer. However, the program product 400 of the present invention is not limited in this respect, and in the present invention, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. Program product 400 may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
A computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the C programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. An encryption/decryption chip based on a cryptographic algorithm, comprising:
the central processing unit is used for sending first data information of data to be encrypted/decrypted;
the cryptographic algorithm hardware calculation unit is used for receiving the first data information, acquiring the data to be encrypted/decrypted from a memory according to the first data information, and encrypting/decrypting the data to be encrypted/decrypted to obtain encrypted/decrypted data;
the cryptographic algorithm hardware computing unit is also used for storing encrypted/decrypted data to the memory and sending second data information of the encrypted/decrypted data to the central processing unit;
the central processing unit is also used for controlling a communication unit to acquire the encrypted/decrypted data from the memory and transmit the encrypted/decrypted data according to the second data information;
the first data information comprises first data starting position information and first data size information, and the second data information comprises a second data starting position and second data size information.
2. The cryptographic algorithm-based encryption/decryption chip of claim 1, wherein the cryptographic algorithm hardware computing unit is a hardware IP core.
3. The cryptographic algorithm-based encryption/decryption chip of claim 2, wherein the hardware IP core is an integrated circuit disposed on the cryptographic algorithm-based encryption/decryption chip by wiring.
4. The cryptographic algorithm-based encryption/decryption chip of claim 2, wherein the hardware IP core is an integrated circuit chip mounted on the cryptographic algorithm-based encryption/decryption chip in a mosaic manner.
5. The cryptographic algorithm based encryption/decryption chip of any one of claims 1 to 4, wherein the memory is a double-rate synchronous dynamic random access memory.
6. The cryptographic algorithm based encryption/decryption chip of claim 5, wherein the cryptographic algorithm hardware computing unit obtains the data to be encrypted/decrypted from the memory through a direct memory access device, and stores the encrypted/decrypted data to the memory.
7. An encryption/decryption method based on a cryptographic algorithm is characterized by comprising the following steps:
a cryptographic algorithm hardware computing unit receives first data information of data to be encrypted/decrypted, which is sent by a central processing unit, wherein the first data information comprises first data initial position information and first data size information;
the cryptographic algorithm hardware computing unit acquires the data to be encrypted/decrypted from a memory according to the first data information;
the cryptographic algorithm hardware computing unit encrypts/decrypts the data to be encrypted/decrypted to obtain encrypted/decrypted data;
the cryptographic algorithm hardware calculation unit stores the encrypted/decrypted data to the memory;
and the cryptographic algorithm hardware computing unit sends second data information of the encrypted/decrypted data in the memory to a central processing unit, wherein the second data information comprises a second data starting position and second data size information.
8. An encryption/decryption method based on a cryptographic algorithm is characterized by comprising the following steps:
the central processing unit sends first data information of data to be encrypted/decrypted to a cryptographic algorithm hardware computing unit, wherein the first data information comprises first data initial position information and first data size information;
the central processing unit receives second data information of the encrypted/decrypted data sent by the cryptographic algorithm hardware computing unit, wherein the second data information comprises a second data starting position and second data size information;
and the central processor controls the communication unit to acquire the encrypted/decrypted data from the memory and transmit the encrypted/decrypted data according to the second data information.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the cryptographic algorithm based encryption/decryption method according to any one of claims 7-8 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the cryptographic algorithm based encryption/decryption method according to any one of claims 7 to 8.
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| CN115982067A (en) * | 2023-03-21 | 2023-04-18 | 北京智芯微电子科技有限公司 | Bus control device and method, industrial control processing chip and industrial control system |
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