CN115346575A

CN115346575A - Static random access memory circuit and electronic product

Info

Publication number: CN115346575A
Application number: CN202210971682.5A
Authority: CN
Inventors: 程仁豪
Original assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Current assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date: 2022-08-12
Filing date: 2022-08-12
Publication date: 2022-11-15

Abstract

The invention provides a static random access memory circuit and an electronic product, wherein the static random access memory circuit comprises a storage array, a source bias circuit and a control circuit, the control circuit compares a source bias voltage output by the source bias circuit with a reference voltage and outputs a feedback signal to control the source bias voltage output by the source bias circuit according to the comparison result, so that the source bias voltage provided by the source bias circuit for the storage array is self-adaptively adjusted, the logic is simple, the sensitivity is high, the universality is high, and the increase of the circuit area is less.

Description

Static random access memory circuit and electronic product

Technical Field

The invention relates to the technical field of low power consumption control, in particular to a static random access memory circuit and an electronic product.

Background

Static power consumption, i.e. power consumption consumed when the power supply and ground are turned on, when the circuit is not operating, leakage current will flow through the circuit, and thus static power consumption may also be referred to as leakage current power consumption.

In an application direction requiring power consumption control, such as a wearable device/a vehicle-mounted chip, static Random-Access Memory (SRAM) has a non-negligible portion of Static power consumption. Because static power consumption cannot be reduced by cutting off power supply due to the particularity of the SRAM storage principle, in a low-power SRAM design, a sleep mode (sleep mode) and source bias (source bias) mechanism is usually selected to be introduced, and static power consumption reduction is realized by partial voltage reduction of a storage array (array).

However, currently, in the working voltage range (1V to 2V) of the SRAM, there is no better adaptive source bias scheme for reducing the static power consumption of the SRAM.

Disclosure of Invention

The invention aims to provide a static random access memory circuit and an electronic product, which have simple circuits, can realize self-adaptive adjustment and have high sensitivity.

To achieve the above object, the present invention provides a static random access memory circuit, which includes:

a memory array for storing data;

a source bias circuit coupled to the memory array for providing a source bias voltage to the memory array;

and the control circuit is coupled with the source bias circuit and used for comparing the source bias voltage output by the source bias circuit with a reference voltage and outputting a feedback signal to control the source bias voltage output by the source bias circuit according to the comparison result.

Optionally, the control circuit includes a sense amplifier.

Optionally, the sense amplifier includes:

the first switch unit is used for conducting under the control of a control signal so as to access the source bias voltage;

the second switch unit is used for being conducted under the control of the control signal so as to be connected with the reference voltage;

a coupling inverting unit coupled to the first switching unit and the second switching unit for comparing the source bias voltage with the reference voltage;

and the output unit is coupled with the coupling inverting unit and used for outputting the feedback signal according to the comparison result of the coupling inverting unit.

Optionally, the first switching unit includes a first MOS transistor, and the second switching unit includes a second MOS transistor; the grid electrodes of the first MOS tube and the second MOS tube are both connected to the control signal, the source electrode of the first MOS tube is connected to the source bias voltage, and the source electrode of the second MOS tube is connected to the reference voltage; the drain of the first MOS tube is coupled with the first port of the coupling inverting unit and one end of the output unit, and the drain of the second MOS tube is coupled with the second port of the coupling inverting unit and the other end of the output unit.

Optionally, the coupling inverting unit includes third to sixth MOS transistors, a source of the third MOS transistor and a source of the fourth MOS transistor are both connected to a first power voltage for supplying power to the control circuit, a source of the fifth MOS transistor and a source of the sixth MOS transistor are coupled, a drain of the third MOS transistor and a drain of the fifth MOS transistor are coupled and serve as a first port of the coupling inverting unit, a drain of the fourth MOS transistor and a drain of the sixth MOS transistor are coupled and serve as a second port of the coupling inverting unit, a gate of the third MOS transistor and a gate of the fifth MOS transistor are coupled and coupled to the second port, and a gate of the fourth MOS transistor and a gate of the sixth MOS transistor are coupled and coupled to the first port.

Optionally, the output unit includes: a first NAND logic circuit, a second NAND logic circuit, and a first inverting logic circuit; the first input end of the first NAND logic circuit is coupled with the second port of the coupling inverting unit, and the second input end of the first NAND logic circuit is coupled with the output end of the second NAND logic circuit and the input end of the first inverting logic circuit; a first input end of the second NAND logic circuit is coupled with an output end of the first NAND logic circuit, and a second input end of the second NAND logic circuit is coupled with a first port of the coupling inverting unit; the output end of the first inverting logic circuit is coupled with the source biasing circuit.

Optionally, the sense amplifier further includes a pull-down switch unit, coupled to the coupling inverting unit, and configured to be turned on under the control of the control signal to provide a second power voltage to the coupling inverting unit.

Optionally, the source bias circuit includes:

the second inverting logic circuit is coupled with the output end of the control circuit and used for accessing the feedback signal and outputting an inverted signal inverted with the feedback signal;

at least two voltage drop branches with different voltage drop degrees, wherein at least one voltage drop branch is coupled to the output end of the control circuit and is used for providing voltage drop with corresponding degree under the control of the feedback signal, and at least another voltage drop branch is coupled to the output end of the second inverting logic circuit and is used for providing voltage drop with corresponding degree under the control of the inverting signal;

and the sum of the voltage drops provided by all the voltage drop branches at the same time is the source bias voltage provided by the source bias circuit.

Optionally, the voltage drop branch includes at least two cascaded MOS transistors, and the number of the cascaded MOS transistors in the voltage drop branches with different voltage drop degrees is different.

Based on the same inventive concept, the invention also provides an electronic product comprising the static random access memory circuit.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. under the feedback of the control circuit, the source bias circuit can realize self-adaptive adjustment;

2. the circuit has simple logic, high sensitivity and strong universality, and the increase of the circuit area is less, for example, the circuit area can be controlled to be increased by about 0.5%;

3. the extra power consumption is only generated when the control circuit performs voltage comparison, and the power supply of the control circuit can be cut off after the system enters a sleep mode (sleep mode), so that the extra static power consumption is not increased in the sleep mode.

Drawings

Fig. 1 is a schematic diagram of a circuit architecture of an SRAM that employs a source bias mechanism to reduce power consumption.

Fig. 2 is a schematic diagram of a circuit architecture of a conventional SRAM that employs a voltage-follower analog circuit to reduce power consumption.

FIG. 3 is a system architecture diagram of an SRAM circuit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of an exemplary circuit structure of a control module in an sram circuit according to an embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating an exemplary structure of a source bias module in an sram circuit according to an embodiment of the present invention.

FIG. 6 is a timing diagram of corresponding signals in the SRAM circuit according to the embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" other elements, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Referring to fig. 1, in order to balance data security and low power consumption of the SRAM in the prior art, one solution is to introduce a source bias circuit 20 and control the output of the source bias circuit 20 by applying control signals B0 and B1 to provide a voltage drop (i.e., a source bias voltage) VDDC of different degrees to a memory array 10 of the SRAM, wherein a combination of the control signals B0 and B1 satisfying different operating modes can be generated by a programmable control structure (e.g., a decoding circuit) to select a corresponding VDDC level setting of the source bias voltage VDDC. The method has the advantages of simple circuit structure, flexible use and no introduction of extra power consumption. It has the following disadvantages: (1) In order to ensure data safety, the scheme needs conservative design, and the power consumption reduction effect is not obvious; (2) adaptive adjustment cannot be achieved; (3) Under the change of external environmental conditions, the voltage reduction effect of the memory array of the SRAM is not controllable, and especially when the voltage drop of the memory array 10 exceeds the Data Retention Voltage (DRV), the Data may be damaged, so the voltage reduction effect of the SRAM may be usually selected to be a conservative design. The data retention voltage DRV refers to a minimum voltage at which data is retained in the SRAM in an idle state.

Referring to fig. 2, in order to achieve the effect of adaptive regulation, a voltage follower analog circuit 30 is usually introduced to provide a corresponding source bias voltage VDDC to the memory array 10. The voltage following analog circuit 30 can be connected to the voltage before and after the voltage division of the resistors R1 and R2, and further adaptively adjust the source bias voltage VDDC output by the voltage following analog circuit according to the obtained voltage division result, so that the adaptive adjustment can be realized, and the sensitivity is high, but the method has the following disadvantages: (1) The structure of the voltage following analog circuit 30 is complex, which generally includes a current source, a reference voltage generator, a voltage follower, etc., the circuit area is significantly increased, and the added modules (such as the current source, the reference voltage generator, the voltage follower, etc.) themselves bring extra power consumption, and cannot be turned off in a sleep mode; (2) The universality is poor, and the voltage following analog circuit 30 needs to be readjusted and designed for SRAM memories with different specifications.

The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 3, an embodiment of the invention provides a sram circuit including a memory array 10, a source bias circuit 20, and a control circuit 40. The memory array 10 is used for storing data, and can perform operations such as reading, writing, and erasing of data under the control of the word line signal WL, the bit line signals BL and BLB, the source bias voltage VDDC, and the second power supply voltage VSS. The source bias circuit 20 is coupled to the memory array 10 and is configured to provide a source bias voltage VDDC to the memory array 10. The control circuit 40 is coupled to the source bias circuit 20, and is configured to compare the source bias voltage VDDC output by the source bias circuit 20 with a reference voltage VREF, and output a feedback signal AUTO _ SB according to the comparison result to control (i.e., adjust) the magnitude of the source bias voltage VDDC output by the source bias circuit 20.

Optionally, the control circuit 40 includes a sense amplifier.

Referring to fig. 4, further optionally, the sense amplifier includes a first switch unit 401, a second switch unit 402, a coupling inverting unit 403, a pull-down switch unit 404, and an output unit 405.

The first switch unit 401 is turned ON under the control of a control signal ABS _ ON to switch ON the source bias voltage VDDC. The second switch unit 402 is configured to be turned ON under the control of the control signal ABS _ ON to switch in the reference voltage VREF.

As an example, referring to fig. 4, the first switching unit 401 includes a first MOS transistor P1, and the second switching unit includes a second MOS transistor P2. The gates of the first MOS transistor P1 and the second MOS transistor P2 are both connected with a control signal ABS _ ON, the source electrode of the first MOS transistor P1 is connected with a source bias voltage VDDC, and the source electrode of the second MOS transistor P2 is connected with a reference voltage VREF. The drain of the first MOS transistor P1 is coupled to the first port D of the coupling inverting unit 403 and one end of the output unit 405, and the drain of the second MOS transistor P2 is coupled to the second port DX of the coupling inverting unit 403 and the other end of the output unit 405. The first MOS transistor P1 and the second MOS transistor P2 may be common-gate PMOS transistors.

The first MOS transistor P1 and the second MOS transistor P2 can be turned ON simultaneously under the control of the control signal ABS _ ON. And after the first MOS transistor P1 and the second MOS transistor P2 are turned on simultaneously, the coupling inverting unit 403 is used for comparing the source bias voltage VDDC and the reference voltage VREF.

As an example, referring to fig. 4, the coupling inverting unit 403 includes a third MOS transistor P3, a fourth MOS transistor P4, a fifth MOS transistor N1, and a sixth MOS transistor N2, where the third MOS transistor P3 and the fourth MOS transistor P4 may be both PMOS transistors, and the fifth MOS transistor N1 and the sixth MOS transistor N2 are both NMOS transistors. A source of the third MOS transistor P3 and a source of the fourth MOS transistor P4 are both connected to a first power voltage VDD (VDD is a power voltage of the whole sram circuit after being powered on) for supplying power to the control circuit 40 and the source bias circuit 20, a source of the fifth MOS transistor N1 and a source of the sixth MOS transistor N2 are coupled, a drain of the third MOS transistor P3 and a drain of the fifth MOS transistor N1 are coupled and serve as a first port D of the coupling inversion unit 403, a drain of the fourth MOS transistor P4 and a drain of the sixth MOS transistor N2 are coupled and serve as a second port DX of the coupling inversion unit 403, a gate of the third MOS transistor P3 and a gate of the fifth MOS transistor N1 are coupled and coupled to the second port DX, and a gate of the fourth MOS transistor P4 and a gate of the sixth MOS transistor N2 are coupled and coupled to the first port D.

Referring to fig. 4, the pull-down switch unit 404 is coupled to the source of the fifth MOS transistor N1 and the source of the sixth MOS transistor N2 of the coupling inverting unit 403, and is turned ON under the control of the control signal ABS _ ON to provide the second power voltage VSS to the coupling inverting unit 403. The pull-down switch unit 404 may include a seventh MOS transistor N3, a gate of the seventh MOS transistor N3 is connected to the control signal ABS _ ON, a drain of the seventh MOS transistor N3 is coupled to a source of the fifth MOS transistor N1 and a source of the sixth MOS transistor N2, and a source of the seventh MOS transistor N3 is connected to a second power voltage VSS, where the second power voltage VSS is different from the first power voltage VDD and is generally used for implementing the grounding of the sram circuit.

Optionally, when the fifth MOS transistor N1 and the sixth MOS transistor N2 are NMOS transistors, the seventh MOS transistor N3 is also an NMOS transistor, and the second power voltage VSS is the ground voltage 0V, that is, the source electrode of the seventh MOS transistor N3 is grounded.

Referring to fig. 4, the output unit 405 is coupled to the first port D and the second port DX of the coupling inverting unit 403, and is used for outputting the feedback signal AUTO _ SB according to the comparison result of the coupling inverting unit 403.

Optionally, with continued reference to fig. 4, the output unit 405 includes a first nand logic circuit nand1, a second nand logic circuit nand2, and a first inverter logic circuit inv1. A first input (not labeled) of the first nand logic circuit nand1 is coupled to the second port DX of the coupling inverting unit 403, and a second input (not labeled) of the first nand logic circuit nand1 is coupled to an output of the second nand logic circuit nand2 and an input of the first inverting logic circuit inv1. A first input terminal of the second nand logic circuit nand2 is coupled to the output terminal of the first nand logic circuit nand1, a second input terminal of the second nand logic circuit nand2 is coupled to the first port D of the inverting unit 403, and an output terminal of the first inverting logic circuit inv1 is coupled to the source bias circuit 20 to provide the feedback signal AUTO _ SB to the source bias circuit 20.

The first nand logic circuit nand1 and the second nand logic circuit nand2 may be implemented by nand gates, or may be implemented by any suitable circuit capable of implementing nand logic, and the first inverting logic circuit inv1 may be implemented by inverters, or may be implemented by any suitable circuit capable of implementing inverting logic, which is not specifically limited in this disclosure.

Referring to fig. 6, the working principle of the sense amplifier of the present embodiment is as follows: when the control signal ASB _ ON is a low level "0", the first MOS transistor P1 and the second MOS transistor P2 are turned ON, and the source bias voltage VDDC and the reference voltage VREF are transmitted to the first port D and the second port DX of the coupling inverting unit 403, and when the control signal ASB _ ON is a high level "1", the first MOS transistor P1 and the second MOS transistor P2 are turned off, so that the differential pressure change is prevented from being influenced by noise, and the output result is further influenced. When VDDC > VREF, the level of the second port DX is changed to a low level "0", the level of the first port D is changed to a high level "1", and the output feedback signal AUTO _ SB is changed to a high level "1", whereas when VDDC < VREF, the level of the second port DX is changed to a high level "1", the level of the first port D is changed to a low level "0", and the output feedback signal AUTO _ SB is changed to a low level "0".

Optionally, referring to fig. 5, the source bias circuit 20 includes a second inverting logic circuit inv2 and at least two voltage drop branches with different voltage drop degrees, where the second inverting logic circuit inv2 is coupled to the output terminal of the control circuit 40, and is configured to receive the feedback signal AUTO _ SB and output an inverted signal AUTO _ SBX inverted from the feedback signal AUTO _ SB. Of all the voltage drop branches, at least one voltage drop branch 201 is coupled to the output terminal of the control circuit 40 and is connected to the first power voltage VDD, and is configured to provide a corresponding voltage drop (i.e., output after the first power voltage VDD is converted into a source bias voltage VDDC of a corresponding tap) under the control of the feedback signal AUTO _ SB, and at least another voltage drop branch 202 is coupled to the output terminal of the second inverting logic circuit inv2 and is connected to the first power voltage VDD, and is configured to provide a corresponding voltage drop (i.e., output after the first power voltage VDD is converted into a source bias voltage VDDC of another corresponding tap) under the control of the inverting signal AUTO _ SBX.

The second inverting logic circuit inv2 may be implemented by an inverter, and may also be implemented by any suitable circuit capable of implementing "inverting" logic, which is not specifically limited in the present invention.

It should be understood that the magnitude (i.e., the shift position) of the source bias voltage VDDC finally output by the source bias circuit 20 is related to the level of the feedback signal AUTO _ SB and the number of voltage drop branches that are turned on under the control of the feedback signal AUTO _ SB and the inverted signal AUTO _ SBX, wherein all the voltage drop branches provide the sum of the voltage drops at the same time to be the source bias voltage VDDC output by the source bias circuit 20. Therefore, the magnitude (i.e., the gear) of the source bias voltage VDDC output by the source bias circuit 20 can be adaptively adjusted according to the level of the feedback signal AUTO _ SB.

Optionally, each voltage drop branch in the source bias circuit 20 includes at least two cascaded MOS transistors, and the number of the cascaded MOS transistors in the voltage drop branches with different voltage drop degrees is different.

Taking the source bias circuit 20 with two

voltage drop branches

201 and 202 with different voltage drop degrees as an example, the voltage drop branch 201 has two cascaded MOS transistors P11 and P12, a gate of the MOS transistor P11 is connected to the feedback signal AUTO _ SB, a source of the MOS transistor P11 is connected to the first power voltage VDD, a drain of the MOS transistor P11 is connected to the source of the MOS transistor P12, and a gate and a drain of the MOS transistor P12 are connected and connected to the output terminal a of the source bias circuit 20. The voltage drop branch 201 has three cascaded MOS transistors P21, P22, and P23, a gate of the MOS transistor P21 is connected to the inverted signal AUTO _ SBX, a source of the MOS transistor P21 is connected to the first power voltage VDD, a drain of the MOS transistor P21 is connected to the source of the MOS transistor P22, a gate and a drain of the MOS transistor P22 are connected to the source of the MOS transistor P23, and a gate and a drain of the MOS transistor P23 are connected to the output a of the source bias circuit 20. The conduction types of the MOS transistors P11, P12, P21, P22, and P23 are the same, for example, they are all PMOS transistors, and thus the two

voltage drop branches

201 and 202 are not turned on simultaneously under the control of the mutually inverted signals AUTO _ SB and AUTO _ SBX.

Specifically, when the feedback signal AUTO _ SB is at a low level "0", the inverted signal AUTO _ SBX is at a high level "1", the MOS transistor P11 is turned on, the MOS transistor P21 is turned off (i.e., turned off), the voltage drop branch 201 is opened, and the voltage drop branch 202 is closed, at this time, the source bias voltage VDDC output by the source bias circuit 20 is a voltage drop provided by the voltage drop branch 201, and is a lower gear. When the feedback signal AUTO _ SB is at a high level "1", the inverted signal AUTO _ SBX is at a low level "0", the MOS transistor P11 is turned off (i.e., turned off), the MOS transistor P21 is turned on, the voltage drop branch 201 is turned off, and the voltage drop branch 202 is turned on, at this time, the source bias voltage VDDC output by the source bias circuit 20 is a voltage drop provided by the voltage drop branch 202, and is at a higher gear.

It should be noted that after the system enters the sleep mode, the control circuit 40 may be powered off or not operated because the control signal ABS _ ON is low, so as to reduce the static power consumption of the system.

In summary, the sram circuit of the present embodiment has a simple structure, a small additional area, and easy modularization and standardization. And the control circuit is added ON the basis of the existing circuit, so that the source bias voltage VDDC output by the source bias circuit is compared with the reference voltage VREF under the control of the control signal ABS _ ON, and the self-adaptive adjustment of the source bias voltage VDDC output by the source bias circuit is realized according to the comparison result, thereby dynamically reducing the static power consumption of the SRAM system and ensuring the data safety of the SRAM system. In addition, the detection of the source bias voltage VDDC may be performed only once before the SRAM system enters the sleep mode, and the power supply of the control circuit 40 may be cut off after the sleep mode is entered, thereby not causing excessive static power consumption.

Based on the same inventive concept, an embodiment of the present invention further provides an electronic product, which includes the sram circuit according to the present invention. The electronic product adopts the static random access memory circuit, so the static power consumption is low.

In the above embodiments, the reference voltage VREF may be provided by any suitable circuit such as a bandgap reference circuit. The control circuit 40 may be implemented by using another sense amplifier circuit, may be implemented by using any other suitable comparison circuit besides a sense amplifier, and the source bias circuit 20 may be implemented by using any suitable circuit, and the specific structures of the control circuit 40 and the source bias circuit 20 are not limited to the specific structure examples in the embodiments described above.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims

1. A static random access memory circuit, comprising:

a memory array for storing data;

a source bias circuit, coupled to the memory array, for providing a source bias voltage to the memory array;

2. The static random access memory circuit of claim 1, wherein the control circuit includes a sense amplifier.

3. The static random access memory circuit of claim 2, wherein the sense amplifier comprises:

4. The SRAM circuit of claim 3, wherein the first switching cell comprises a first MOS transistor, and the second switching cell comprises a second MOS transistor; the grid electrodes of the first MOS tube and the second MOS tube are both connected to the control signal, the source electrode of the first MOS tube is connected to the source bias voltage, and the source electrode of the second MOS tube is connected to the reference voltage; the drain of the first MOS tube is coupled with the first port of the coupling inverting unit and one end of the output unit, and the drain of the second MOS tube is coupled with the second port of the coupling inverting unit and the other end of the output unit.

5. The SRAM circuit of claim 3, wherein the coupling inverter unit comprises third to sixth MOS transistors, a source of the third MOS transistor and a source of the fourth MOS transistor are both connected to a first power voltage for powering the control circuit, a source of the fifth MOS transistor and a source of the sixth MOS transistor are coupled, a drain of the third MOS transistor and a drain of the fifth MOS transistor are coupled and serve as a first port of the coupling inverter unit, a drain of the fourth MOS transistor and a drain of the sixth MOS transistor are coupled and serve as a second port of the coupling inverter unit, a gate of the third MOS transistor and a gate of the fifth MOS transistor are coupled and coupled to the second port, and a gate of the fourth MOS transistor and a gate of the sixth MOS transistor are coupled and coupled to the first port.

6. The static random access memory circuit of claim 3, wherein the output unit comprises: a first NAND logic circuit, a second NAND logic circuit, and a first inverting logic circuit; the first input end of the first NAND logic circuit is coupled with the second port of the coupling inverting unit, and the second input end of the first NAND logic circuit is coupled with the output end of the second NAND logic circuit and the input end of the first inverting logic circuit; a first input end of the second NAND logic circuit is coupled with an output end of the first NAND logic circuit, and a second input end of the second NAND logic circuit is coupled with a first port of the coupling inverting unit; the output end of the first inverting logic circuit is coupled with the source biasing circuit.

7. The SRAM circuit of any one of claims 3-6, wherein the sense amplifier further comprises a pull-down switch unit coupled to the coupled inverting unit for turning on under control of the control signal to provide a second supply voltage to the coupled inverting unit.

8. The static random access memory circuit of claim 1, wherein the source bias circuit comprises:

the second inverting logic circuit is coupled to the output end of the control circuit and used for accessing the feedback signal and outputting an inverted signal inverted to the feedback signal;

9. The sram circuit of claim 8, wherein the voltage drop branch comprises at least two MOS transistors in cascade, and wherein the number of MOS transistors in cascade in voltage drop branches having different voltage drop degrees is different.

10. An electronic product comprising the sram circuit according to any one of claims 1 to 9.