CN115345101A - UVM-based chip register verification method - Google Patents
UVM-based chip register verification method Download PDFInfo
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- CN115345101A CN115345101A CN202210949098.XA CN202210949098A CN115345101A CN 115345101 A CN115345101 A CN 115345101A CN 202210949098 A CN202210949098 A CN 202210949098A CN 115345101 A CN115345101 A CN 115345101A
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- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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Abstract
The invention provides a verification method of a chip register based on UVM. The method comprises the following steps: configuring the sequence, after starting the verification sequence, taking a first value from the queue variable of the verification sequence, and reading and checking the first register by the value according to the reading and writing process corresponding to the front door mode, or according to the reading and writing process corresponding to the back door mode. If the data in the queue is not completely executed, taking a next value from the queue variable to continue reading, writing and checking, and if the data in the queue is completely executed, ending the access of the first register and accessing the next register; and ending the sequence until all registers are traversed. The sequence of the present invention is configured before being started, and the read-write verification of the traversal register can be completed. The workload of writing the read-write sequence of the register can be reduced, and the method has reusability and is convenient to use.
Description
Technical Field
The invention relates to the technical field of integrated circuit verification, in particular to a verification method of a chip register based on UVM.
Background
In the UVM verification method of the chip Register, the concept of a Register architecture model (RAL) is introduced, and the Register model provides tasks such as mirror and update, which can complete the interaction of the Register model and related registers in a DUT in batches, so that a verifier can organize and configure the registers better. The prior art may support the generation of a register model from a descriptive document of registers, which is not specifically set forth herein. With the register model, the register can be read and written by front door access and back door access. The front door access is to send a read-write instruction on the bus through the analog cpu to perform read-write operation; the back door access operation is to change the value of the register directly through hierarchical reference without reading and writing through the bus.
For register verification, the UVM has some sequence built in. However, the built-in sequence often has limitations in practical applications, such as an inability to specify multiple different write data and different access manners. The UVM built-in sequence can not flexibly meet the requirements of various verification registers, so that a verifier still needs to write a sequence for traversing the register verification by himself. Different designs require the validation personnel to perform repetitive labor, which is inefficient.
Disclosure of Invention
The invention mainly aims to provide a verification method of a chip register based on UVM, which does not need a verifier to compile a sequence traversing the register verification, can reduce repetitive labor and improve efficiency.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
compared with the prior art, the invention breaks through the limitation of the verification sequence of the built-in UVM register, creates a sequence which can write any number in unlimited number and can automatically traverse the verification register, and the front door and the back door can be accessed selectively. The use is as convenient as a built-in sequence of the UVM, a user can not care about the content of the sequence, only needs to correctly configure and start the sequence when in use, and various different register verification requirements are flexibly met. The sequence can reduce the workload of writing the register verification sequence, has strong operability and reusability.
The technical scheme of the invention is as follows:
if the access mode of the configuration sequence is a front door mode, after the verification sequence is started, a first value is taken from a queue variable of the verification sequence, and the first value is written into a first register through the front door mode. The value of the first register is read back and checked in a front gate manner.
If the access mode of the configuration sequence is a back door mode, after the verification sequence is started, a first value is taken from a queue variable of the verification sequence, and the first value is written into a first register in a front door mode. And reading back the value of the first register in a back gate mode and verifying the value, writing the first value into the first register in a back gate mode, and reading back the value of the first register in a front gate mode and verifying the value.
If the data in the queue is not completely executed, taking a next value from the queue variable to continue reading, writing and checking, and if the data in the queue is completely executed, ending the access of the first register and accessing the next register; and ending the sequence until all registers are traversed.
The above technical solution further includes:
adding a source code of the verification sequence to a verification environment of the UVM and creating an instance of the verification sequence;
specifying a register model RAL of the verification sequence;
assigning values to variables corresponding to the access modes in the verification sequence;
assigning values to queue variables in the validation sequence;
the verification sequence is initiated.
A register model RAL specifying a verification sequence, comprising: and pointing a pointer of a register model RAL type in the verification sequence to the created register model RAL in the verification environment of the UVM.
Assigning values to variables corresponding to the access modes in the verification sequence, wherein the assigned contents comprise: front door access and rear door access.
Assigning values to queue variables in the verification sequence, including:
writing write data of a verification register in a queue type variable of the verification sequence, wherein the number of the write data is one or more;
and sequentially taking values from the queue variables in the execution process of the verification sequence, and reading, writing and checking registers until all members of the queue are traversed.
Drawings
Fig. 1 is a schematic diagram of a sequence configuration flow according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a sequence read-write flow according to an embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein.
Referring to fig. 1, the configuration process of the verification sequence includes: adding a source code of a verification sequence to a verification environment of the UVM and creating an instance of the verification sequence; specifying a register model RAL of the verification sequence; assigning values to variables corresponding to the access modes in the verification sequence; assigning values to queue variables in the validation sequence; a verification sequence is initiated.
Assigning values to variables corresponding to the access modes in the verification sequence, wherein the assigned contents comprise: front door access and rear door access.
Wherein assigning values to queue variables in the validation sequence comprises: and writing the write data of the verification register in the queue type variable of the verification sequence, wherein the number of the written write data is one or more. And sequentially taking values from the queue variables in the execution process of the verification sequence, and reading, writing and checking registers until all members of the queue are traversed.
For example, the actual configuration process of the sequence includes the following processes.
1) Adding the source code of the sequence (multi _ reg _ access _ seq) to the UVM verification environment and creating an instance of the verification sequence;
multi_reg_access_seq reg_seq；
reg_seq＝new(“reg_seq”)；
2) Pointing a pointer of a register model RAL type in the sequence to a register model RAL already established in the environment;
reg_seq.model＝XXX.XXX.p_rm；
3) Assigning values to variables determining front and back door access modes in the sequence;
access _ op _ e = Front or Backdoor;
4) Assigning values to queue variables in the sequence, for example, continuously writing 4 values: 16'h0000, 16' h5555, 16'hAAA, 16' hFFFF;
reg_seq.data[$]＝{16’h0000,16’h5555,16’hAAAA,16’hFFFF}；
5) A start sequence;
reg_seq.start(null)。
referring to fig. 2, the read-write flow of the sequence includes:
if the access mode of the configuration sequence is a front door mode, after the verification sequence is started, a first value is taken from a queue variable of the verification sequence, and the first value is written into a first register through the front door mode. The value of the first register is read back and checked in a front gate manner.
If the access mode of the configuration sequence is a back door mode, after the verification sequence is started, a first value is taken from a queue variable of the verification sequence, and the first value is written into a first register in a front door mode. And reading back the value of the first register in a back gate mode and checking, writing the first value into the first register in a back gate mode, and reading back the value of the first register in a front gate mode and checking.
If the data in the queue is not completely executed, taking a next value from the queue variable to continue reading, writing and checking, and if the data in the queue is completely executed, ending the access of the first register and accessing the next register;
and ending the sequence until all registers are traversed.
For example, the read/write flow within the sequence includes the following flows:
1) After the sequence is started, a value is taken out from the queue data [ $ ], and the value is written into a first register in a front door mode;
2) Judging access _ op _ e;
if access _ op _ e = = Front, the value of the first register is read back by Front door mode;
if access _ op _ e = = background, reading back the value of the first register in a back gate mode; writing the data into a first register in a back door mode, and reading back the value of the first register in a front door mode;
3) And if the queue data [ $ ] has only one member, the sequence is ended. If the queue data [ $ ] has a plurality of members, the process of 1) -2) is continuously repeated, wherein the process 1) sequentially fetches the data from the queue until all the values in the queue are traversed;
4) And repeating the process of 1) -3) for the next register until all the readable and writable registers in the register model are traversed.
Claims (5)
1. A verification method of a chip register based on UVM is characterized by comprising the following steps:
if the access mode of the configuration sequence is a front door mode, after the verification sequence is started, a first value is taken from a queue variable of the verification sequence, the first value is written into a first register in the front door mode, and the value of the first register is read back in the front door mode and is checked;
if the access mode of the configuration sequence is a back door mode, after the verification sequence is started, a first value is taken from a queue variable of the verification sequence, the first value is written into a first register in a front door mode, the value of the first register is read back in a back door mode and is checked, the first value is written into the first register in the back door mode, and the value of the first register is read back in a front door mode and is checked;
if the data in the queue is not completely executed, taking a next value from the queue variable to continue reading, writing and checking, and if the data in the queue is completely executed, ending the access of the first register and accessing the next register; and ending the sequence until all registers are traversed.
2. The method of claim 1, wherein the method further comprises:
adding a source code of the verification sequence to a verification environment of the UVM and creating an instance of the verification sequence;
specifying a register model RAL for the validation sequence;
assigning values to variables corresponding to the access modes in the verification sequence;
assigning values to queue variables in the validation sequence;
the verification sequence is initiated.
3. The method of claim 2, wherein specifying a register model of the validation sequence, RAL, comprises:
and pointing a pointer of a register model RAL type in the verification sequence to the created register model RAL in the verification environment of the UVM.
4. The method of claim 2, wherein a value is assigned to a variable corresponding to the access mode in the verification sequence, the assigned value comprising: front door access and rear door access.
5. The method of claim 2, wherein assigning values to queue variables in the validation sequence comprises:
writing write data of a verification register in a queue type variable of the verification sequence, wherein the number of the write data is one or more; and sequentially taking values from the queue variables in the execution process of the verification sequence, and reading, writing and checking registers until all members of the queue are traversed.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116127886A (en) * | 2023-04-12 | 2023-05-16 | 北京燧原智能科技有限公司 | Verification method and device for memory circuit |
| CN116956789A (en) * | 2023-09-19 | 2023-10-27 | 芯耀辉科技有限公司 | Method, computing device and medium for accessing register back door |
| CN116974813A (en) * | 2023-09-25 | 2023-10-31 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
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2022
- 2022-08-09 CN CN202210949098.XA patent/CN115345101A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116127886A (en) * | 2023-04-12 | 2023-05-16 | 北京燧原智能科技有限公司 | Verification method and device for memory circuit |
| CN116956789A (en) * | 2023-09-19 | 2023-10-27 | 芯耀辉科技有限公司 | Method, computing device and medium for accessing register back door |
| CN116956789B (en) * | 2023-09-19 | 2023-12-12 | 芯耀辉科技有限公司 | Method, computing device and medium for accessing register back door |
| CN116974813A (en) * | 2023-09-25 | 2023-10-31 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
| CN116974813B (en) * | 2023-09-25 | 2024-04-19 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
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