CN115333546A - Universal polar code-oriented multi-bit parallel list decoding method and device - Google Patents

Universal polar code-oriented multi-bit parallel list decoding method and device Download PDF

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CN115333546A
CN115333546A CN202210785545.2A CN202210785545A CN115333546A CN 115333546 A CN115333546 A CN 115333546A CN 202210785545 A CN202210785545 A CN 202210785545A CN 115333546 A CN115333546 A CN 115333546A
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metric values
decoding
path metric
path
minimum
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管武
王志君
罗汉青
梁利平
罗平
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Beijing University of Posts and Telecommunications
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes

Abstract

The application provides a universal multi-bit parallel list decoding method facing to a polar code, which comprises the following steps: acquiring a polarization code to be decoded and dividing the polarization code into M bit groups; sequentially putting the M bit groups into a decoder for decoding to obtain a decoding result, wherein the decoding result comprises the following steps: the current M bit group is processed with parallel measurement calculation to obtain 2 M L path metrics; constructing a master-slave sequencing network of the decoder; exchanging path metric values selected in a master-slave sequencing network to obtain L path metric values; taking the obtained M-bit values corresponding to the L paths as the decoding judgment of the path, and further taking the M-bit values as the decoding result of the current M-bit group; and acquiring decoding results of all M bit groups, and then taking the minimum path of the minimum L paths in the decoding results of all M bit groups as a final decoding path, wherein the sequence of all M bit values corresponding to the path is taken as the decoding result of the polarization code. The invention adopting the scheme solves the technical problems of complexity and performance of list sequencing of polar code decoding.

Description

Universal polar code-oriented multi-bit parallel list decoding method and device
Technical Field
The present application relates to the field of information processing technologies, and in particular, to a general method and apparatus for decoding a polarization-code-oriented multi-bit parallel list.
Background
Polar codes are the latest excellent channel error correction coding technology, have been applied in the 5G mobile communication standard, and are one of the candidate channel coding technologies for future 6G mobile communication. Polarization codes are increasingly used.
In the polar code decoding, the list elimination decoding method is the optimal decoding method and has the best performance. In the process of list elimination decoding, the path metrics calculated by each list need to be sorted, so as to select the list with the optimal metric. In the typical polar code decoding, the number of candidate lists cannot be less than 16, and certainly, in order to reduce the performance loss, the larger the list is, the better the list is. However, the number of lists is too large, the sorting complexity is high, the occupation period is long, and the decoding rate of the polar code is greatly reduced.
In order to solve the problems of large list complexity and long occupation period, a plurality of methods are provided. The first method is to reduce the number of lists, such as to reduce the number of lists below 8, such as single list, 2 list or 4 list; this approach reduces the number of lists, reduces complexity, but greatly reduces performance. The second method is an approximate sorting method, namely, the metric values of each list are represented by the highest two bits of each list, and the precision of the values of each list is reduced, so that a comparator with a small bit width can be used for realizing sorting comparison, the calculation complexity is reduced, and the calculation speed is increased; this method also results in too low precision and inaccurate ordering, which leads to a loss of decoding performance.
Disclosure of Invention
The present application is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, a first objective of the present application is to provide a universal polar code-oriented multi-bit parallel list decoding method, which solves the technical problem that the complexity and performance of the list ordering of polar code decoding in the existing method cannot be guaranteed at the same time, and realizes dual guarantee of the ordering complexity and performance.
A second objective of the present application is to provide a general apparatus for decoding a polar code-oriented multi-bit parallel list.
A third object of the present application is to propose a computer device.
A fourth object of the present application is to propose a non-transitory computer-readable storage medium.
To achieve the above object, an embodiment of the first aspect of the present application provides a general method for decoding a multi-bit parallel list oriented to a polar code, including: obtaining a polarization code to be decoded, and dividing the polarization code into at least one M bit group; sequentially putting the divided M bit groups into a decoder for decoding to obtain a decoding result; the method for decoding the M bit groups includes the following steps that the list size of a decoder is L, the divided M bit groups are sequentially placed into the decoder for decoding, and a decoding result is obtained, wherein the method includes the following steps: performing parallel metric calculation on the M bit group currently put into the decoder to obtain 2 M L path metrics; constructing a main sequencing network of a decoder, and selecting the minimum L path metric values in the main sequencing network; constructing a slave sequencing network of the decoder, and selecting N path metric values which are the minimum in the slave sequencing network, wherein N is a list size parameter of the decoder; exchanging path metric values selected in a master-slave sequencing network to obtain final L path metric values; taking the final M-bit values corresponding to the L paths as the decoding judgment of the path, and taking the decoding judgment as the decoding result of the current M-bit group; and acquiring decoding results of all M bit groups, and then taking the minimum path of the minimum L paths in the decoding results of all M bit groups as a final decoding path, wherein the sequence of all M bit values corresponding to the path is taken as the decoding result of the polarization code.
According to the general multi-bit parallel list decoding method for the polar codes, the complexity is reduced through two-stage comparison of a master stage and a slave stage; meanwhile, by using the secondary sorting, the main sorting ensures accurate sorting and small performance loss, the secondary sorting reduces the sorting complexity and improves the decoding rate.
Optionally, in an embodiment of the present application, for a decoder with a list size of L, the master ordering network has 2L path metric values in total, wherein the master ordering network is formed by the path metric values
Figure BDA0003731700270000021
The structure of the utility model is that the material,
and sorting the 2L path metric values, and extracting L path metric values with the minimum path metric values as the minimum L path metric values of the main sorting network.
Optionally, in an embodiment of the present application, constructing a secondary ranking network, and selecting the N path metric values that are the smallest in the secondary ranking network, includes:
decoding and selecting a parameter N according to a multi-bit parallel list of the polarization codes;
constructing a secondary ranking network based on the selected parameter N, wherein the secondary ranking network is formed from the path metric values
Figure BDA0003731700270000022
Forming;
among the NL path metric values included from the ranking network, the smallest N path metric values are found.
Optionally, in an embodiment of the present application, exchanging N path metric values in a master-slave ranking network to obtain the minimum L path metric values includes:
sorting the maximum N path metric values in the extracted L minimum path metric values and the selected minimum N path metric values to obtain the minimum N path metric values after re-sorting;
and combining the unordered path metric values in the extracted L minimum path metric values with the minimum N path metric values after reordering to obtain final L path metric values.
In order to achieve the above object, a second embodiment of the present invention provides a general decoding apparatus for a polar code-oriented multi-bit parallel list, including a data processing module and a decoding module, wherein:
the data processing module is used for acquiring a polarization code to be decoded and dividing the polarization code into at least one M bit group;
the decoding module is used for sequentially putting the divided M bit groups into a decoder for decoding to obtain a decoding result;
wherein, the list size of the decoder is L, and the decoding module is specifically configured to:
performing parallel metric calculation on the M bit group currently put into the decoder to obtain 2 M L path metrics;
constructing a main sorting network of a decoder, and selecting the minimum L path metric values in the main sorting network;
constructing a slave sequencing network of a decoder, and selecting N path metric values which are the minimum in the slave sequencing network, wherein N is a list size parameter of the decoder;
exchanging path metric values selected in a master-slave sequencing network to obtain final L path metric values;
taking the final M-bit values corresponding to the L paths as the decoding judgment of the path, and taking the decoding judgment as the decoding result of the current M-bit group;
and acquiring decoding results of all M bit groups, and then taking the minimum path of the minimum L paths in the decoding results of all M bit groups as a final decoding path, wherein the sequence of all M bit values corresponding to the path is taken as the decoding result of the polarization code.
In order to achieve the above object, a third embodiment of the present invention provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the computer device implements the above general method for decoding a multi-bit parallel list of polar codes.
In order to achieve the above object, a fourth aspect of the present invention provides a non-transitory computer-readable storage medium, wherein instructions of the storage medium, when executed by a processor, can perform the above general polar-code-oriented multi-bit parallel list decoding method.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic flowchart of a general method for decoding a multi-bit parallel list oriented to a polar code according to an embodiment of the present application;
FIG. 2 is a decoding process diagram according to an embodiment of the present application;
FIG. 3 is a diagram of a master-slave switching sequencing network according to an embodiment of the present application;
fig. 4 is a simulation diagram of decoding performance of a list of M =4 lower polar codes according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a general polar code-oriented multi-bit parallel list decoding apparatus according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The following describes a general polar code-oriented multi-bit parallel list decoding method and apparatus according to an embodiment of the present application with reference to the drawings.
Fig. 1 is a flowchart illustrating a general polar code-oriented multi-bit parallel list decoding method according to an embodiment of the present application.
As shown in fig. 1, the general polar code-oriented multi-bit parallel list decoding method includes the following steps:
step 101, acquiring a polarization code to be decoded, and dividing the polarization code into at least one M bit group;
and 102, sequentially putting the divided M bit groups into a decoder for decoding to obtain a decoding result.
The general multi-bit parallel list decoding method facing the polar codes reduces complexity through two-stage comparison of a master stage and a slave stage; meanwhile, the secondary sorting is used, the main sorting ensures accurate sorting and small performance loss, the secondary sorting reduces the sorting complexity and improves the decoding rate. The invention reduces the complexity of a sequencing network in the multi-bit parallel list decoding of the polarization code, is easy to realize in engineering, and has the advantages of low hardware cost and high hardware throughput.
In the present application, the process of sequentially placing the divided M bit groups into a decoder for decoding to obtain a decoding result is shown in fig. 2, and includes:
s1, performing M-bit parallel metric calculation on L paths, wherein 2ML path metrics are calculated;
s2, constructing a main sequencing network;
s3, constructing a slave sequencing network;
s4, exchanging N path metric values in the master-slave sequencing network to obtain the minimum L path metric values;
s5, taking the M bit values corresponding to the minimum L paths as the decoding judgment of the paths;
s6, judging whether all bits finish decoding or not; if yes, entering S7; otherwise, entering S1 to decode the next group of M bits;
and S7, taking the minimum path in the minimum L paths as a final decoding path, and taking the sequence of all M-bit values corresponding to the path as a decoding result of the polarization code.
Optionally, in an embodiment of the present application, the sorting structure is as shown in fig. 3, for polar code M-bit parallel list decoding, splitting in decoding generates 2 M L path metrics using an ordered matrix
Figure BDA0003731700270000041
Figure BDA0003731700270000042
To show that each list selects the minimum 2 path metric values
Figure BDA0003731700270000043
For a decoder with a list size L, the main ordering network has 2L path metric values in total,
and sorting the constructed element set with 2L path metric values, and extracting the L path metric values with the minimum path metric value.
Optionally, in an embodiment of the present application, constructing a secondary ranking network, and selecting the minimum N path metric values from the ranking network includes:
selecting proper N parameters to ensure that the decoding performance of the multi-bit parallel list of the polarization codes is not reduced;
parameter selection, L =8,n =2; l =32,n =4; the selected parameters are suitable for M =2,4,8 bit parallel decoding; where the coding performance of M =4 is shown in fig. 4;
constructing a secondary sorting network according to the selected N parameters, and selecting a path metric value for a polar code M-bit parallel list decoding algorithm
Figure BDA0003731700270000051
To form a slave sequencing network;
in constructing a set of NL path metric value elements, the smallest N path metric values are found.
Optionally, in an embodiment of the present application, exchanging N path metric values in a master-slave ordering network to obtain L minimum path metric values includes:
the switching network sorts the maximum N path metric values in the selected L minimum path metric values and the minimum N path metric values to find the minimum N path metric values;
and combining the selected (L-N) minimum path metric values with the obtained N path metric values to obtain final L path metric values.
In order to implement the above embodiments, the present application further provides a general decoding apparatus for a polar code-oriented multi-bit parallel list.
Fig. 5 is a schematic structural diagram of a general polar code-oriented multi-bit parallel list decoding apparatus according to an embodiment of the present application.
As shown in fig. 5, the general decoding apparatus for polar code-oriented multi-bit parallel list comprises a data processing module and a decoding module, wherein:
the data processing module is used for acquiring a polarization code to be decoded and dividing the polarization code into at least one M bit group;
the decoding module is used for sequentially putting the divided M bit groups into a decoder for decoding to obtain a decoding result;
wherein, the list size of the decoder is L, and the decoding module is specifically configured to:
performing parallel metric calculation on the M bit group currently put into the decoder to obtain 2 M L path metrics;
constructing a main sorting network of a decoder, and selecting the minimum L path metric values in the main sorting network;
constructing a slave sequencing network of the decoder, and selecting N path metric values which are the minimum in the slave sequencing network, wherein N is a list size parameter of the decoder;
exchanging path metric values selected in a master-slave sequencing network to obtain final L path metric values;
taking the final M-bit values corresponding to the L paths as the decoding judgment of the path, and taking the decoding judgment as the decoding result of the current M-bit group;
and acquiring decoding results of all the M bit groups, and then taking the minimum path of the minimum L paths in the decoding results of all the M bit groups as a final decoding path, wherein the sequence of all M bit values corresponding to the path is taken as the decoding result of the polarization code.
It should be noted that the foregoing explanation on the embodiment of the universal polarization code-oriented multi-bit parallel list decoding method is also applicable to the universal polarization code-oriented multi-bit parallel list decoding apparatus of this embodiment, and is not repeated here.
In order to implement the foregoing embodiments, the present invention further provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method described in the foregoing embodiments is implemented.
In order to implement the above embodiments, the present invention also proposes a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of the above embodiments.
In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Further, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried out in the method of implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are exemplary and should not be construed as limiting the present application and that changes, modifications, substitutions and alterations in the above embodiments may be made by those of ordinary skill in the art within the scope of the present application.

Claims (10)

1. A universal polar code-oriented multi-bit parallel list decoding method is characterized by comprising the following steps:
acquiring a polarization code to be decoded, and dividing the polarization code into at least one M bit group;
sequentially putting the divided M bit groups into a decoder for decoding to obtain a decoding result;
the method for decoding the M bit groups includes the following steps that the list size of the decoder is L, the divided M bit groups are sequentially placed into the decoder for decoding, and a decoding result is obtained, wherein the method includes the following steps:
performing parallel metric calculation on the M bit group currently put into the decoder to obtain 2 M L path metrics;
constructing a main sorting network of the decoder, and selecting the minimum L path metric values in the main sorting network;
constructing a slave sequencing network of the decoder, and selecting N path metric values which are the minimum in the slave sequencing network, wherein N is a list size parameter of the decoder;
exchanging path metric values selected in a master-slave sequencing network to obtain final L path metric values;
taking the value of M bits corresponding to the final L paths as the decoding judgment of the path, and taking the decoding judgment as the decoding result of the current M bit group;
and acquiring decoding results of all M bit groups, and then taking the minimum path of the minimum L paths in the decoding results of all M bit groups as a final decoding path, wherein the sequence of all M bit values corresponding to the path is taken as the decoding result of the polarization code.
2. The method of claim 1 wherein for a decoder having a list size of L, there are 2L path metric values in total for a primary ranking network, wherein the primary ranking network is determined by the path metric values
Figure FDA0003731700260000011
The structure of the utility model is that the material,
and sorting the 2L path metric values, and extracting L path metric values with the minimum path metric values as the minimum L path metric values of the main sorting network.
3. The method of claim 1 wherein said constructing a ranked list of network from which to choose the smallest N path metric values comprises:
decoding and selecting a parameter N according to a multi-bit parallel list of the polarization codes;
constructing a secondary ranking network according to the selected parameter N, wherein the secondary ranking network is formed by path metric values
Figure FDA0003731700260000012
Forming;
and finding out the minimum N path metric values from the NL path metric values included in the sorting network.
4. The method of claim 1, wherein exchanging the N path metric values in the master-slave ranked network to obtain the smallest L path metric values comprises:
sorting the maximum N path metric values in the extracted L minimum path metric values and the selected minimum N path metric values to obtain the minimum N path metric values after re-sorting;
and combining the route metric values which are not sorted in the extracted L minimum route metric values with the N minimum route metric values after the re-sorting to obtain the final L route metric values.
5. A universal polar code-oriented multi-bit parallel list decoding device is characterized by comprising a data processing module and a decoding module, wherein:
the data processing module is used for acquiring a polarization code to be decoded and dividing the polarization code into at least one M bit group;
the decoding module is used for sequentially putting the divided M bit groups into a decoder for decoding to obtain a decoding result;
wherein the list size of the decoder is L, and the decoding module is specifically configured to:
performing parallel metric calculation on the M bit group currently put into the decoder to obtain 2 M L path metrics;
constructing a main sorting network of the decoder, and selecting the minimum L path metric values in the main sorting network;
constructing a slave sequencing network of the decoder, and selecting the minimum N path metric values in the slave sequencing network, wherein N is a list size parameter of the decoder;
exchanging path metric values selected in a master-slave sequencing network to obtain final L path metric values;
taking the value of M bits corresponding to the final L paths as the decoding judgment of the path, and taking the decoding judgment as the decoding result of the current M bit group;
and acquiring decoding results of all M bit groups, and then taking the minimum path of the minimum L paths in the decoding results of all M bit groups as a final decoding path, wherein the sequence of all M bit values corresponding to the path is taken as the decoding result of the polarization code.
6. The apparatus of claim 5, wherein for a decoder with a list size L, there are 2L path metric values in total for a primary ranking network, wherein the primary ranking network is determined by the path metric values
Figure FDA0003731700260000021
The structure of the utility model is that the material,
and sorting the 2L path metric values, and extracting L path metric values with the minimum path metric values as the minimum L path metric values of the main sorting network.
7. The apparatus of claim 5, wherein the second extraction module is specifically configured to:
selecting a parameter N according to the decoding performance of the multi-bit parallel list of the polarization code;
constructing a secondary ranking network according to the selected parameter N, wherein the secondary ranking network is formed by path metric values m 3 1: : L N Forming;
and finding out the minimum N path metric values from the NL path metric values included in the sorting network.
8. The apparatus of claim 5, wherein the switching module is specifically configured to:
sorting the maximum N path metric values in the extracted L minimum path metric values and the selected minimum N path metric values to obtain the minimum N path metric values after re-sorting;
and combining the unordered path metric values in the extracted L minimum path metric values with the rearranged minimum N path metric values to obtain the final L path metric values.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1-4 when executing the computer program.
10. A non-transitory computer-readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the method of any one of claims 1-4.
CN202210785545.2A 2022-07-05 2022-07-05 Universal polar code-oriented multi-bit parallel list decoding method and device Pending CN115333546A (en)

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