CN115333525A - Clamping circuit structure - Google Patents
Clamping circuit structure Download PDFInfo
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- CN115333525A CN115333525A CN202211111550.1A CN202211111550A CN115333525A CN 115333525 A CN115333525 A CN 115333525A CN 202211111550 A CN202211111550 A CN 202211111550A CN 115333525 A CN115333525 A CN 115333525A
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- control signal
- source voltage
- tube
- field effect
- input end
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Abstract
The invention discloses a clamping circuit structure, which comprises a first field effect transistor and a second field effect transistor, wherein the first field effect transistor and the second field effect transistor comprise a common output end; the first field effect transistor comprises a first source voltage input end and a first control signal input end, and the second field effect transistor comprises a second source voltage input end and a second control signal input end; the first source voltage input end is connected with a first source voltage, the second source voltage input end is connected with a second source voltage, and the first control signal input end is connected with a first control signal; the second control signal input end is connected with a second control signal; the first source voltage and the second source voltage are clamping levels or input voltages, and the first source voltage and the second source voltage are different. The circuit structure of the invention provides great flexibility for the clamping circuit, and can adjust the low-end clamping level of the input signal according to specific requirements.
Description
Technical Field
The invention relates to a clamping circuit, in particular to a clamping circuit structure with adjustable clamping level.
Background
The clamping circuit is used for fixing a certain part of a level signal on a selected level, wherein the lowest output of the level signal is fixed on a certain fixed level by the clamping circuit, the low end of an input signal is clamped, and the clamping circuit is changed to be mostly applied to reasonable direct current bias point setting on a key bias circuit when the power supply voltage is adjusted in a wide range. In the prior art, a clamping method capable of adjusting a low-end clamping level and a corresponding circuit structure are not available.
Disclosure of Invention
In order to adjust the clamping level of the clamping circuit, the application provides a clamping circuit structure.
A clamp circuit structure includes a first field effect transistor and a second field effect transistor, the first and second field effect transistors including a common output; the first field effect transistor comprises a first source voltage input end and a first control signal input end, and the second field effect transistor comprises a second source voltage input end and a second control signal input end; the first source voltage input end is connected with a first source voltage, the second source voltage input end is connected with a second source voltage, and the first control signal input end is connected with a first control signal; the second control signal input end is connected with a second control signal; the first source voltage and the second source voltage are clamping levels or input voltages, and the first source voltage and the second source voltage are different.
Furthermore, the first field effect transistor and the second field effect transistor are both PMOS tubes.
Furthermore, both the first source voltage input end and the second source voltage input end are gates, and both the first control signal input end and the second control signal input end are sources when the first control signal input end and the second control signal input end are conducted; the grid electrode of the first PMOS tube is connected with the clamping level, and the source electrode of the first PMOS tube is connected with the input voltage when the first PMOS tube is conducted; the grid electrode of the second PMOS tube is connected with the input voltage, and the source electrode of the second PMOS tube is connected with the clamping level when the second PMOS tube is conducted; the first control signal is an input voltage and the second control signal is a clamp level.
Furthermore, the first field effect transistor and the second field effect transistor are both CMOS transistors, and each CMOS transistor comprises an upper tube and a lower tube.
Furthermore, the first control signal input end and the second control signal input end are both gates of an upper tube of the CMOS tube; the first control signal and the second control signal are processed signals processed according to the input voltage and the clamping level, and the signal values of the first control signal and the second control signal are opposite.
The CMOS transistor further comprises a comparator, a NOT gate logic circuit, a first CMOS transistor and a second CMOS transistor, wherein the first CMOS transistor and the second CMOS transistor comprise a common output end; the input end of the comparator is connected with a clamping level and an input voltage, the output end of the comparator is provided with one output end and two output ends, the output end of the one output end is respectively connected with a grid electrode of an upper tube in the second CMOS tube and a grid electrode of a lower tube in the first CMOS tube, and the two output ends are respectively connected with a grid electrode of an upper tube in the first CMOS tube and a grid electrode of a lower tube in the second CMOS tube through a NOT gate logic circuit.
Furthermore, the upper tube is a PMOS tube, and the lower tube is an NMOS tube.
The invention also discloses a bias circuit which comprises the clamping circuit structure.
The invention has the beneficial effects that:
the clamping circuit provides a solution with adjustable clamping level, and when the input voltage is lower than the clamping level, the output is the clamping level; when the input voltage is higher than the clamping level, the output is the input level; this provides great flexibility to the clamp circuitry, enabling the low end clamp level to be adjusted for the input signal according to specific needs; and when the clamping circuit structure is applied to adjusting a wide power supply voltage range, reasonable mainstream bias point setting can be carried out on a key bias circuit.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural view of example 1;
FIG. 2 is a schematic structural view of example 2;
FIG. 3 is a graph of the effect of the output of the clamp circuit;
FIG. 4 is a schematic structural view of embodiment 3.
Detailed Description
In order to make the purpose, features and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the embodiments described below are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The invention is further elucidated with reference to the drawings and the embodiments.
In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for convenience in describing the present application and for simplicity in description, but do not indicate or imply that the referenced devices or elements must be in a particular order and therefore should not be considered as limiting the present application.
Example 1
The present embodiment discloses a clamping circuit structure, as shown in fig. 1, the circuit structure includes: a first field effect transistor and a second field effect transistor.
The first field effect transistor and the second field effect transistor include a common output terminal.
The first field effect transistor comprises a first source voltage input end and a first control signal input end, and the second field effect transistor comprises a second source voltage input end and a second control signal input end;
the first source voltage input end is connected with a first source voltage, namely a clamping level, the second source voltage input end is connected with a second source voltage, namely an input voltage, and the first control signal input end is connected with a first control signal; the second control signal input end is connected with a second control signal.
The first source voltage and the second source voltage are clamping levels or input voltages, and the first source voltage and the second source voltage are different, that is, in other embodiments, the first source voltage may be an input voltage, and the second source voltage may be a clamping level.
The first field effect transistor is controlled to be switched on and off by the first control signal and the clamping level; the second control signal and the input voltage control the second field effect transistor to be turned on and off. The switching on and off of the field effect transistor are controlled by the first control signal, the second control signal, the clamping level and 4 electric signals of the input voltage together, so that only one of the two field effect transistors can be switched on, and the common output end outputs the source voltage of the switched-on field effect transistor, namely the input voltage or the clamping level.
The clamping level is adjustable. And controlling the output end to output the clamping level when the input voltage is lower than the clamping level, and outputting the input voltage by the output end when the input voltage is higher than the clamping level.
Example 2
In embodiment 1, when the field effect transistor is a PMOS transistor, the first control signal is an input voltage, and the second control signal is a clamp level, this embodiment discloses a clamp circuit structure including a pair of PMOS transistors, as shown in fig. 2.
The first and second source voltage input ends are both grids, and the first and second control signal input ends are both sources when being conducted; the grid electrode of the first PMOS tube MP1 is connected with a clamping level vref, and the source electrode of the first PMOS tube MP1 is connected with an input voltage vin when the first PMOS tube MP1 is conducted; the gate of the second PMOS transistor MP2 is connected to the input voltage vin, and the source of the second PMOS transistor MP2 is connected to the clamping level vref when it is turned on. The drains of MP1 and MP2 are connected to the output terminal vout in common.
When the input voltage vin is lower than the clamp level vref, the input path of the first PMOS transistor MP1 to the output is cut off, and the path of the clamp level vref to the output vout is connected to the second PMOS transistor MP 2; the output terminal vout outputs a clamping level vref, and the clamping level verf is adjustable and is a fixed value.
When the input voltage vin is higher than the clamp level vref, the path from the first PMOS transistor MP1 to the output is turned on, while the path from the clamp level vref to the output vout is turned off and the second PMOS transistor MP2 is turned off, so that the output vout outputs the input voltage vin and increases with the increase of vin.
The effect of the output circuit of this embodiment is shown in fig. 3, the clamp level can be adjusted to any fixed value, so that the low-end clamp level of the input signal can be adjusted as required.
Example 3
In embodiment 1, the field effect transistor is a CMOS transistor, the first control signal and the second control signal are processed signals processed according to the input voltage and the clamp level, and the signal values of the first control signal and the second control signal are opposite, and this embodiment discloses a clamp circuit structure including a pair of CMOS transistors, as shown in fig. 4.
The circuit comprises a comparator, a NOT gate logic circuit, a first CMOS tube and a second CMOS tube, C1 and C2, the first CMOS tube C1 and the second CMOS tube C2 comprise a common output end; the input end of the comparator is connected with the clamping level and the input voltage, the output end of the comparator is provided with one output end and two output ends, the output end of the one output end is respectively connected with the grid electrode of the upper tube of the second CMOS tube C2 and the grid electrode of the lower tube of the first CMOS tube C1, and the output end of the two output ends is respectively connected with the grid electrode of the upper tube of the first CMOS tube C1 and the grid electrode of the lower tube of the second CMOS tube C2 through the NOT-gate logic circuit.
In order to simplify the circuit, in this embodiment, the upper tube of the first and second CMOS transistors is a PMOS transistor, and the lower tube is an NMOS transistor.
When the input voltage vin is lower than the clamping level vref, the comparator outputs 1, one path of the output voltage passes through the NOT gate logic circuit to obtain a first control signal of 0, and the other path of the output voltage does not pass through the logic circuit to obtain a second control signal of 1;
the first control signal 0 is input into a P tube grid electrode in a first CMOS tube C1, in addition, a clamping level vref is input into an input end of the C1, the first CMOS tube C1 is conducted, and vref is conducted;
the second control signal 1 is input to a P-tube grid electrode in a second CMOS tube C2, and an input voltage vin lower than a clamping level is input to an input end of the second CMOS tube C2, and the second CMOS tube C2 is cut off, and vin is cut off;
therefore, when the input voltage vin is lower than the clamp level vref, the output terminal vout of the entire circuit outputs a clamp level verf. The clamping level verf is adjustable and is a fixed value.
When the input voltage vin is higher than the clamping level vref, the comparator outputs 0, one path of the output signal passes through the NOT gate logic circuit to obtain a first control signal of 1, and the other path of the output signal does not pass through the logic circuit to obtain a second control signal of 0;
the first control signal 1 is input to the P tube grid of the first CMOS tube C1, and the input end of C1 inputs a clamping level vref lower than the input voltage vin, the first CMOS tube C1 is cut off, vref is cut off
A second control signal 0 is input to a gate of a P-transistor in the second CMOS transistor C2, and an input voltage vin is input to an input terminal of the second CMOS transistor C2, and the second CMOS transistor C2 is turned on and vin is turned on;
therefore, when the input voltage vin is higher than the clamp level vref, the output terminal vout of the entire circuit outputs the input voltage vin, and increases as vin increases.
The effect of the output circuit of this embodiment is shown in fig. 3, the clamp level can be adjusted to any fixed value, so that the low-end clamp level of the input signal can be adjusted as required.
Example 4
This embodiment provides a bias circuit including the clamp circuit structure described in embodiment 2 or 3.
When the clamp circuit structure described in embodiment 2 or 3 is used to adjust a wide power supply voltage range, reasonable dc bias point setting can be performed at a key bias circuit.
In the several embodiments provided in the present application, it should be understood that the disclosed structure may be implemented in other manners, and the above-described structural embodiments are merely illustrative, for example, the division of the modules or units is only a logical division, and other divisions may be implemented in practice, for example, multiple units or components may be combined or integrated into another device, or some features may be omitted, or not implemented.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A clamping circuit structure is characterized by comprising a first field effect transistor and a second field effect transistor, wherein the first field effect transistor and the second field effect transistor comprise a common output end; the first field effect transistor comprises a first source voltage input end and a first control signal input end, and the second field effect transistor comprises a second source voltage input end and a second control signal input end; the first source voltage input end is connected with a first source voltage, the second source voltage input end is connected with a second source voltage, and the first control signal input end is connected with a first control signal; the second control signal input end is connected with a second control signal; the first source voltage and the second source voltage are clamping levels or input voltages, and the first source voltage and the second source voltage are different.
2. The clamping circuit structure of claim 1, wherein the first and second field effect transistors are both PMOS transistors.
3. The clamping circuit structure of claim 2, wherein the first and second source voltage input terminals are both gates, and the first and second control signal input terminals are both sources when conducting; the grid electrode of the first PMOS tube is connected with the clamping level, and the source electrode of the first PMOS tube is connected with the input voltage when the first PMOS tube is conducted; the grid electrode of the second PMOS tube is connected with the input voltage, and the source electrode of the second PMOS tube is connected with the clamping level when the second PMOS tube is conducted; the first control signal is an input voltage and the second control signal is a clamp level.
4. The clamp circuit structure of claim 1, wherein the first and second field effect transistors are both CMOS transistors, the CMOS transistors comprising an upper tube and a lower tube.
5. The clamping circuit structure of claim 4, wherein the first and second control signal inputs are both gates of upper transistors of the CMOS transistor; the first control signal and the second control signal are processed signals processed according to the input voltage and the clamping level, and the signal values of the first control signal and the second control signal are opposite.
6. The clamp circuit structure of claim 5, comprising a comparator, a not gate logic circuit, and first and second CMOS transistors, the first and second CMOS transistors including a common output; the input end of the comparator is connected with a clamping level and an input voltage, the output end of the comparator is provided with one output end and two output ends, the output end of the one output end is respectively connected with a grid electrode of an upper tube in the second CMOS tube and a grid electrode of a lower tube in the first CMOS tube, and the two output ends are respectively connected with a grid electrode of an upper tube in the first CMOS tube and a grid electrode of a lower tube in the second CMOS tube through a NOT gate logic circuit.
7. The clamp circuit structure of claim 6, wherein the upper transistors are PMOS transistors and the lower transistors are NMOS transistors.
8. A bias circuit comprising the clamp circuit structure of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211111550.1A CN115333525A (en) | 2022-09-13 | 2022-09-13 | Clamping circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211111550.1A CN115333525A (en) | 2022-09-13 | 2022-09-13 | Clamping circuit structure |
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| Publication Number | Publication Date |
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| CN115333525A true CN115333525A (en) | 2022-11-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211111550.1A Pending CN115333525A (en) | 2022-09-13 | 2022-09-13 | Clamping circuit structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116489289A (en) * | 2023-06-16 | 2023-07-25 | 杭州雄迈集成电路技术股份有限公司 | Digital pre-clamping method and device for coaxial video signals |
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2022
- 2022-09-13 CN CN202211111550.1A patent/CN115333525A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116489289A (en) * | 2023-06-16 | 2023-07-25 | 杭州雄迈集成电路技术股份有限公司 | Digital pre-clamping method and device for coaxial video signals |
| CN116489289B (en) * | 2023-06-16 | 2023-11-21 | 浙江芯劢微电子股份有限公司 | Digital pre-clamping method and device for coaxial video signals |
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