CN115332331A - Negative capacitance gate-all-around source overlap tunneling field effect transistor - Google Patents
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- 230000005641 tunneling Effects 0.000 title claims abstract description 41
- 230000005669 field effect Effects 0.000 title claims abstract description 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 15
- 230000000694 effects Effects 0.000 claims abstract description 13
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 239000002210 silicon-based material Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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Abstract
The invention discloses a negative capacitance ring gate source electrode overlapping tunneling field effect transistor. According to the invention, the silicon-germanium heterojunction is formed on the contact surface of the source electrode and the channel, the negative capacitance effect is generated through the ferroelectric medium layer, the grid electrode extends towards the source electrode to form the source electrode overlapping region, the band tunneling probability at the heterojunction is further improved through the adjustable thickness of the ferroelectric medium layer and the adjustable length of the source electrode overlapping region, the conduction current is improved, and the defect of insufficient driving capability of the existing GAA-TFET is effectively overcome.
Description
Technical Field
The invention belongs to the technical field of novel nano semiconductor information devices, and particularly relates to a device structure for improving the driving current of a gate-all tunneling field effect transistor (GAA-TFET) by combining gate source overlapping (namely extending a gate to a source), a silicon-germanium heterojunction and a negative capacitance effect.
Background
With the integration of the nanoscale CMOS chip becoming higher and higher, the power consumption of the chip becomes an urgent problem to be solved, and the main method for reducing the power consumption is to make the CMOS device have better switching characteristics, which mainly depend on the size of the sub-threshold swing (SS). Because the CMOS transistor can not break through the Boltzmann limit at room temperature, namely SS can not be reduced below 60mV/decade, the power consumption of the traditional CMOS device is difficult to be reduced continuously.
A negative capacitance transistor (NCFET) reduces SS by the negative capacitance effect of the ferroelectric material, and can solve this problem as one of the methods. Another promising device is a Tunneling Field Effect Transistor (TFET), which causes carriers to tunnel from the source to the channel by band-to-band tunneling to generate a current. Due to different conduction mechanisms of devices, the TFET can easily break through the Boltzmann limit to reduce SS to below 60 mV/decade. However, TFETs are characterized by low off-state and on-state currents, resulting in weak drive capabilities, limiting their future applications. Also, after CMOS technology enters the 5nm node, the size of the transistor gradually approaches its physical limit.
Gate-all-around field effect transistors (GAA-FETs) are mainstream CMOS devices because they have stronger gate control capability, instead of fin field effect transistors (finfets). Therefore, gate-all-around tunneling field effect transistors (GAA-TFETs) are a strong competitor to ultra-low power CMOS devices facing sub-5 nm nodes. However, the existing device structure and mechanism still cannot effectively solve the problem of weak GAA-TFET driving capability. Therefore, the driving current of the tunneling field effect transistor is improved by combining the negative capacitance effect, the silicon-germanium heterojunction, the grid source overlapping and the gate-all-around structure. On the premise of ensuring other electrical properties of the tunneling field effect transistor, the driving capability of the GAA-TFET device is improved through partial change of the device structure.
Disclosure of Invention
The invention provides a novel CMOS device structure aiming at the driving capability of the GAA-TFET, namely: the source electrode is made of germanium materials, the channel and the drain electrode are made of silicon materials, a silicon-germanium heterojunction is formed on the contact surface of the channel and the source electrode, a ferroelectric dielectric layer is added between a grid oxide layer medium and a grid metal layer to generate a negative capacitance effect so as to improve the surface potential of the channel of the device, and the grid electrode extends towards the source electrode to form a source electrode overlapping region (SOL) structure, so that the driving capability of the device is improved under the combined action of multiple effects.
The invention comprises a source electrode, a channel, a drain electrode and a grid electrode, and is characterized in that: the source electrode is made of germanium materials, and the channel and the drain electrode are made of silicon materials; forming a silicon-germanium heterojunction on the contact surface of the channel and the source electrode, and the silicon-germanium heterojunction is used for increasing the tunneling area and the tunneling probability; adding a ferroelectric dielectric layer between an oxide layer dielectric of the grid and a metal layer of the grid for generating a negative capacitance effect and improving the surface potential of a channel; the grid electrode extends to the source electrode to form an active electrode overlapping area; and also to increase the tunneling area and tunneling probability.
Preferably, the length of the source overlapping region is not more than 33% of the length of the gate; the thickness of the ferroelectric dielectric layer is 130% of the length of the source electrode overlapping region.
Preferentially, the source electrode is formed by carrying out P type heavy doping in a germanium material; the channel is formed by carrying out N-type light doping in a silicon material; the drain electrode is formed by N-type heavy doping in a silicon material.
Preferably, the oxide layer dielectric of the gate is HfO with high dielectric constant 2 (ii) a The dielectric constant is 20-24; the metal layer of the grid is TiN; the ferroelectric dielectric layer of the grid is based on HfO 2 Radical doping is formed.
The invention has the beneficial effects that: the invention combines the negative capacitance effect and the silicon-germanium heterojunction, and continuously improves the band-to-band tunneling rate and the tunneling area of the device through source electrode overlapping, thereby improving the driving capability of the device. The source electrode overlapping part in the NCGAA-SOL-TFET enables the width of a source electrode and a channel heterojunction to be increased, the energy band at the heterojunction is bent more strongly, the band tunneling rate and the tunneling area are increased, and the conduction current of the device is further improved.
Drawings
FIG. 1 is a schematic diagram of a SiGe heterojunction NCGAA-TFET;
FIG. 2 is a schematic diagram of a SiGe heterojunction NCGAA-SOL-TFET;
FIG. 3 is a process flow diagram of SiGe heterojunction NCGAA-SOL-TFET.
Detailed Description
The embodiments and process steps of the present invention will be described in detail below with reference to examples, and it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the present invention.
The invention mainly aims to improve the current driving capability of the GAA-TFET device, and the GAA-TFET can easily reduce the subthreshold swing to be below 60mV/decade as a promising future device for replacing the traditional MOSFET. But its disadvantage is also apparent in that the on-current is very low, resulting in insufficient driving capability.
In the GAA-TFET, the negative capacitance effect is generated through the ferroelectric dielectric layer in the overlapping area of the grid electrode and the source electrode, so that the potential on the surface of a channel is amplified, and the band-to-band tunneling probability is improved.
And then, the silicon-germanium heterojunction is used for improving the conduction current of the channel, the germanium material has narrow forbidden band width and high carrier mobility, and the band tunneling rate and the tunneling area can be greatly increased by the heterojunction formed by the germanium and the silicon. And the silicon germanium heterojunction is more compatible with the current CMOS process compared with other compound heterojunction.
And finally, the grid electrode extends towards the source electrode, so that the heterojunction integrally moves towards the source electrode, the width of a heterojunction depletion region is increased, the energy band at the heterojunction is bent more strongly, the probability of band-to-band tunneling and the tunneling area are greatly increased, and the conduction current is further improved.
For the SiGe heterojunction NCGAA-TFET shown in fig. 1, in order to increase the tunneling current, the main method is to mainly increase the area of the tunneling junction and the band-to-band tunneling probability, and consider that a voltage is also applied to the source close to the channel, i.e., the gate extends toward the source to form a source overlap region, so that the positions of the source overlap region corresponding to the electric field in the device can be adjusted, and the positions of the source valence band and the channel conduction band can be adjusted. The heterojunction structure has the advantages that the energy band at the heterojunction is bent and generates band-band tunneling, the energy band close to the heterojunction in the source electrode is also bent, namely the heterojunction structure is equivalent to widening a depletion region of the heterojunction, and the effect is that the area and the probability of the band-band tunneling can be increased at the same time, so that the tunneling current is improved.
Fig. 2 shows a specific technical solution diagram of the present example, which includes: the grid electrode is composed of an oxide layer, a ferroelectric dielectric layer and a metal electrode, a source electrode overlapping region with the same structure and material as the grid electrode, a source electrode formed by doping germanium material, a channel region formed by doping silicon material and a drain electrode. The ferroelectric dielectric layer generates a negative capacitance effect, the silicon-germanium heterojunction formed by the source region and the channel increases the tunneling area and the tunneling probability, and the driving current of the device is improved under the combined action of multiple effects of a source electrode overlapping region formed by extending the grid electrode to the source region.
The CMOS device with the new structure is named as a negative capacitance ring gate source electrode overlapping tunneling field effect transistor (NCGAA-SOL-TFET), and the driving capability of the NCGAA-SOL-TFET can reach the level of the traditional standard ring gate CMOS device under the condition of ensuring the stability of other electrical properties.
On the basis of a more advanced GAA-TFET process, the gate extends to the source for a certain length, namely the source close to the gate forms a source overlapping region, so that an NCGAA-SOL-TFET structure is provided, and the method specifically comprises the following steps:
the source electrode is formed by P-type heavy doping in a germanium material;
the channel is formed by carrying out N-type light doping in a silicon material;
the drain electrode is formed by N-type heavy doping in a silicon material;
the gate oxide layer dielectric is HfO with high dielectric constant (20-24) 2 ；
The grid metal layer is TiN;
the grid ferroelectric dielectric layer is based on HfO 2 Base doping is formed;
the source overlapping region is a part extending the gate to the source, and has the same structure and material as the gate.
The preparation process of the device of the invention is shown in figure 3:
(1) Preparing a silicon substrate;
(2) Etching nanowire-shaped silicon on a silicon substrate through reactive ions to serve as a drain electrode and a channel region;
(3) Growing a germanium semiconductor on the channel through epitaxy to be used as a source electrode;
(4) N-type doping is performed to drain and channel regions of silicon semiconductor by ion implantation, with doping concentrations of 2 × 10 19 /cm 3 、10 15 /cm 3 ；
(5) P-type doping is carried out on a source electrode made of germanium semiconductor through ion implantation, and the doping concentration is 10 20 /cm 3 ；
(6) Depositing a layer of HfO on the channel by an atomic layer deposition process 2 The thin film is a grid oxide layer medium;
(7) Depositing a layer based on HfO on the gate oxide dielectric by an atomic layer deposition process 2 When the thickness of the ferroelectric dielectric layer is 130% of the length of the gate overlap region, the comprehensive performance of the device is optimal;
(8) In a nitrogen environment, performing rapid thermal annealing for 5s at 700 ℃ to enable the ferroelectric dielectric layer to show better ferroelectricity;
(9) The length of the source electrode overlapping area is adjustable and does not exceed 33 percent of the length of the grid electrode, and the process steps of the grid electrode oxide layer and the grid electrode ferroelectric medium layer are repeated in the source electrode overlapping area;
(10) And depositing a metal grid on the grid ferroelectric dielectric layer and the source electrode overlapping region ferroelectric dielectric layer by a physical vapor deposition process. Source and drain electrodes are formed on the source and drain electrodes, again by chemical vapor deposition.
In summary, the invention provides a structure of a silicon-based heterojunction negative capacitance ring gate source overlapping tunneling field effect transistor with adjustable source overlapping region length and ferroelectric dielectric layer thickness, and the GAA-TFET device with excellent performance can be finally obtained by adjusting different source overlapping region lengths and ferroelectric layer thicknesses for optimization. When the source electrode overlapping length does not exceed 33% of the grid electrode and the thickness of the ferroelectric medium layer is 130% of the source electrode overlapping length, the comprehensive electrical performance of the device is optimal.
Claims (4)
1. The negative capacitance ring grid source electrode overlapping tunneling field effect transistor comprises a source electrode, a channel, a drain electrode and a grid electrode, and is characterized in that: the source electrode is made of germanium materials, and the channel and the drain electrode are made of silicon materials;
forming a silicon-germanium heterojunction on the contact surface of the channel and the source electrode, and increasing the tunneling area and the tunneling probability;
adding a ferroelectric dielectric layer between an oxide layer dielectric of the grid and a metal layer of the grid for generating a negative capacitance effect and improving the surface potential of a channel;
the grid electrode extends to the source electrode to form an active electrode overlapping area; and also to increase the tunneling area and tunneling probability.
2. The negative-capacitance gate-all-around source-overlap tunneling field effect transistor of claim 1, wherein: the length of the source overlapping region is not more than 33% of the length of the grid electrode; the thickness of the ferroelectric dielectric layer is 130% of the length of the source electrode overlapping region.
3. The negative-capacitance gate-all-around source-overlap tunneling field effect transistor of claim 1, wherein: the source electrode is formed by carrying out P-type heavy doping in a germanium material; the channel is formed by carrying out N-type light doping in a silicon material; the drain electrode is formed by N-type heavy doping in a silicon material.
4. The negative-capacitance gate-all-around source-overlap tunneling field effect transistor according to claim 2 or 3, wherein: the oxide layer medium of the grid is HfO with high dielectric constant 2 (ii) a The dielectric constant is 20 to 24; the metal layer of the grid is TiN; the ferroelectric dielectric layer of the grid is based on HfO 2 Radical doping is formed.
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| CN202211074782.4A CN115332331A (en) | 2022-09-02 | 2022-09-02 | Negative capacitance gate-all-around source overlap tunneling field effect transistor |
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