CN115328560A - Chip starting method and system, computer equipment, storage medium and chip - Google Patents
Chip starting method and system, computer equipment, storage medium and chip Download PDFInfo
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- CN115328560A CN115328560A CN202210999722.7A CN202210999722A CN115328560A CN 115328560 A CN115328560 A CN 115328560A CN 202210999722 A CN202210999722 A CN 202210999722A CN 115328560 A CN115328560 A CN 115328560A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
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Abstract
The invention relates to the technical field of chips, in particular to a chip starting method, a chip starting system, computer equipment, a storage medium and a chip. The method comprises the following steps: reading and executing a boot program in the off-chip high-speed storage, finishing the starting process of the chip, and ending the process; if the chip can not be started, judging that the standby off-chip high-speed storage is started, if so, copying a boot program in an execution address of the space of the off-chip high-speed storage computer executing the starting to a specified address, executing the copied boot program to start the chip, and ending the starting process of the chip until the chip finishes the starting process; if the chip can not be started, selecting another standby off-chip high-speed storage which is not started to execute starting, and repeating the starting process of the standby off-chip high-speed storage; if the chip cannot be started by the high-speed storage outside the plurality of spare chips, resetting the trigger chip and restarting the starting process.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip starting method and system, a computer device, a storage medium, and a chip.
Background
An SoC chip is a system-on-chip composed of a processor, a cache, a memory, an interconnection bus, peripherals, and the like. The SoC is usually embedded with a Central Processing Unit (cpu), which calls a software program designed by a user to execute. The power-on start of the SoC chip is a process of cooperative work of software and hardware, a central processing unit obtains a start program from a storage computer device and runs the start program, a boot program works at the bottom layer of the SoC, the boot program realizes the initialization of the hardware computer device and the loading of an upper application program of the whole SoC system, and whether the function of the start program is correct determines whether the running environment of the SoC chip can be correctly constructed and whether a user program can be correctly executed.
From the application point of view, the SoC chip supports the starting of various storage media, and the boot program can be placed in various storage computer devices, such as starting from FLASH storage, starting from an SD card, starting from an eMMC, and the like. At present, for a multi-media starting mechanism of a chip, the existing method is as follows: a ROM is embedded in the chip, a section of starting code is stored in the ROM, the section of starting code can copy the boot program in the off-chip storage computer equipment to the high-speed RAM, and then the processor continues to execute from the high-speed RAM. As shown in fig. 1, for a multi-media-enabled chip architecture in the prior art, a processor, a ROM, an SRAM, an SDRAM, a FLASH memory, an SD/eMMC memory are connected through an interconnection bus, and a boot program is placed in the FLASH memory or the SD/eMMC memory. To reduce the amount of code in the ROM, the boot program generally needs to be split into two parts: the first part boot program is responsible for initializing SDRAM; the second part of the boot procedure performs the entire boot function. The code in the ROM needs to copy the first part boot program into the SRAM to be executed, and then the first part boot program guides the second part boot program to be executed completely.
In the prior art, two defects exist, namely, a boot program needs to be designed into two parts, so that the complexity of the program is increased; secondly, the ROM needs to be solidified in the chip, and the ROM increases the chip cost and area and increases the difficulty for chip production.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a chip starting method, a system, computer equipment, a storage medium and a chip, and a guide module is designed to complete the guide of multi-medium starting by combining the characteristics of high-speed random access storage computer equipment and nonvolatile storage computer equipment, so that the boot program design is optimized, and the starting of various media of the chip with simple and diversified processes is realized.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
in a first aspect, in an embodiment provided by the present invention, a chip starting method is provided, which is applied to a chip, where the chip includes a starting off-chip high-speed storage and at least one spare off-chip high-speed storage; the method comprises the following steps:
reading and executing a boot program in the off-chip high-speed storage, finishing the starting process of the chip, and ending the process;
if the chip can not be started, judging that the standby off-chip high-speed storage is started, if so, copying a boot program in an execution address of the space of the off-chip high-speed storage computer executing the starting to a specified address, executing the copied boot program to start the chip, and ending the starting process of the chip until the chip finishes the starting process;
if the chip can not be started, selecting another spare off-chip high-speed storage which is not started to execute starting, and repeating the starting process of the spare off-chip high-speed storage;
if the chip cannot be started by the high-speed storage outside the plurality of spare chips, resetting the trigger chip and restarting the starting process.
As a further aspect of the present invention, after the boot program in the execution address of the space of the off-chip high-speed storage computer device executing startup is copied to the specified address, the executing of the transferred boot program to perform chip startup further includes completing configuration of the off-chip high-speed storage computer device before startup, where the off-chip high-speed initialization module storage is available.
As a further aspect of the invention, a plurality of said spare off-chip high speed stores are provided with different levels of priority.
As a further scheme of the invention, the start-up off-chip high-speed storage is FLASH storage.
As a further aspect of the invention, the plurality of spare off-chip high speed stores comprise SD/eMMC stores, IC stores and USB stores.
In a second aspect, in yet another embodiment provided by the present invention, there is provided a chip comprising:
the system comprises a processor, a guide module, an SRAM, an SDRAM, a starting off-chip high-speed memory and at least one spare off-chip high-speed memory;
the processor is used for analyzing and executing the boot program;
the guide module is used for judging a starting mode and migrating a boot program;
the SRAM is used for storing stack data when the boot program is executed;
the SDRAM is used for storing the boot program after the migration;
starting off-chip high-speed storage for storing boot programs;
and at least one spare off-chip high-speed module is used for storing a boot program and starting for standby.
In a third aspect, in a further embodiment provided by the present invention, a chip multimedia boot system is provided, the system comprising:
the system comprises a processor, a guide module, an SRAM, an SDRAM, a starting off-chip high-speed memory and at least one spare off-chip high-speed memory;
the processor is used for analyzing and executing the boot program;
the guide module is used for judging a starting mode and migrating a boot program;
the SRAM is used for storing stack data when the boot program is executed;
the SDRAM is used for storing the boot program after the migration;
starting off-chip high-speed storage for storing boot programs;
and at least one spare off-chip high-speed module is used for storing a boot program and starting for standby.
In a fourth aspect, in yet another embodiment provided by the present invention, a computer device is provided, which includes a memory and a processor, the memory storing a computer program, the processor implementing the steps of the chip start-up method when loading and executing the computer program.
In a fifth aspect, in a further embodiment provided by the present invention, a storage medium is provided, which stores a computer program that, when loaded and executed by a processor, implements the steps of the chip start-up method.
The technical scheme provided by the invention has the following beneficial effects:
the invention designs the guide module to complete the guide of the multi-medium start by combining the characteristics of the high-speed random access storage computer equipment and the nonvolatile storage computer equipment, optimizes the boot program design and realizes the multi-medium start of the chip with simple and diversified flows.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
FIG. 1 is a flowchart of a chip multimedia boot according to an embodiment of the present invention.
Fig. 2 is a block diagram of a chip according to an embodiment of the present invention.
Fig. 3 is a block diagram of a boot module in a chip according to an embodiment of the present invention.
Fig. 4 is a block diagram of a chip multimedia boot system according to an embodiment of the present invention.
In the figure: 100-processor, 200-boot module, 300-SRAM, 400-SDRAM, 500-start off-chip high-speed storage, 600-spare off-chip high-speed storage, 201-resolution module, 202-SDRAM initialization module, 203-spare off-chip storage initialization module, 204-spare off-chip storage reading module, 205-data caching module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In order to reduce the amount of code in ROM, the boot program generally needs to be split into two parts: the first part boot program is responsible for initializing SDRAM; the second part of the boot procedure performs the entire boot function. The code in the ROM needs to copy the first part boot program to the SRAM for execution, and then the first part boot program guides the second part boot program to complete execution.
In the prior art, two defects exist, namely, a boot program needs to be designed into two parts, so that the complexity of the program is increased; secondly, the ROM needs to be solidified in the chip, and the ROM increases the chip cost and area and increases the difficulty for chip production.
The invention combines the characteristics of high-speed random access storage computer equipment and nonvolatile storage computer equipment, designs the guide module to complete the guide of multi-medium starting, optimizes boot program design and realizes the starting of various media of chips with simple and diversified processes.
Specifically, the embodiments of the present invention will be further explained below with reference to the drawings.
Referring to fig. 1, fig. 1 is a flowchart of a chip starting method according to an embodiment of the present invention, and as shown in fig. 1, the chip starting method includes steps S10 to S40. The chip starting method is applied to a chip which comprises starting off-chip high-speed storage and at least one spare off-chip high-speed storage.
S10, reading and executing a boot program in the off-chip high-speed storage, wherein the SRAM in the chip is responsible for stacking in the boot program executing process, and the process is ended until the chip finishes the starting process;
and S20, when the chip can not be started, judging that the standby off-chip high-speed storage is started, if so, copying a boot program in an execution address of the space of the off-chip high-speed storage computer executing the starting to a specified address, executing the copied boot program to start the chip, and ending the process when the chip finishes the starting process.
And S30, if the chip can not be started, selecting another standby off-chip high-speed storage which is not started to execute starting, and repeating the operation in the step S20.
And S40, if the chip cannot be started by the high-speed storage outside the standby chips, resetting the triggering chip and restarting the starting process.
In an embodiment of the invention, a plurality of said spare off-chip high speed stores may be provided with different levels of priority.
In an embodiment of the present invention, after copying the boot program in the execution address of the space of the off-chip high-speed storage computer device that executes startup to the designated address, executing the transferred boot program to perform chip startup further includes completing configuration of the off-chip high-speed storage computer device before startup, where the off-chip high-speed initialization module is available for storage.
In an embodiment of the present invention, the boot off-chip high speed storage may be FLASH storage.
The plurality of spare off-chip high-speed storages include various storage media such as SD/eMMC storage, I2C storage, and USB storage.
It should be understood that although the steps are described above in a certain order, the steps are not necessarily performed in the order described. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, some steps of the present embodiment may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in turns with other steps or at least a part of the steps or stages in other steps.
In one embodiment, referring to fig. 2, a chip is further provided in an embodiment of the present invention, the chip includes a processor 100, a boot module 200, an SRAM300, an SDRAM400, a boot off-chip high speed storage 500, and at least one spare off-chip high speed storage 600; the processor 100, the boot module 200, the SRAM300, the SDRAM400, and at least two off-chip high-speed modules 500 are connected by an interconnection bus.
The processor 100 is used for parsing and executing the boot program.
The boot module 200 is a module that starts to operate first after the chip is powered on, and is used for determining a start mode and migrating a boot program.
Referring to fig. 3, in the embodiment of the present invention, the boot module 200 includes a parsing module 201, an SDRAM initialization module 202, at least one spare off-chip storage initialization module 203, at least one spare off-chip storage read module 204, and a data caching module 205.
The analysis module 201 is configured to control a start process of a specific storage medium according to a result of the analysis module 201, where the analysis module is responsible for analyzing a chip start mode and a data packet.
The SDRAM initialization module 202 is configured to complete SDRAM configuration when the chip-enabled standby off-chip storage is started, and then the SDRAM is available.
And at least one spare off-chip storage initialization module 203, configured to complete the configuration of the spare off-chip storage first when the chip enables the spare off-chip storage to be started.
And at least one spare off-chip storage reading module 204 is used for migrating the boot program stored in the specified address of the spare off-chip storage to the SDRAM.
And the data caching module 205 is used for caching data in the boot program migration process.
The SRAM300 is configured to store stack data during execution of the boot program.
The SDRAM400 is used for storing the boot program after migration.
The boot off-chip high-speed storage 500 is used to store boot programs, and the boot off-chip high-speed storage 500 is initially stored in these computer devices for boot programs.
The boot off-chip high speed storage 500 may be FLASH storage.
And at least one spare off-chip high-speed module 600 for storing boot programs and starting the spare off-chip high-speed module for standby.
Specifically, when the chip cannot be started, it is determined that the standby off-chip high-speed storage is started, if so, the SDRAM400 initialization module in the boot module in the first step completes configuration of the SDRAM400 first, at this time, the SDRAM400 is available, the off-chip high-speed initialization module executing the startup in the second step completes configuration of the off-chip high-speed storage computer device executing the startup in the second step, at this time, the standby off-chip high-speed storage is available, the off-chip high-speed storage executing the startup in the third step copies the boot program from the execution address of the space of the off-chip high-speed storage computer device executing the startup to the designated address in the SDRAM400, and finally, the processor starts reading the SDRAM400 program from the SDRAM address to execute, and the chip completes the startup process, and the process ends.
In an embodiment of the present invention, the spare off-chip high speed module 600 may include an SD/eMMC storage, an I2C storage, and a USB storage.
The multi-media starting and guiding method provided by the invention replaces the existing ROM computer equipment, simplifies the design of boot program, overcomes the defects of high ROM cost, large area, limited capacity and the like, and supports the starting of various storage media such as FLASH storage, SD/eMMC storage, I2C storage and USB storage.
In one embodiment, referring to fig. 4, a chip multimedia boot system is further provided in an embodiment of the present invention, the system includes a processor 100, a boot module 200, an SRAM300, an SDRAM400, a boot off-chip high speed storage 500, and at least one spare off-chip high speed storage 600; the processor 100, the boot module 200, the SRAM300, the SDRAM400, and at least two off-chip high-speed modules 500 are connected by an interconnection bus.
The processor 100 is used for parsing and executing the boot program.
The boot module 200 is a module that starts to operate first after the chip is powered on, and is used for determining a start mode and migrating a boot program.
In an embodiment of the present invention, the boot module 200 includes a parsing module 201, an SDRAM initialization module 202, at least one spare off-chip storage initialization module 203, at least one spare off-chip storage read module 204, and a data caching module 205.
The parsing module 201 is configured to analyze the chip start mode and the data packet, and control the start process of the specific storage medium according to a result of the parsing module.
The SDRAM initialization module 202 is configured to complete SDRAM configuration when the chip-enabled standby off-chip storage is started, and then the SDRAM is available.
And at least one spare off-chip storage initialization module 203, configured to complete the configuration of the spare off-chip storage first when the chip enables the spare off-chip storage to be started.
And at least one spare off-chip storage reading module 204 is used for migrating the boot program stored in the specified address of the spare off-chip storage to the SDRAM.
And the data caching module 205 is used for caching data in the boot program migration process.
The SRAM300 is configured to store stack data during execution of the boot program.
The SDRAM400 is used for storing the boot program after migration.
Boot off-chip cache 500 for storing boot programs, the boot off-chip cache 500 being the first boot program to be stored in these computer devices.
The boot off-chip high speed storage 500 may be FLASH storage.
And at least one spare off-chip high-speed module 600 is used for storing the boot program and starting for standby.
Specifically, when the chip cannot be started, it is determined that the standby off-chip high-speed storage is started, if so, the SDRAM400 initialization module in the boot module in the first step completes configuration of the SDRAM400 first, at this time, the SDRAM400 is available, the off-chip high-speed initialization module executing the startup in the second step completes configuration of the off-chip high-speed storage computer device executing the startup in the second step, at this time, the standby off-chip high-speed storage is available, the off-chip high-speed storage executing the startup in the third step copies the boot program from the execution address of the space of the off-chip high-speed storage computer device executing the startup to the designated address in the SDRAM400, and finally, the processor starts reading the SDRAM400 program from the SDRAM address to execute, and the chip completes the startup process, and the process ends.
In an embodiment of the present invention, the standby off-chip high speed module 600 may include an SD/eMMC storage, an I2C storage, and a USB storage.
The multi-media starting and guiding method provided by the invention replaces the existing ROM computer equipment, simplifies the design of boot program, overcomes the defects of high ROM cost, large area, limited capacity and the like, and supports the starting of various storage media such as FLASH storage, SD/eMMC storage, I2C storage and USB storage.
Illustratively, a specific flowchart of an example of the multi-media booting method of a chip according to an embodiment is provided, which includes the following steps:
(1) When the chip is started for FLASH storage, the processor directly reads the boot program from the FLASH storage to execute, the SRAM in the chip is responsible for stacking in the boot program execution process, and the process is ended until the chip finishes the starting process.
(2) When the chip is not started for FLASH storage, whether SD/eMMC storage is started or not is judged, if yes, an SDRAM initialization module in a guide module completes SDRAM configuration firstly, SDRAM is available at the moment, the SD/eMMC initialization module completes SD/eMMC storage computer equipment configuration at the second step, SD/eMMC storage is available at the moment, the SD/eMMC storage reading module copies a boot program to a designated address in SDRAM from an execution address of an SD/eMMC storage computer equipment space at the third step, and finally a processor starts to read the SDRAM program from the SDRAM address to execute, so that the chip completes the starting process, and the process is ended.
(3) When the chip is not started for SD/eMMC memory, whether I2C memory is started or not is judged, if yes, the SDRAM initialization module in the guide module completes SDRAM configuration firstly, SDRAM is available at the moment, the I2C initialization module completes configuration of I2C memory computer equipment at the moment, I2C memory is available at the moment, the I2C computer equipment reading module copies a boot program to an appointed address in the SDRAM from the appointed address of the I2C memory computer equipment at the third step, and finally the processor starts to read the SDRAM program from the SDRAM address to execute, so that the chip completes the starting process, and the process is finished.
(4) When the chip is not started for I2C storage, whether USB storage is started or not is judged, if yes, the SDRAM initialization module in the guide module completes SDRAM configuration firstly, SDRAM is available at the moment, the USB initialization module completes USB storage computer equipment configuration at the second step, USB storage is available at the moment, the USB computer equipment reading module copies the boot program to the specified address in the SDRAM from the specified address of the USB storage computer equipment, and finally the processor starts to read the SDRAM program from the SDRAM address to execute, so that the chip completes the starting process, and the process is ended.
(5) When the chip is not started for USB storage, an invalid starting mode code appears, and the chip is triggered to reset to restart the starting process.
In an embodiment, there is further provided a computer device in an embodiment of the present invention, including at least one processor, and a memory communicatively connected to the at least one processor, where the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to cause the at least one processor to execute the chip activation method, and the processor executes the instructions to implement the steps in the above method embodiment:
s10, reading and executing a boot program in the off-chip high-speed storage, wherein the SRAM in the chip is responsible for stacking in the boot program executing process, and the process is ended until the chip finishes the starting process;
and S20, when the chip can not be started, judging that the standby off-chip high-speed storage is started, if so, copying a boot program in an execution address of the space of the off-chip high-speed storage computer executing the starting to a specified address, executing the copied boot program to start the chip, and ending the process when the chip finishes the starting process.
And S30, if the chip cannot be started, selecting another standby off-chip high-speed memory which is not started to execute starting, and repeating the operation of the step S20.
And S40, if the chip cannot be started by the high-speed storage outside the plurality of spare chips, resetting the trigger chip and restarting the starting process.
In an embodiment of the invention, a plurality of said spare off-chip high speed stores may be provided with a priority.
In an embodiment of the present invention, after the boot program in the execution address of the space of the off-chip high-speed storage computer device that executes startup is copied to the designated address, executing the transferred boot program to perform chip startup further includes completing configuration of the off-chip high-speed storage computer device before startup, where storage of the off-chip high-speed initialization module is available.
In an embodiment of the present invention, the boot off-chip high speed storage may be FLASH storage.
The plurality of spare off-chip high-speed storages include various storage media such as SD/eMMC storage, I2C storage, and USB storage.
The computer equipment comprises user computer equipment and network computer equipment. Wherein the user computer device includes but is not limited to a computer, a smart phone, a PDA, etc.; the network computer device includes, but is not limited to, a single network server, a server group consisting of a plurality of network servers, or a Cloud Computing (Cloud Computing) based Cloud consisting of a large number of computers or network servers, wherein the Cloud Computing is one of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. Wherein the computer device can be operated alone to implement the invention, or can be accessed to a network and implement the invention through interoperation with other computer devices in the network. The network in which the computer device is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a VPN network, and the like.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In an embodiment of the present invention, there is also provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the above-described method embodiment:
s10, reading and executing a boot program in the off-chip high-speed storage, wherein the SRAM in the chip is responsible for stacking in the boot program executing process till the chip finishes the starting process, and the process is finished;
and S20, when the chip can not be started, judging that the standby off-chip high-speed storage is started, if so, copying a boot program in an execution address of the space of the off-chip high-speed storage computer executing the starting to a specified address, executing the copied boot program to start the chip, and ending the process when the chip finishes the starting process.
And S30, if the chip cannot be started, selecting another standby off-chip high-speed memory which is not started to execute starting, and repeating the operation of the step S20.
And S40, if the chip cannot be started by the high-speed storage outside the plurality of spare chips, resetting the trigger chip and restarting the starting process.
In an embodiment of the invention, a plurality of said spare off-chip high speed stores may be provided with a priority.
In an embodiment of the present invention, after the boot program in the execution address of the space of the off-chip high-speed storage computer device that executes startup is copied to the designated address, executing the transferred boot program to perform chip startup further includes completing configuration of the off-chip high-speed storage computer device before startup, where storage of the off-chip high-speed initialization module is available.
In an embodiment of the present invention, the boot off-chip high speed storage may be FLASH storage.
The plurality of spare off-chip high-speed storages include various storage media such as SD/eMMC storage, I2C storage, and USB storage.
It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A chip starting method, the chip includes starting the high-speed storage outside the chip and no less than one spare high-speed storage outside the chip; the method is characterized by comprising the following steps:
reading and executing a boot program in the off-chip high-speed storage, and finishing the starting process and starting the chip;
if the chip can not be started, judging to start the standby off-chip high-speed storage, if so, copying a boot program in an execution address of the space of the off-chip high-speed storage computer equipment for executing the starting to a specified address, executing the copied boot program to start the chip, and finishing the starting process of the chip to finish the starting;
if the chip can not be started, selecting another standby off-chip high-speed storage which is not started to execute starting, and repeating the starting process of the standby off-chip high-speed storage;
if the chip cannot be started by the high-speed storage outside the plurality of spare chips, resetting the trigger chip and restarting the starting process.
2. The chip startup method according to claim 1, wherein executing the transferred boot program for chip startup after the boot program is copied to the specified address in the execution address of the off-chip high-speed storage computer device space for executing startup further comprises completing configuration of the off-chip high-speed storage computer device before startup when off-chip high-speed initialization module storage is available.
3. The chip startup method of claim 1, wherein the startup off-chip high speed storage is FLASH storage.
4. The chip startup method according to claim 1, wherein a plurality of the spare off-chip high-speed storages are provided with different levels of priority.
5. The chip startup method of claim 3, wherein the plurality of spare off-chip high speed stores comprise SD/eMMC stores, I2C stores, and USB stores.
6. A chip is characterized by comprising a processor, a boot module, an SRAM, an SDRAM, a starting off-chip high-speed memory and at least one spare off-chip high-speed memory;
the processor is used for analyzing and executing the boot program;
the guide module is used for judging a starting mode and migrating a boot program;
the SRAM is used for storing stack data when the boot program is executed;
the SDRAM is used for storing the boot program after migration;
starting off-chip high-speed storage for storing boot programs;
and at least one spare off-chip high-speed module is used for storing a boot program and starting for standby.
7. The chip of claim 6, wherein the boot module comprises a parsing module, an SDRAM initialization module, at least one spare off-chip storage read module, and a data cache module;
the analysis module is used for analyzing the chip starting mode and the data packet by the analysis module;
the SDRAM initialization module is used for completing SDRAM configuration when the chip enables the standby off-chip storage to be started, and then the SDRAM is available;
the at least one spare off-chip storage initialization module is used for completing the configuration of spare off-chip storage firstly when the chip enables the spare off-chip storage to be started;
at least one spare off-chip storage reading module is used for migrating the boot program stored in the specified address of the spare off-chip storage to SDRAM;
and the data caching module is used for caching data in the boot program migration process.
8. A chip multimedia boot apparatus, comprising: the system comprises a processor, a guide module, an SRAM, an SDRAM, a starting off-chip high-speed memory and at least one spare off-chip high-speed memory;
the processor is used for analyzing and executing the boot program;
the guide module is used for judging a starting mode and migrating a boot program;
the SRAM is used for storing stack data when the boot program is executed;
the SDRAM is used for storing the boot program after migration;
starting off-chip high-speed storage for storing boot programs;
and at least one spare off-chip high-speed module is used for storing a boot program and starting for standby.
9. A computer device comprising a memory storing a computer program and a processor implementing the steps of the chip startup method according to any one of claims 1-5 when the computer program is loaded and executed.
10. A storage medium storing a computer program which is loaded by a processor and which when executed carries out the steps of the chip start-up method according to any one of claims 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210999722.7A CN115328560A (en) | 2022-08-19 | 2022-08-19 | Chip starting method and system, computer equipment, storage medium and chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210999722.7A CN115328560A (en) | 2022-08-19 | 2022-08-19 | Chip starting method and system, computer equipment, storage medium and chip |
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| CN202210999722.7A Pending CN115328560A (en) | 2022-08-19 | 2022-08-19 | Chip starting method and system, computer equipment, storage medium and chip |
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| CN (1) | CN115328560A (en) |
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