CN1153276C - Method for making monocrystal non-volatility memory element - Google Patents
Method for making monocrystal non-volatility memory element Download PDFInfo
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- CN1153276C CN1153276C CNB011181168A CN01118116A CN1153276C CN 1153276 C CN1153276 C CN 1153276C CN B011181168 A CNB011181168 A CN B011181168A CN 01118116 A CN01118116 A CN 01118116A CN 1153276 C CN1153276 C CN 1153276C
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Abstract
The present invention relates to a method for making a mono-electric crystal non-volatile memory element, which comprises: a first oxide layer as a sacrificial layer is formed on a semiconductor substrate, and then, a silicon nitride layer is formed and is patterned to form an opening; a part of the semiconductor substrate is exposed, a second oxide layer is formed along the surface of the opening and on the silicon nitride layer, the second oxide layer at the side wall of the opening is etched to form a side wall gap, a gate dielectric layer is formed on the exposed semiconductor substrate, a first polysilicon layer is polished in a chemical mechanical polishing mode, and the silicon nitride layer, a gap wall and the sacrificial layer are removed; a tunneling dielectric layer and a control gate are respectively formed on the surface of a suspension gate. The present invention has the advantages of convenient manufacturing process and high electron injection efficiency.
Description
Technical field
The present invention relates to semiconductor element, be meant a kind of method for making of single-transistor non-volatile memory device especially.
Background technology
As everyone knows, semi-conductor industry has been developed to ultra-large type integrated circuit (ULSI) technical field, the manufacturing of nonvolatile memory is also along with development trend, towards dwindling the component size development, nonvolatile memory comprises the element of different types, for example can become the read only memory (EAROM) by electricity, can remove programmable read only storage (EEPROM) and Nonvolatile static random access memory (EEPROM-EAROMS) by electricity.The trend of different types element is all toward high persistence and high-speed demand side development.These elements all utilize the Fowler-Nordheim tunneling effect, reach more property of electronic variable.The energy barrier at wherein cold electron tunneling silicon and thin dielectric layer interface and enter the silicon dioxide conduction band.Generally speaking this thin dielectric layer is made up of silicon dioxide, and when a voltage imposes on grid, this moment, thin layer of silicon dioxide allowed the electric charge tunnelling.Therefore material silicon dioxide is the high-insulation body, and then the tunnelling electronics is captured and sinks in the silicon dioxide layer.
Multiple nonvolatile memory is exposed in the known technology.For example, Michelfx proposes tool from arranging the erasable programmable read only storage (EPROMs) of planar array memory cell.In the middle of this technology, the diffusion region of imbedding that is self-aligned to the suspension grid is used in the bit line.Consult " A New Self-AlignedCell for UItra High Density EPROMs, A.T.Michelx, IEDM, Tech.pp.548-553,1987 ".Bergomot proposes another kind of memory cell array, is used for high density flash EEPROM, consults " NOR Virtual ground (NVG)-Scaling Concept for Very High DensityEEPROMs, A Bergomot, IEEE; PP.15-18,1993 ". this memory cell structure is used for the micro component size, to make high density flash EEPROM.Another prior art relevant with this field is U.S. Patent number NO.4,203,158.The major defect of above technology is:
This class component of great majority all comprises a suspension grid electric crystal in each storage location and separates the selection electric crystal with one, and this class formation occupies than large tracts of land, and electron injection efficiency is lower, is difficult to meet technical development trend.
Summary of the invention
The method for making that the purpose of this invention is to provide a kind of single-transistor non-volatile memory device overcomes the drawback of prior art, reaches the purpose that processing procedure wedge angle easy and that wherein comprise partly promotes electron injection efficiency.
The object of the present invention is achieved like this: a kind of method for making of single-transistor non-volatile memory device is characterized in that: it comprises the steps:
(1) on semiconductor substrate, forms a sacrifice layer;
(2) on this sacrifice layer, form first dielectric layer;
(3) figure is transformed on this sacrifice layer and this first dielectric layer,, exposes the semiconductor substrate of a part thus to the open air to form opening;
(4) along forming second dielectric layer on this open surfaces and the sacrifice layer;
(5) this second dielectric layer of etching forms side wall spacer on the sidewall of this opening, and this semiconductor substrate is exposed between this clearance wall;
(6) expose the place to the open air in this semiconductor substrate and form gate dielectric layer;
(7) on this first dielectric layer, form first conductive layer, this opening of backfill;
(8) remove this first conductive layer and reach planarized surface;
(9) remove this first dielectric layer, side wall spacer and sacrifice layer, form suspended grid;
(10) form tunnel dielectric layer in this suspended grid surface;
(11) on this tunnel dielectric layer, form second conductive layer, as the control grid.
This first dielectric layer is made up of silicon nitride, removes with hot phosphoric acid solution.This second dielectric layer is made up of silicon dioxide, and removes or remove with the buffer silicon oxide etching solution with hydrofluoric acid solution.This sacrifice layer is made up of silicon dioxide, and removes or remove with the buffer silicon oxide etching solution with hydrofluoric acid solution.This tunnel dielectric layer is made up of one of following at least material: silicon oxynitride, silicon nitride, silicon dioxide, silica/silicon nitride composition or silica/silicon nitride/silicon dioxide composition.
The present invention also provides the method for making of another kind of single-transistor nonvolatile memory, it is characterized in that: it comprises the steps:
(1) on semiconductor substrate, forms first oxide layer as sacrifice layer;
(2) on this sacrifice layer, form first dielectric layer;
(3) figure is transformed on this sacrifice layer and this first dielectric layer,, exposes the semiconductor substrate of a part thus to the open air to form opening;
(4) along forming second dielectric layer on this open surfaces and the silicon nitride layer;
(5) this second dielectric layer of etching forms side wall spacer on the sidewall of this opening, and semiconductor substrate is exposed between this clearance wall;
(6) expose the place to the open air in this semiconductor substrate and form gate dielectric layer;
(7) on this first dielectric layer, form first polysilicon layer, fill up opening once again;
(8) remove this first polysilicon layer, reach planarized surface;
(9) remove this first dielectric layer, side wall spacer and sacrifice layer, form suspended grid;
(10) form tunnel dielectric layer in this suspended grid surface;
(11) on this tunnel dielectric layer, form second polysilicon layer, as the control grid.
This first dielectric layer is made up of silicon nitride, and removes with hot phosphoric acid solution.This second dielectric layer is made up of silicon dioxide, and removes with hydrofluoric acid solution.This side wall spacer is removed with the buffer silicon oxide etching solution.This sacrifice layer is made up of silicon dioxide, and removes or remove with the buffer silicon oxide etching solution with hydrofluoric acid solution.
Major advantage of the present invention is to have the effect that processing procedure wedge angle part easy and that wherein comprise can promote electron injection efficiency.
Further specify below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1 forms oxide layer for the present invention on substrate.The semiconductor crystal wafer profile of silicon nitride layer and opening;
Fig. 2 forms the semiconductor crystal wafer profile of clearance wall for the present invention;
Fig. 3 forms the semiconductor crystal wafer profile of conductive layer for the present invention;
Fig. 4 forms the semiconductor crystal wafer profile of suspended grid for the present invention;
Fig. 5 forms the semiconductor crystal wafer profile of control gate for the present invention.
Embodiment
Consult Fig. 1-Fig. 5, the invention provides the method for making that a novel manner is made the single-transistor nonvolatile memory.In this method for making, clearance wall is used for forming conductive layer, and this method is more simplified than known technology, at first provide a crystal plane to for＜100〉or＜111 monocrystalline silicon substrate 2, sacrifice layer 4 (for example silicon dioxide layer) is formed on the substrate 2, and first dielectric layer 6 (as silicon nitride layer or similar person) be formed on the silicon oxide layer 4.Generally speaking, under temperature 800-1100 ℃ of thermal oxidation furnace, can get silicon dioxide layer 4.The about 50-500 dust of thickness of common silicon dioxide layer 4.
Other method for makings also can be used for forming oxide layer 4 as chemical vapour deposition (CVD).The deposition of silicon nitride layer 6 can form in any suitable manner.For example low-pressure chemical vapor deposition (LPCVD), electricity are starched enhanced chemical vapor deposition (PECVD) or high density plasma enhanced chemical vapor deposition (HDPCVD).In most preferred embodiment, the reacting gas that forms in silicon nitride layer 6 steps comprises SiH
4, NH
3, N
2, N
2O or SiH
2Cl
2, NH
3, N
2, N
2O.
Next, utilize lithographic process exposed portion silicon nitride layer 6, the photoresist design transfer that will have opening is to silicon nitride layer 6, with the photoresist (not shown) is that mask is to silicon nitride layer 6, oxide layer 4 is carried out etching, so can be by opening 8 place's exposed portion substrates 2 in silicon nitride layer 6.In most preferred embodiment, the width range of opening 8 can be the 0.5-0.1 micron.After silicon nitride layer 6 pattern definitions, photoresist is removed.
Thereafter, second dielectric layer 10 is formed on first dielectric layer 8 and opening 8 surfaces of substrate 2, and the width of compression opening 8, and as shown in Figure 1, second dielectric layer 10 can be made up of unadulterated silicon dioxide.
Consult Fig. 2,, form clearance wall 12 by second dielectric layer 10 is carried out on the sidewall that is etched in opening 8 of anisotropic; Another kind of selection is to use electric paste etching.
With reference to figure 3, gate dielectric layer 14 is formed at opening 8 belows (bottom), is made up of silicon dioxide or silicon oxynitride.Silicon oxynitride layer 14 with thermal oxidation method at N
2O or NO gaseous environment generate preferable down.The temperature range that generates silicon oxynitride layer 14 is 700-1150 ℃, and the about 25-150 dust of thickness is preferable.
Referring to Fig. 3, next step forms another conductive layer 16, for example through doped polycrystalline silicon layer on silicon nitride layer 6, and fill up the opening 8 that narrows once again, doped polycrystalline silicon layer 16 can be selected the polysilicon that mixes or with the mix polysilicon of (mixing synchronously) of deposition reaction; In addition, metal or alloy also can be used for conductive layer 16.Then remove a part of polysilicon layer 16 in cmp mode (CMP).This uses general technology to obtain the topology profile.
Consult Fig. 4, next step removes silicon nitride layer 6, clearance wall 12 and sacrifice layer 4.Therefore keep the curved profile of polysilicon structure as the suspension grid.Must notice that the suspension grid are included in the efficient that can promote the electronics injection than the wedge angle 17 of upper end.In this embodiment, can utilize hot phosphoric acid solution that silicon nitride layer 6 is removed, oxide be divested with HF (hydrofluoric acid) solution or buffer oxide silicon etching liquid (BOE).
As shown in Figure 5, form tunnel dielectric layer 18 along suspension grid 16 surfaces, it is preferable as material that tunnel dielectric layer 18 can adopt silicon dioxide, silicon nitride, silicon oxynitride ON (silicon dioxide/silicon nitride) or ONO (silicon dioxide/silicon nitride/silicon dioxide) combination layer.Another conductive layer 20 for example through doped polycrystalline silicon layer, is formed on the tunnel dielectric layer 18, as the control grid.Utilize photoetching and etch process to define the pattern of control grid 20 at last.
Aforesaid preferred embodiment is known every change of this type of skill personage in order to explanation the present invention, does not allly break away from the equivalence finished under the disclosed spirit and changes or modify, and all should be included within protection scope of the present invention.
Claims (10)
1, a kind of method for making of single-transistor non-volatile memory device, it is characterized in that: it comprises the steps:
(1) on semiconductor substrate, forms a sacrifice layer;
(2) on this sacrifice layer, form first dielectric layer;
(3) figure is transformed on this sacrifice layer and this first dielectric layer,, exposes the semiconductor substrate of a part thus to the open air to form opening;
(4) along forming second dielectric layer on this open surfaces and the sacrifice layer;
(5) this second dielectric layer of etching forms side wall spacer on the sidewall of this opening, and this semiconductor substrate is exposed between this clearance wall;
(6) expose the place to the open air in this semiconductor substrate and form gate dielectric layer;
(7) on this first dielectric layer, form first conductive layer, this opening of backfill;
(8) remove this first conductive layer and reach planarized surface;
(9) remove this first dielectric layer, side wall spacer and sacrifice layer, form suspended grid;
(10) form tunnel dielectric layer in this suspended grid surface;
(11) on this tunnel dielectric layer, form second conductive layer, as the control grid.
2, method for making as claimed in claim 1 is characterized in that: this first dielectric layer is made up of silicon nitride, and removes with hot phosphoric acid solution.
3, method for making as claimed in claim 1 is characterized in that: this second dielectric layer is made up of silicon dioxide, and removes or remove with the buffer silicon oxide etching solution with hydrofluoric acid solution.
4, method for making as claimed in claim 1 is characterized in that: this sacrifice layer is made up of silicon dioxide, and removes or remove with the buffer silicon oxide etching solution with hydrofluoric acid solution.
5, method for making as claimed in claim 1 is characterized in that: this tunnel dielectric layer is made up of one of following at least material: silicon oxynitride, silicon nitride, silicon dioxide, silica/silicon nitride composition or silica/silicon nitride/silicon dioxide composition.
6, a kind of method for making of single-transistor nonvolatile memory, it is characterized in that: it comprises the steps:
(1) on semiconductor substrate, forms first oxide layer as sacrifice layer;
(2) on this sacrifice layer, form first dielectric layer;
(3) figure is transformed on this sacrifice layer and this first dielectric layer,, exposes the semiconductor substrate of a part thus to the open air to form opening;
(4) along forming second dielectric layer on this open surfaces and first dielectric layer;
(5) this second dielectric layer of etching forms side wall spacer on the sidewall of this opening, and semiconductor substrate is exposed between this clearance wall;
(6) expose the place to the open air in this semiconductor substrate and form gate dielectric layer;
(7) on this first dielectric layer, form first polysilicon layer, fill up opening once again;
(8) remove this first polysilicon layer, reach planarized surface;
(9) remove this first dielectric layer, side wall spacer and sacrifice layer, form suspended grid;
(10) form tunnel dielectric layer in this suspended grid surface;
(11) on this tunnel dielectric layer, form second polysilicon layer, as the control grid.
7, method for making as claimed in claim 6 is characterized in that: this first dielectric layer is made up of silicon nitride, and removes with hot phosphoric acid solution.
8, method for making as claimed in claim 6 is characterized in that: this second dielectric layer is made up of silicon dioxide, and removes with hydrofluoric acid solution.
9, method for making as claimed in claim 6 is characterized in that: this side wall spacer is removed with the buffer silicon oxide etching solution.
10, method for making as claimed in claim 6 is characterized in that: this sacrifice layer is made up of silicon dioxide, and removes or remove with the buffer silicon oxide etching solution with hydrofluoric acid solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011181168A CN1153276C (en) | 2001-05-16 | 2001-05-16 | Method for making monocrystal non-volatility memory element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011181168A CN1153276C (en) | 2001-05-16 | 2001-05-16 | Method for making monocrystal non-volatility memory element |
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| Publication Number | Publication Date |
|---|---|
| CN1385893A CN1385893A (en) | 2002-12-18 |
| CN1153276C true CN1153276C (en) | 2004-06-09 |
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| CNB011181168A Expired - Lifetime CN1153276C (en) | 2001-05-16 | 2001-05-16 | Method for making monocrystal non-volatility memory element |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7547627B2 (en) * | 2004-11-29 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| CN110047742A (en) * | 2019-03-08 | 2019-07-23 | 福建省福联集成电路有限公司 | A kind of manufacturing method of semiconductor device and semiconductor devices |
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