CN115327193A

CN115327193A - Test protection circuit with overvoltage protection

Info

Publication number: CN115327193A
Application number: CN202210497541.4A
Authority: CN
Inventors: V·V·阿隆民; 路易斯·杰伊·沙特金; 余俊生
Original assignee: Tower Manufacturing Corp
Current assignee: Tower Manufacturing Corp
Priority date: 2021-05-11
Filing date: 2022-05-05
Publication date: 2022-11-11

Abstract

A test protection circuit with a Ground Fault Circuit Interrupter (GFCI) having end-of-life automatic monitoring and over-voltage monitoring is provided. The present invention also provides a relay synchronization switch for isolating the GFCI during automatic monitoring. The test protection circuit also provides an end-of-life circuit that disables the test protection circuit if the automatic monitoring fails and a cutoff circuit that disables the test protection circuit if an overvoltage condition is detected.

Description

Test protection circuit with overvoltage protection

Technical Field

The present invention relates generally to electrical safety devices and, more particularly, to an automatic reset Ground Fault Circuit Interrupter (GFCI) having an automatic monitoring end-of-life circuit and overvoltage monitoring.

Background

Conventional electrical devices typically receive Alternating Current (AC) from a power source, such as an electrical outlet, via a pair of conductive lines. The pair of conductive lines, commonly referred to as phase and neutral, enable the appliance or load to receive the current required for operation.

Connecting an electrical device to a power source through a pair of conductive traces creates a number of potentially dangerous conditions. In particular, there is a risk of ground faults and neutral ground conditions in the conductive lines. A ground fault condition occurs when there is an imbalance between the currents flowing in the phase and neutral lines. A neutral-to-ground condition occurs when the neutral is grounded at the load. Ground fault conditions are extremely dangerous and can cause serious injury.

Ground fault interrupters include ground fault circuit breakers, ground fault receptacles and even cable-mounted ground fault protection devices. Even if ground fault interrupters pass all current industry standards, they may be troubled by false trips. One of the causes of false tripping is the disconnection of power from the inductive device, particularly by unplugging the device.

Examples of such devices include electric shavers, high intensity lamps, and small cooling fans, such as fans used to cool electronic equipment. Unplugging these devices can create an arc between the plug and the receptacle, resulting in a broadband noise of several volts being superimposed on the power line. Due to the broadband nature of noise, even very small stray coupling capacitances couple noise from the power line conductor into the ground fault circuit, causing a false trip.

A typical ground fault interrupter includes an operational amplifier that amplifies a sensed ground fault signal and applies the amplified signal to a window comparator that compares the signal to positive and negative reference signals. If either reference value is exceeded, a trip signal is generated. One common type of ground fault detection circuit is a sleep oscillator type detector. Such a detector comprises a first sensor coil through which the phase and neutral lines of the circuit to be protected pass. The output of the first sensor coil is applied via a coupling capacitor to the above-mentioned operational amplifier, which is followed by a window comparator. A phase to ground fault causes the amplified signal to exceed a reference value and generate a trip signal.

The sleep oscillator type ground fault detector includes a second sensor coil through which only a neutral line passes. A neutral to ground fault couples the two detector coils together causing the amplifier to oscillate, which results in the generation of a trip signal.

It has been found that load-related switching phenomena, such as caused by unplugging an inductive-type device or the like, cause broadband noise that can cause false tripping of a ground fault interrupter.

Ground fault circuit interrupters are well known in the art and are commonly used to protect against ground faults and neutral ground conditions. Generally, GFCI devices sense the presence of a ground fault and a neutral ground condition in the conductive paths and, in response thereto, open at least one of the conductive paths between the power source and the load to eliminate the hazardous condition.

In U.S. patent No. 5,177,657 to m.baer et al, a ground fault interrupter circuit is disclosed that interrupts the flow of current to a pair of lines extending between a power supply and a load. The ground fault interrupter circuit includes: a circuit breaker including a normally open switch disposed on one or both of the lines, a relay circuit for selectively closing the normally open switch, an electronic latch circuit operable in a first bi-stable state and a second bi-stable state, and a fault sensing circuit for sensing the presence of a fault condition in at least one of the lines. When the electronic latch circuit is in the first bi-stable state, the electronic latch circuit causes the relay circuit to close the normally open switch and hold the normally open switch in its closed position. The electronic latch circuit also causes the relay circuit to allow the normally open switch to return to its normally open state when the latch circuit is in its second bi-stable state. The fault sensing circuit senses the presence of a fault condition in at least one of the lines and latches the electronic latching circuit in its second state when the fault condition is detected.

In U.S. patent No. 5,418,678 to t.m. mcdonald, an improved Ground Fault Circuit Interrupter (GFCI) device is disclosed that requires manual setup after initial connection to an ac power source or completion of a power interruption. The improved GFCI device utilizes a controlled switching device that, in response to a load power signal, allows the relay contact set of the GFCI device to close only when power is available at the output or load terminals. The controlled switching device preferably includes an opto-isolator or other type of switching device that provides isolation between the GFCI input and output when the set of relay contacts is open. The improved GFCI device can be incorporated into a portable unit, such as a plug-in or line cable unit, for use with an unprotected AC receptacle.

In U.S. patent No. 4,816,957 to l.f. irwin, an adapter unit is disclosed that includes a moisture-resistant housing in which is mounted an improved, self-testing type ground line fault interrupter device. The improved device is electrically interconnected to a connector mounted externally of the adapter housing so that the unit can be directly plugged into a standard duplex receptacle of an existing circuit. The apparatus includes circuitry for automatically testing the operability of the device when inserted into a duplex receptacle without requiring the user to manually operate a test button or other overt action.

In U.S. patent No. 4,578,732 to c.w. draper et al, a wall socket type ground fault circuit interrupter is disclosed having a pair of sockets accessible from the front of the interrupter, a reset button and a test button. The interrupter has latched snap contacts and a novel latching relay structure for holding the snap contacts in a circuit-closed position. The snap contacts allow all components including the monitoring toroid (sensing transformer) and the power supply to be separately positioned and connected on the load side of the snap contacts so that all circuits of the interrupter are de-energized when the contacts snap into the circuit open position. The snap contact mechanism and relay are provided with structures that provide no trip mode contact actuation for the interrupter and thus provide a snap contact operation that is deterring from vandalism.

One disadvantage of GFCI devices of the type described above is that GFCI devices typically include a large solenoid to selectively open and close the switching device. Specifically, in order to switch and maintain the solenoid in its energized state, the solenoid typically requires a constant supply line voltage (about 120 volts). As a result, the solenoid becomes a significant power consumption source.

UL943 now requires panel-mount and receptacle-based GFCI to indicate "end of life" if the device fails to trip when the test button is manually operated. However, even if the end user tests their device periodically, a GFCI device that has not been properly tested may reset and continue to provide power, but may not provide ground fault protection. Without the built-in power-on rejection feature, the consumer may mistakenly and tragedly believe that there is protection if there is power. Despite the manufacturer's warnings, many end users are still (and continue to maintain) unaware that periodic testing is required; others know to test regularly, but do not always test carefully. The UL will also introduce a requirement to automatically monitor the GFCI, whereby the GFCI will self-test at regular intervals and provide an indication of "end of life" to the user.

Generally, an end-of-life event is an open or short circuit of the ground fault sensing components (toroid and integrated circuit); a fault in the trip solenoid and/or its control circuit, or an open or short circuit in a switching Semiconductor (SCR) controlling the trip solenoid control circuit.

Accordingly, there is a need for a solenoid with adequate rating for a line voltage GFCI device that has a reduced tendency to fail due to the high voltages and currents associated with typical line voltages. There is also a need for a ground fault interrupter that does not trip erroneously in response to broadband noise in the protected circuit. There is also a need for a ground fault circuit that has improved immunity to broadband noise that is also generated in response to sputtering arc faults.

There is also a need for a GFCI that can manually and automatically test components of the GFCI that often fail and deny power when the test fails.

Disclosure of Invention

A GFCI constructed in accordance with the invention for interrupting current flowing through a pair of lines extending between a source and a load, the GFCI comprising: a circuit breaker having a switch disposed on one of the lines, the switch having a first position in which the power source in its associated line is not connected to the load and a second position in which the power source in its associated line is connected to the load; a relay circuit for selectively moving the switch and holding the switch in the first position or the second position.

The GFCI includes a latch circuit operable in a first bistable state and a second bistable state (on/off), the latch circuit allowing the solenoid to switch from its de-energized state to its energized state and remain in its energized state when in the first bistable state, and causing the solenoid to switch from its energized state to its de-energized state and remain in its de-energized state when in the second bistable state.

The GFCI includes a fault detection circuit for detecting the presence of a fault condition in at least one of the lines extending between a source and a load and causing the latch circuit to latch in its second, bi-stable state upon detection of the fault condition. The fault detection circuit includes: a low power ground fault interrupter integrated circuit and an SCR driver; and at least one passive RF noise suppressor for preventing RF noise from being amplified by the integrated circuit and accidentally triggering the SCR driver. The GFCI also includes a light emitting diode circuit for indicating that the GFCI is operating properly.

Additional objects, as well as features and advantages, of the present invention will be set forth in part in the detailed description which follows, and in part will be obvious from the detailed description, or may be learned by practice of the invention. In the detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments for practicing the invention. These embodiments will be described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is best defined by the appended claims.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and together with the description, serve to explain the principles of the invention. In the drawings, like numbering represents like parts:

FIG. 1 is a schematic circuit diagram of an automatic reset Ground Fault Circuit Interrupter (GFCI) having the monitoring feature and over-voltage feature of the present invention; and

fig. 2 is a graphical representation of the timing relationship of the monitoring features shown in fig. 1.

Detailed Description

The following brief definitions of terms should be applied throughout the application:

the term "comprising" is meant to include, but is not limited to, the manner in which it is used in its general patent context;

the phrases "in one embodiment," "according to one embodiment," and the like, generally refer to: the particular features, structures, or characteristics may be included in at least one embodiment of the invention and may be included in more than one embodiment of the invention (importantly, such phrases do not necessarily refer to the same embodiment);

if the specification describes something as "exemplary" or "an example," it is understood to mean a non-exclusive example;

if the specification states a component or feature "may", "can", "will", "should", "preferred", "might", "generally", "selectively", "for example" or "may" (or other such language) to be included or to have a certain characteristic, that particular component or feature is not necessarily included or to have that characteristic.

Referring now to the drawings and in particular to fig. 1, there is shown a ground fault circuit interrupter (hereinafter "GFCI") circuit constructed in accordance with the teachings of the present invention and designated generally by reference numeral 11.

As will be discussed in detail below, after initially connecting the input terminal L to the load terminal L and the input terminal N to the load terminal N, the GFCI 11 protects the load from a ground fault condition. Further, once GFCI 11 protects the load from a ground fault condition, GFCI 11 may be reset to protect against additional ground fault conditions.

GFCI 11 includes circuit breaker 13, relay circuit 15, power supply circuit 17, fault detection circuit 21, bi-stable electronic latch circuit 23, and test circuit 27.GFCI 11 also includes an auto-monitoring end-of-life module that includes relay synchronization switch 31, analog ground fault generator 33, auto-monitoring and end-of-life logic, and end-of-life switch 35A.

The circuit breaker 13 includes a pair of single pole double throw switches SW1 and SW2, which are provided in the phase and neutral lines between the power source and the load, respectively. The circuit breaker 13 functions to selectively open and close the pair of conductive lines. The switches SW1 and SW2 can be placed in either of two connection positions. In the first connection position or disconnection position, i.e., the position shown in fig. 1, the switches SW1 and SW2 are positioned such that the input power source is not connected to the load. In a second connection position, opposite to that shown in fig. 1, the switches SW1 and SW2 are positioned such that the input power source is connected to the load. In both positions, the input power is connected to the power circuit 17.

The relay circuit 15 is used to selectively place the circuit breaker 13 in its first or second connection position. The relay circuit 15 includes a solenoid RL1a, a transistor Q2 a, and a bias circuit including a resistor R21 and a zener diode ZD 2.

The solenoid RL1a is associated with the breaker 13 contacts of the switches SW1 and SW2 and is responsible for selectively controlling the connection position of the switches SW1 and SW2. Before supplying power to the GFCI 11, the solenoid RL1a places the switches SW1 and SW2 in the first connection position as shown. When the switches SW1 and SW2 are engaged and the solenoid RL1a is energized, the solenoid RL1a holds the switches SW1 and SW2 at the second connection position.

The transistor Q2 is a high-voltage transistor for controlling the flow of current through the energized solenoid RL1a. When transistor Q2 is "off, the current through solenoid RL1a is disabled and RL1a is de-energized. When transistor Q2 is "on", current flows through solenoid RL1a, energizing RL1a.

Power supply circuit 17 provides power to GFCI circuit 11. The power supply circuit 17 includes a rectifying diode D17 and a capacitor C12. Also shown in fig. 1 is a varistor MOV1, having a value of 150 volts, for protection against electrical surges from the ac power source. The silicon rectifier D17 and the capacitor C12 convert the line ac current from the power supply into dc current.

When the switches SW1 and SW2 are in their second connection positions, the fault detection circuit 21 detects both a ground fault in the conductive line and a neutral ground condition. The fault detection circuit 21 includes a sensing transformer T1, a grounded-neutral transformer T2, a coupling capacitor C7, a feedback resistor R3, and a ground fault interrupter Integrated Circuit (IC) (GFCI IC).

The sensing transformer T1 senses the difference in current between the phase and neutral lines and in the event of a ground fault condition, the transformer T1 induces an associated output from its secondary winding. Grounded neutral transformer T2 cooperates with transformer T1 to sense the presence of a neutral-to-ground condition and thereby induce an associated output. Coupling capacitor C7 couples the ac signal from the secondary winding of transformer T1 to the GFCI IC.

After detecting a ground fault or neutral to ground condition, the GFCI IC generates an output pulse on pin 5 to activate latch circuit 23. The activated latch circuit 23 deactivates or deenergizes the solenoid RL1a via the relay synchronization switch 31. The latch circuit 23 includes a silicon controlled rectifier SCR1 operable in a conductive or non-conductive state.

The rectifier SCR1 selectively turns on and off a transistor Q2 in the relay circuit 15 via a relay synchronous switch 31, as will be discussed in more detail herein. The reset switch SW4 is a conventional push-in switch that, when pressed, removes the holding current from the anode of the rectifier SCR1, thereby turning off the rectifier SCR1 if the rectifier SCR1 is in its conducting state.

Resistor R2 and capacitor C4 act as a smoothing circuit to smooth the varying dc voltage provided by the power supply and provide a filtered dc voltage to the power input of IC U1. As discussed in more detail herein, C4 also provides temporary GFCI IC VCC when GFCI 11 is in automatic auto-monitoring mode.

Test circuit 27 provides a means of testing whether circuit 11 is functioning properly. The test circuit 27 includes a current limiting resistor R12 and a test switch SW3 of conventional push-in design. When test switch SW3 is depressed to energize test circuit 27, resistor R12 provides a simulated fault current to transformer T1 similar to a ground fault condition.

In use, GFCI 11 functions in the following manner. Prior to initial connection, the switches SW1 and SW2 are normally in the first connection position shown in fig. 1.

After one end of GFCI 11 is initially connected to the power source, a line voltage of approximately 120 volts RMS is applied to solenoid RL1a by power circuit 17. The switches SW1 and SW2 are engaged (opposite to the position shown in fig. 1), and power from the power supply circuit 17 maintains the switches SW1 and SW2 in their connected positions through the solenoid RL1a.

While solenoid RL1a remains in its energized state, rectifier SCR1 is in a non-conductive state and transistor Q2 is conductive, which enables current to flow through solenoid RL1a through Q2 to neutral. Upon detection of a ground fault or a neutral-to-ground condition, fault detection circuit 21 sends a gate signal to rectifier SCR1, bringing rectifier SCR1 into a conductive state, which in turn turns off transistor Q2 via the relay synchronous switch. With transistor Q2 off, current does not flow through solenoid RL1a, and therefore solenoid RL1a becomes de-energized. Upon de-energization, solenoid RL1a returns switches SW1 and SW2 to their first non-connected positions, thereby interrupting power from the power source to the load.

Once the fault condition is cleared, circuit 11 may be reset by depressing switch SW 4. Pressing switch SW4 causes the SCR1 to hold current off, which causes the rectifier SCR1 to turn off. This in turn causes transistor Q2 to re-conduct when switch SW4 is released, causing solenoid RL1a to re-energize. It will be appreciated that power from the power source to the load requires the engagement of switches SW1 and SW2.

120/240 switch

The 120/240 switch 101 monitors power from the power circuit 17. During normal operation, i.e., when the input power is 120 VAC, 120/240 switch 101 provides a ground or neutral path for solenoid current to go through solenoid RL1a through Q2 to neutral. If 120/240 switch 101 senses an over-voltage condition, such as 240 VAC, 120/240 switch 101 disengages the neutral path provided for solenoid current to flow through solenoid RL1a, thereby de-energizing RL1a and opening switches SW1 and SW2.

Automatic monitoring and end of life

The monitoring module 101 includes a relay synchronization switch 31, an analog ground fault generator 33, an automatic monitoring and end-of-life circuit 35, and an end-of-life switch 35A.

The Simulated Ground Fault Generator (SGFG) 33 includes the logic and devices needed to simulate a periodic ground fault. Referring to fig. 2, during normal GFCI operation, SGFG 33 is off. During the automatic monitoring window, the SGFG generates a short-circuit-on pulse, setting the basic timing of the automatic monitoring end-of-life (EOL) window. The SGFG pulse is sensed by GFCI circuit 21 as a ground fault. Upon detection of the analog ground fault, the GFCI IC generates an output pulse at pin 5 to activate latch circuit 23 (SCR 1).

When the SGFG 33 generates a short circuit on pulse for the purpose of automatically monitoring the ground fault detection circuit 21, the SGFG pulse is also sensed by the GFCI relay synchronization switch 31, the relay synchronization switch 31 including the logic and devices necessary to temporarily isolate the normal GFCI fault detection described above. The GFCI components under test include a sensing transformer T1, a grounding transformer T2, a GFCI IC, and a bistable electronic latch circuit 23.

It will be appreciated that the timing window or pulse period set by the SGFG has a duration short enough such that when K1 is temporarily isolated by the relay synchronization switch 31 during the auto-monitoring EOL window, the charge on capacitor C4 is sufficient to maintain power to the GFCI IC for the duration of the auto-monitoring EOL window.

The auto-monitoring and EOL logic (monitoring) circuit 35 determines the number of times the SCR1 is not turned on during successive auto-monitoring EOL windows. As shown in fig. 2, if the test problem "SCR1 on? "off" then SCR1 is not turned on. If SCR1 is not turned on a predetermined number of times, the GFCI fault detection circuit is faulty and the EOL switch 35A is activated, thereby de-energizing solenoid K1.

The invention described above is intended to be merely exemplary, and those skilled in the art should be able to make various changes and modifications thereto without departing from the spirit of the invention. All such variations and modifications are intended to fall within the scope of the present invention as defined in the appended claims.

Claims

1. A test protection circuit for interrupting current flowing through a pair of lines, wherein one of the pair of lines extends between a phase input and a phase output and the other line extends between a neutral input and a neutral output, the test protection circuit comprising:

a Ground Fault Circuit Interrupter (GFCI), wherein the GFCI comprises:

a power circuit for supplying current to the GFCI,

a first switch having a first input terminal and a first contact terminal;

a second switch having a second input terminal and a second contact terminal, wherein the first switch is ganged with the second switch;

a relay circuit for controlling the first and second switches, wherein each switch includes a first position in which it is de-energized and a second position in which it is energized, and wherein the first switch is connected between the phase input and the phase output, and wherein the second switch is connected between the neutral input and the neutral output;

a fault detection circuit for detecting a ground fault in the pair of lines, wherein the relay circuit includes a solenoid;

a first bi-stable electronic latch circuit for de-energizing the relay circuit upon detection of a fault;

a monitoring module integrated with the GFCI, the monitoring module comprising:

the analog ground fault generator is used for generating a ground fault starting pulse and testing the fault detection circuit and the first bistable electronic latch circuit;

a relay synchronization switch for isolating the GFCI during a ground fault on pulse;

an automatic monitoring logic module for monitoring said first bi-stable electronic latch circuit during a ground fault enable pulse; and

an end-of-life switch that disables the relay circuit if the automatic monitoring logic determines that the first bi-stable electronic latch circuit has failed.

2. The test protection circuit of claim 1, wherein the first bi-stable electronic latch circuit comprises a Silicon Controlled Rectifier (SCR).

3. The test protection circuit of claim 1, wherein the fault detection circuit comprises:

a sensing transformer;

a grounded neutral transformer; and

a GFCI Integrated Circuit (IC) coupled to the sense transformer and a grounded-neutral transformer.

4. The test protection circuit of claim 3, wherein the fault detection circuit comprises a power capacitor for providing power to the GFCI integrated circuit when the GFCI is isolated by the relay synchronous switch during a ground fault opening pulse.

5. The test protection circuit of claim 2, wherein the automatic monitoring logic module comprises a GFCI circuit responsive to a predetermined number of failures of the GFCI circuit simulating a ground fault opening pulse to test the GFCI circuit, wherein the GFCI circuit under test comprises:

a sensing transformer;

a grounded neutral transformer;

a GFCI Integrated Circuit (IC) coupled to the sense transformer and a grounded-neutral transformer; and

the first bi-stable electronic latch circuit.

6. The test protection circuit of claim 1, further comprising an overvoltage monitoring circuit.

7. The test protection circuit of claim 6, wherein the over-voltage monitoring circuit de-energizes the solenoid if a predetermined voltage is detected that exceeds 120 VAC.

8. A GFCI circuit for interrupting current flowing through a pair of lines, one of the pair of lines extending between a phase input and a phase output and the other line extending between a neutral input and a neutral output, the GFCI circuit comprising:

a fault detection circuit for detecting a ground fault in the pair of lines;

a relay circuit for controlling a first switch and a second switch, wherein each switch includes a first position in which it is de-energized and a second position in which it is energized, and wherein the first switch is connected between the phase input and the phase output, and wherein the second switch is connected between the neutral input and the neutral output;

a first bi-stable electronic latch circuit for de-energizing the relay circuit when the fault detection circuit detects a fault;

a monitoring module integrated with the GFCI, the monitoring module comprising:

the analog ground fault generator is used for generating a ground fault starting pulse and testing a fault detection circuit component;

a relay synchronization switch for isolating the fault detection circuit during a ground fault on pulse; and

wherein the fault detection circuit includes a power capacitor for providing power to the GFCI integrated circuit when the GFCI is isolated by the relay synchronous switch during a ground fault opening pulse.

9. The GFCI circuit of claim 8, wherein the monitoring module further comprises:

an automatic monitoring logic module for monitoring said first bi-stable electronic latch circuit during a ground fault enabling pulse; and

10. The GFCI circuit of claim 8, wherein the fault detection circuit component under test comprises:

a sensing transformer;

a grounded neutral transformer;

the first bi-stable electronic latch circuit.

11. A method for intermittently testing components of a Ground Fault Circuit Interrupter (GFCI) for interrupting power between a phase input and a phase output, the method comprising:

providing a simulated ground fault generator for generating a ground fault test on pulse;

providing a relay for controlling the switch to interrupt power between the phase input and the phase output when the relay is de-energized;

providing a relay synchronous switch for isolating the relay for the duration of a ground fault test starting pulse;

turning on a first bi-stable electronic latch circuit during a ground fault test turn-on pulse; and

a monitoring circuit is provided for detecting a turn-on failure of the first bi-stable electronic latch circuit during a ground fault test turn-on pulse.

12. The method of claim 11, further comprising providing an end-of-life switch that de-energizes a relay if the monitoring circuit determines that the first bi-stable electronic latch circuit has failed.

13. The method of claim 11, further comprising providing a 120/240V switch that de-energizes the relay if the 120/240V switch determines an overvoltage condition.

14. A switched test protection circuit for interrupting current flowing through a pair of lines, wherein one of the pair of lines extends between a phase input and a phase output and the other line extends between a neutral input and a neutral output, the test protection circuit comprising:

a Ground Fault Circuit Interrupter (GFCI), wherein the GFCI comprises:

a switched first switch having a first input terminal and a first contact terminal;

a second switch of the switch type having a second input terminal and a second contact terminal, wherein the first switch is ganged with the second switch;

a relay circuit connected to a first switch and a second switch, wherein each switch includes an on position and an off position, and wherein the first switch is connected between the phase input and the phase output, and the second switch is connected between the neutral input and the neutral output;

a fault detection circuit for detecting a ground fault in the pair of lines, and the relay circuit includes a solenoid;

a 120/240V switch that de-energizes the relay if the 120/240V switch determines an over-voltage condition;

a monitoring module integrated with a GFCI, the monitoring module comprising:

a relay synchronization switch for isolating the relay circuit during a ground fault opening pulse;

an end-of-life switch to disable the relay circuit if the automatic monitoring logic module determines that the first bi-stable electronic latch circuit has failed.

15. The switched mode test protection circuit of claim 14, wherein the fault detection circuit comprises:

a sensing transformer;

a grounded neutral transformer; and

16. The switched mode test protection circuit of claim 15, wherein the automatic monitoring logic module comprises:

testing the GFCI circuit in response to a predetermined number of failures of the GFCI circuit simulating a ground fault opening pulse, wherein the GFCI circuit under test comprises:

a sensing transformer;

a grounded neutral transformer;

a GFCI Integrated Circuit (IC) coupled to the sense transformer and the grounded-neutral transformer; and

a first bi-stable electronic latch circuit.