CN115312111A

CN115312111A - Dynamic random access memory testing method and device

Info

Publication number: CN115312111A
Application number: CN202110497958.6A
Authority: CN
Inventors: 闫以建; 郭江; 王玉洁; 王辉; 崔延卿; 赵战伟; 张晓敏
Original assignee: Beijing Huawei Digital Technologies Co Ltd
Current assignee: Beijing Huawei Digital Technologies Co Ltd
Priority date: 2021-05-07
Filing date: 2021-05-07
Publication date: 2022-11-08

Abstract

The embodiment of the application discloses a dynamic random access memory testing method.A controller acquires a step skipping mode, and the step skipping mode represents an addressing mode of a storage unit. And aiming at each column of the DRAM, carrying out addressing operation on the memory cells in the column according to a preset skipping mode to obtain an addressing result, thereby realizing the addressing operation on all the columns. After obtaining the addressing result, the controller may determine the test result based on the addressing result. That is, after the controller performs addressing operation on the memory unit according to the preset skipping mode, the fault type of the DRAM can be determined according to the addressing result to cover different fault types, so that the DRAM can be comprehensively tested.

Description

Dynamic random access memory testing method and device

Technical Field

The present application relates to the field of memory device processing technologies, and in particular, to a method and an apparatus for testing a dynamic random access memory.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor memory, and since the DRAM can store data only for a short time, the DRAM must be refreshed once every certain time in order to maintain the data. As shown in fig. 1a, the basic memory cell of a DRAM is composed of a Transistor (Transistor) and a Capacitor (Capacitor), and the operation principle is that when a Word Line (WL) is gated, the Transistor is turned on, and information stored in the Capacitor can be read through a Bit Line (BL), i.e., a data line. The state of the capacitor determines whether the logic state of the memory cell is 1 or 0. Specifically, a charged capacitance is considered a logical 1 in the digital electron, while an "empty" capacitor is a 0.

With the development of technology, the performance of DRAM is higher and higher, and the fabrication process size is smaller and smaller. In order to improve the stability of the DRAM operation, the performance of the DRAM needs to be tested. However, the current DRAM test algorithm can only test one or several types of failure types, and cannot cover other newly added failure types, so that the DRAM cannot be tested in all directions.

Disclosure of Invention

The embodiment of the application provides a dynamic random access memory testing method and device, so that the fault type of a DRAM (dynamic random access memory) can be comprehensively detected, and the stability of the DRAM is improved.

In a first aspect of embodiments of the present application, a dynamic random access memory testing method is provided, where the method includes: the controller acquires a skipping mode, wherein the skipping mode is used for indicating an addressing mode; aiming at any column in a Dynamic Random Access Memory (DRAM), the controller carries out addressing operation on the storage units in the column according to the step skipping mode to obtain an addressing result; and determining a test result according to the addressing result.

Through the implementation mode, after the controller carries out addressing operation on the storage unit according to the preset skipping mode, the fault type of the DRAM can be determined according to the addressing result so as to cover different fault types, and therefore comprehensive testing of the DRAM is achieved. For example, when the controller can normally address each memory cell, the controller reads first data from the memory cells of the DRAM and determines a test result according to the first data and the second data after completing an address operation for all columns. For example, when the first data and the second data are not identical, it may be determined that the DRAM has a leakage fault such that the written second data becomes the first data. It can be seen that, by the above test method, the memory cells in the columns are addressed in a preset skipping manner in columns, so that the current frequent switching is realized, the leakage voltage of the adjacent rows is enhanced, and the detection of the leakage fault of the adjacent rows caused by the frequent switching of the rows can be realized. For another example, when the controller cannot address the memory cell normally, it indicates that there is an address line timing margin failure, resulting in an addressing problem.

In a specific implementation manner, the determining a test result according to the addressing result includes: the controller determines that an address timing margin fault exists in the DRAM when the addressing result includes that the memory cell cannot be addressed.

In this implementation, if the controller cannot address the memory cell normally, it indicates that the current skipping mode causes a large decoding pressure, resulting in an address decoding error, and the memory cell cannot be addressed.

In a specific implementation manner, the determining a test result according to the addressing result includes: when the addressing result comprises that the storage unit can be addressed, the controller determines a test result according to first data and second data, wherein the first data are data read from the storage unit when the storage unit is addressed, and the second data are data written into the storage unit in advance before the addressing operation.

In this implementation, when the controller can normally perform a normal addressing operation on the memory cell, the first data is read from the memory cell, and compared according to the second data written in advance, and a test result is determined according to the comparison result, so as to find out whether the data in the memory cell is changed. If a change occurs, it indicates that a leakage fault occurs during addressing.

In a specific implementation, before the controller determines the test result according to the first data and the second data, the method further includes: the controller reads first data from the memory cell.

In a specific implementation manner, for any column in the dynamic random access memory DRAM, the controller performs an addressing operation on the memory cells in the column according to the skipping manner, and obtains an addressing result, including: the controller acquires a hit coefficient corresponding to a Dynamic Random Access Memory (DRAM), wherein the hit coefficient represents the average opening times of storage units in the DRAM; and aiming at any column in the DRAM, the controller carries out addressing operation on the storage unit in the column according to the skipping mode until the starting times of the storage unit are matched with the hit coefficient, and an addressing result is obtained.

In the implementation mode, the number of times that the memory unit is started is matched with the hit coefficient by defining the hit coefficient concept, so that the leakage fault caused by the influence of the memory unit on the neighbor memory unit is excited, and the leakage fault is detected.

In a specific implementation, the determining, by the controller, the test result according to the first data and the second data includes: when the first data and the second data are not the same, the controller determines that a leakage fault exists in a memory cell in the DRAM.

In one particular implementation, the leakage fault includes a fault in which a frequently switched row causes leakage of memory cells of an adjacent row.

In a specific implementation, the skipping manner comprises one or more of ascending addressing, descending addressing, skipping addressing or Pseudo Random Binary Sequence (PRBS) addressing.

In a specific implementation manner, when the skipping manner is the PRBS addressing, the controller performs an addressing operation on the memory cell in the column according to the skipping manner to obtain an addressing result, including: the controller obtains an addressing sequence corresponding to the PRBS addressing according to the random seed;

and the controller carries out addressing operation on the storage units in the column according to the addressing sequence to obtain an addressing result.

In a specific implementation manner, before the controller performs the addressing operation on the memory cells in the column according to the skipping manner, the method further includes: the controller writes the second data to memory cells in the DRAM.

In a specific implementation, the method further includes: the controller writes third data to memory cells in the DRAM when the first data is the same as the second data; aiming at any row of storage units in the DRAM, the controller carries out addressing operation on the storage units in the row according to the step skipping mode until the opening times of the storage units are matched with the hit coefficient; the controller acquires fourth data in a storage unit in the DRAM; and determining a test result according to the third data and the fourth data.

In a particular implementation, the addressing operation includes a read operation on the memory cell.

In one particular implementation, the controller tests the DRAM through a built-in self test BIST interface.

In one particular implementation, different columns in the DRAM correspond to different hit coefficients.

In a specific implementation manner, the matching between the number of times of turning on the memory unit and the hit coefficient includes that the number of times of turning on is equal to the hit coefficient, or that a difference between the number of times of turning on and the hit coefficient is smaller than a preset threshold.

In a second aspect of the embodiments of the present application, there is provided a test system, the system including a controller and a dynamic random access memory DRAM, the controller and the DRAM being connected through a peripheral circuit; the controller acquires a step skipping mode, and the step skipping mode is used for indicating an addressing mode; the controller is further configured to perform, for any one column in the dynamic random access memory DRAM, an addressing operation on the memory cell in the column according to the skipping mode to obtain an addressing result; the controller is further configured to determine a test result according to the addressing result.

In a third aspect of embodiments of the present application, there is provided a dynamic random access memory testing apparatus, including: the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a skipping mode, and the skipping mode is used for indicating an addressing mode; the addressing unit is used for addressing the storage units in any column in the DRAM according to the skipping mode to obtain an addressing result; and the determining unit is used for determining a test result according to the addressing result.

In a fourth aspect of embodiments of the present application, there is provided a communication device, including: a processor and a memory; the memory for storing instructions or computer programs; the processor is configured to execute the instructions or computer program in the memory to cause the communication device to perform the method of the first aspect.

In a fifth aspect of embodiments herein, there is provided a computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of the first aspect above.

According to the technical scheme provided by the embodiment of the application, the controller acquires a step skipping mode, and the step skipping mode represents an addressing mode of the storage unit. And aiming at each column of the DRAM, carrying out addressing operation on the memory cells in the column according to a preset skipping mode to obtain an addressing result, thereby realizing the addressing operation on all the columns. After obtaining the addressing result, the controller may determine the test result based on the addressing result. That is, after the controller performs addressing operation on the memory unit according to the preset skipping mode, the fault type of the DRAM can be determined according to the addressing result to cover different fault types, so that the DRAM can be comprehensively tested. For example, when the controller can normally address each memory cell, the controller reads first data from the memory cells of the DRAM and determines a test result according to the first data and the second data after completing an address operation for all columns. For example, when the first data and the second data are not identical, it may be determined that the DRAM has a leakage fault such that the written second data becomes the first data. It can be seen that, by the above test method, the memory cells in the columns are addressed in a preset skipping manner in columns, so that the current frequent switching is realized, the leakage voltage of the adjacent rows is enhanced, and the detection of the leakage fault of the adjacent rows caused by the frequent switching of the rows can be realized. For another example, when the controller cannot address the memory cell normally, it indicates that there is an address line timing margin failure, resulting in an addressing problem.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1a is a schematic diagram of a memory cell structure;

fig. 1b is a schematic view of an application scenario provided in the embodiment of the present application;

FIG. 2 is a flowchart of a DRAM testing method according to an embodiment of the present disclosure;

FIG. 3a is a schematic diagram of ascending addressing according to an embodiment of the present application;

FIG. 3b is a schematic diagram of descending addressing provided by an embodiment of the present application;

FIG. 3c is a diagram illustrating ascending skip order addressing according to an embodiment of the present application;

FIG. 3d is a diagram illustrating descending jump addressing according to an embodiment of the present application;

FIG. 3e is a schematic diagram of circular addressing provided by an embodiment of the present application;

FIG. 3f is a schematic diagram of PRBS addressing provided by an embodiment of the present application;

FIG. 4 is a flow chart of another DRAM testing method according to an embodiment of the present application;

fig. 5 is a structural diagram of a test system according to an embodiment of the present application;

FIG. 6 is a block diagram of an apparatus for testing a DRAM according to an embodiment of the present disclosure;

fig. 7 is a structure diagram of a network device according to an embodiment of the present application;

fig. 8 is a diagram of another network device structure according to an embodiment of the present application.

Detailed Description

In order to make those skilled in the art better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

With the higher and higher memory performance of the DRAM, algorithms for testing the DRAM are more and more, such as March algorithm, three-step method, graphic algorithm, rowhammer algorithm, and the like. The March algorithm is used for fault excitation and detection through a series of March primitives, wherein the March primitives are related to specific address steps, read-write operations and data inversion, and most storage unit type faults can be covered. The three-step method is used for reversely detecting faults of the data line and the address line by constructing the walk 0 and the walk 1 of the data line and the address line through basic address reading and writing and address walking. And the pattern type algorithm is used for detecting the fault that the content of one storage unit is attacked by the content of a group of other storage units through a specific pattern type walking design. The Rowhammer algorithm selects a fixed row in a refresh period, writes an opposite value compared with an adjacent row to the row, repeatedly accesses the row, observes the influence on the upper row and the lower row, causes the leakage of charges of a storage unit and possibly causes bit inversion, and is used for exciting the Rowhammer problem. The algorithm detects the effect of a read operation being continued on a row on the memory cells of other rows. That is, the above algorithm mainly centers on the detection of memory cell failure, address decoding failure, read-write logic failure, and internal and external interface failure.

As the process size of DRAMs becomes smaller, the failure of frequent switching of a row to cause leakage of neighboring rows will occur. Specifically, when a certain row is turned on, crosstalk occurs due to a voltage coupling effect, so that an adjacent off row is in a weak on state, and further, charge loss of an adjacent memory cell is caused. When a row is frequently turned on, the charge loss of the adjacent memory cells is more, resulting in the loss of the state of the memory cells, which seriously affects the data reliability. As shown in fig. 1b, when the row corresponding to WL2 is frequently turned on, the row corresponding to WL1 is caused to be in a weak on state, so that the memory cells in the row corresponding to WL1 have leakage fault and the state is lost. However, the current DRAM test algorithm cannot effectively detect the leakage failure mode, which affects the stability of the DRAM.

Based on this, the embodiment of the application provides a dynamic random access memory testing method, which is used for solving the problem that the traditional detection algorithm cannot cover the detection of the leakage fault of the adjacent rows caused by frequent switching rows. The DRAM may include, but is not limited to, synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM (DDR), DDR (graphics double data rate, version 5, gddr5), DDR (graphics double data rate, version 6, gddr6), low power SDRAM (low power DDR, LPDDR 2, DDR3, DDR4, and DDR5, etc.

For the sake of understanding, a dynamic random access memory testing method provided by the embodiments of the present application will be described below with reference to the accompanying drawings.

Referring to fig. 2, which is a flowchart of a dynamic random access memory testing method provided in an embodiment of the present application, as shown in fig. 2, the method may include:

s201: the controller obtains a skip mode, which is used to indicate an addressing mode.

In this embodiment, the addressing mode for the memory unit may be set in advance in the controller, and the addressing mode may include, but is not limited to, ascending addressing, descending addressing, jump addressing, circular addressing, and Pseudo Random Binary Sequence (PRBS) addressing. The ascending addressing may be an addressing operation from a lower address to a higher address according to a unit step size. As shown in fig. 3a, a column in the DRAM includes 8 memory cells with corresponding addresses of 000, 001, 010, 011, 100, 101, 110, 111, respectively, and the controller addresses from 000 to 111 in ascending order. Wherein, the descending addressing can be the addressing operation from the high address to the low address according to the unit step size. As shown in fig. 3b, the controller addresses from 111 to 000 in descending order addressing. The jump addressing may be jump addressing according to a preset step size, where the preset step size is larger than a unit step size, and may include jump ascending addressing and jump descending addressing. As shown in fig. 3c and 3d, the preset step size is 2 unit step sizes. Circular addressing may be such that the addressing operation is from low to high and then from high to low, or from high to low and then from low to high. For example, as shown in fig. 3e, the controller performs the addressing operation according to a method from a low address to a high address and then from the high address to the low address. The PRBS addressing is addressing according to a randomly generated binary sequence, as shown in fig. 3f, where the binary sequence is 100101111011 … …, and the controller sequentially addresses address 100, address 101, address 111, and address 011 according to the binary sequence.

It should be noted that, in this embodiment, the addressing pressure on the DRAM may be increased by setting the skipping manner, so as to trigger a possible failure of the DRAM under the action of a larger addressing pressure.

S202: aiming at any column in the DRAM, the controller carries out addressing operation on the storage units in the column according to a skipping mode, and an addressing result is obtained.

In this embodiment, after obtaining the preset skipping modes, for any column in the DRAM, the controller may select one of the skipping modes to perform an addressing operation on the memory cell in each column, or select multiple skipping modes to perform an addressing operation on the memory cell in the column respectively. For example, if the controller selects the ascending addressing, the memory cells in each column of the DRAM are addressed in the ascending addressing mode. For another example, if the controller selects the ascending addressing and the PRBS addressing, then for each column in the DRAM, the memory cells in the column are addressed in the ascending addressing mode, and when the memory cells in all the columns are addressed in the ascending addressing mode, the memory cells in each column are addressed in the PRBS addressing mode. The addressing operation can include two operation modes, wherein one mode is that no read/write operation is carried out, and only addressing is carried out; the other is to perform a read operation.

It should be noted that, when the controller performs an addressing operation on a certain column of memory cells in a PRBS addressing manner, an addressing sequence corresponding to PRBS addressing is obtained according to the random seed, and then the controller performs an addressing operation on the memory cells in the column according to the addressing sequence to obtain an addressing result. That is, when PRBS addressing different columns, the addressing sequence will be determined from the random seed. For example, when PRBS addressing is performed on the first column of DRAM, its corresponding binary sequence (addressing sequence) is 100101111011 … …; upon PRBS addressing the second column, the binary sequence is retrieved as 001111101110 … ….

It should be noted that, a certain column in the DRAM may be addressed according to a preset skipping manner, and all columns in the DRAM may also be addressed according to the preset skipping manner. That is, the outer layer performs addressing between rows in units of columns in the ascending addressing, descending addressing, jump addressing, PRBS addressing, etc., and the inner layer performs addressing between rows in units of rows in the ascending addressing, descending addressing, jump addressing, PRBS addressing, etc.

S203: and determining a test result according to the addressing result.

After the controller performs an addressing operation on the memory cells in the DRAM, an addressing result is obtained. The addressing result may be that the controller can normally address the memory cell, or may include that the controller cannot normally address the memory cell. The controller will obtain different test results for different addressing results as described above.

In a specific implementation manner, when a controller performs addressing access on a memory cell in a DRAM, if an address operation cannot be performed on the memory cell, it is determined that the DRAM has an address timing margin fault, which causes an addressing problem, and a specific memory cell cannot be located. When the address timing allowance fault is used for indicating that the memory cell is addressed in a step skipping mode, address decoding is wrong due to high addressing pressure, and the memory cell cannot be addressed.

In a specific implementation mode, when the controller performs addressing access on the memory cells in the DRAM, if the controller can perform normal addressing operation on the memory cells, the controller reads first data in each memory cell in the DRAM; the controller determines a test result based on the first data and the second data. That is, after the controller performs an addressing operation on the memory cells in each column of the DRAM in a preset skipping manner, the first data in each memory cell is read from the DRAM, and the test result of the memory cell is determined according to the first data and the second data. Specifically, when the first data and the second data of a certain memory cell are not the same, it indicates that the memory cell has a leakage fault, and the data in the memory cell changes, i.e., the second data changes into the first data. The leakage fault may include a fault in which the frequently switched rows cause leakage of memory cells of adjacent rows.

It should be noted that the test method provided in this embodiment may also detect an interface fault, an internal memory cell and read/write logic fault, and a Rowhammer fault, so as to verify the reliability of the DRAM.

As can be seen from the above, the controller acquires a skip mode indicating an addressing mode for the memory cell. And aiming at each column of the DRAM, carrying out addressing operation on the memory cells in the column according to a preset skipping mode to obtain an addressing result, thereby realizing the addressing operation on all the columns. After obtaining the addressing result, the controller may determine the test result based on the addressing result. That is, after the controller performs addressing operation on the memory unit according to the preset skipping mode, the fault type of the DRAM can be determined according to the addressing result to cover different fault types, so that the DRAM can be comprehensively tested. For example, when the controller can normally address each memory cell, the controller reads first data from the memory cells of the DRAM and determines a test result according to the first data and the second data after completing an address operation for all columns. For example, when the first data and the second data are not the same, it may be determined that the DRAM has a leakage failure such that the written second data becomes the first data. It can be seen that, by the above test method, the memory cells in the columns are addressed in a preset skipping manner in columns, so that the current frequent switching is realized, the leakage voltage of the adjacent rows is enhanced, and the detection of the leakage fault of the adjacent rows caused by covering the frequently switched rows can be realized. For another example, when the controller cannot address the memory cell normally, it indicates that there is an address line timing margin failure, resulting in an addressing problem.

In the above embodiments, the controller may detect not only the address timing margin fault but also the leakage fault, and for understanding the detection of the leakage fault, the following description will be made with reference to the accompanying drawings.

Referring to fig. 4, which is a flowchart of another dynamic random access memory testing method provided in the embodiment of the present application, as shown in fig. 4, the method may include:

s401: the controller writes the second data to the memory cells of the DRAM. In this embodiment, the controller writes the second data in all the memory cells of the DRAM before testing the DRAM. Wherein, the second data may be all 1 or all 0. For example, the second data is all 1, that is, all 1 are stored in all memory cells of the DRAM. Alternatively, the second data may be non-all-1 or non-all-0 data, for example, if the length of the memory cell is 8 bits, the second data may be 10010000, 11000000, or 10100101, etc.

S402: the controller obtains the hit coefficient corresponding to the DRAM.

In this embodiment, in order to stimulate the occurrence of various faults with a greater probability, a concept of a hit coefficient is proposed, where the hit coefficient indicates an average turn-on number of a certain column of memory cells. The larger the number of hits, the larger the number of times the memory cell can be turned on, and the larger its influence on the memory cells of the adjacent row. The hit number can be determined by specific actual measurement, verification and device specification. The hit coefficient may be defined as: the total number of times the operation row of the current column is frequently switched/the number of memory cells of the current column. In particular, the hit coefficients for different columns may be the same, e.g., all columns correspond to the same hit coefficient. Alternatively, the hit coefficients for different columns may be different. The setting of the hit coefficient is determined according to actual conditions, and the embodiment is not limited herein.

S403: and the controller carries out addressing operation on the memory cells in a certain column according to a preset skipping mode until the starting times of the memory cells are matched with the hit coefficient, and an addressing result is obtained.

In this embodiment, after the controller obtains the hit coefficient corresponding to the DRAM, the controller may perform an addressing operation on a certain row of memory cells according to a preset skipping mode until the number of times of starting the memory cells matches the hit coefficient, and obtain an addressing result. The addressing result may include that the controller may normally perform a normal read operation on the memory cell. The matching between the turn-on number of the memory cell and the hit coefficient may be that the turn-on number is equal to the hit coefficient, or that a difference between the turn-on number and the hit coefficient is smaller than a preset threshold. The purpose of addressing is to turn on the transistors of the memory cells in the column, so that the transistors are turned on to perform addressing operation on the memory cells, and further, the memory cells in the adjacent rows can be caused to be in a weak on state. For example, as shown in fig. 3a, the controller performs an address operation to address 001, triggering the transistor of the memory cell 001 to conduct, which may cause the

memory cells

000 and 010 to be in a weak on state.

The implementation of the manner of acquiring the skipping steps by the controller can be referred to the relevant description of S201 in the embodiment shown in fig. 2.

S404: the controller reads the first data from the memory cell.

S405: the controller determines a test result based on the first data and the second data.

When the controller performs addressing access on the memory cells in the DRAM, if the controller can perform normal addressing operation on the memory cells, the controller reads first data in each memory cell in the DRAM; the controller determines a test result based on the first data and the second data. That is, after the controller performs an addressing operation on the memory cells in each column of the DRAM in a preset skipping manner, the first data in each memory cell is read from the DRAM, and the test result of the memory cell is determined according to the first data and the second data.

Specifically, when the first data and the second data of a certain memory cell are not the same, it indicates that the memory cell has a leakage fault, and the data in the memory cell changes, i.e., the second data changes into the first data. The leakage fault may include a fault in which frequently switching rows causes leakage of memory cells of adjacent rows.

When the first data is the same as the second data, in order to ensure the accuracy of the test, the controller can also write third data into the storage unit in the DRAM; aiming at any row of memory cells in the DRAM, the controller carries out addressing operation on the memory cells in the row according to a preset skipping mode until the starting times of the memory cells are matched with a hit coefficient; the controller acquires fourth data in a storage unit in the DRAM; and determining a test result according to the third data and the fourth data. The third data and the second data may be related, for example, the second data is all 1, and the third data is all 0.

Based on the above method embodiments, embodiments of the present application provide a test system and a test apparatus, which will be described below with reference to the accompanying drawings.

Referring to fig. 5, which is a block diagram of a test system according to an embodiment of the present disclosure, as shown in fig. 5, the system may include a controller 501 and a DRAM502. The controller 501 is connected with the DRAM502 through a peripheral circuit;

the controller 501 acquires a step skipping mode, and the step skipping mode is used for indicating an addressing mode;

the controller 501 is further configured to perform, for any column in the dynamic random access memory DRAM, an addressing operation on the memory cell in the column according to the skipping manner, so as to obtain an addressing result;

the controller 501 is further configured to determine a test result according to the addressing result.

For specific implementation of the controller, reference may be made to related descriptions of the method embodiments shown in fig. 2 or fig. 4, and details of this embodiment are not repeated herein.

Referring to fig. 6, which is a block diagram of a dynamic random access memory testing apparatus according to an embodiment of the present application, as shown in fig. 6, the apparatus 600 can be applied to a controller, and performs functions of the controller according to the above method embodiment, where the apparatus 600 may include: an acquisition unit 601, an addressing unit 602 and a determination unit 603.

An obtaining unit 601, configured to obtain a skipping mode, where the skipping mode is used to indicate an addressing mode. For specific implementation of the obtaining unit 601, reference may be made to the related description of S201 in the embodiment shown in fig. 2.

And the addressing unit 602 is configured to perform, for any column in the DRAM, an addressing operation on the memory cells in the column according to the skipping manner, so as to obtain an addressing result. For the specific implementation of the addressing unit 602, reference may be made to the description related to S202 in the embodiment shown in fig. 2, or to the description related to S403 in the embodiment shown in fig. 4.

A determining unit 503, configured to determine a test result according to the addressing result. For the specific implementation of S503, reference may be made to the related description of S203 in the embodiment shown in fig. 2.

In a specific implementation, the determining unit 603 is specifically configured to determine that the DRAM has an address timing margin fault when the addressing result includes that the memory cell cannot be addressed.

In a specific implementation manner, the determining unit 603 is specifically configured to determine, when the addressing result includes that the memory cell can be addressed, a test result according to first data and second data, where the first data is data read from the memory cell when the memory cell is addressed, and the second data is data that is written into the memory cell in advance before the addressing operation is performed.

In a specific implementation manner, the apparatus further includes: a reading unit (not shown in the drawings);

a reading unit for reading the first data from the storage unit before the determining unit 603 determines the test result according to the first data and the second data.

In a specific implementation manner, the addressing unit 602 is specifically configured to obtain a hit coefficient corresponding to a dynamic random access memory DRAM, where the hit coefficient represents an average number of times of turning on a storage unit in the DRAM; and aiming at any column in the DRAM, carrying out addressing operation on the storage unit in the column according to the skipping mode until the starting times of the storage unit are matched with the hit coefficient, and obtaining an addressing result.

In a specific implementation manner, the determining unit 603 is specifically configured to determine that a leakage fault exists in a memory cell in the DRAM when the first data and the second data are not the same.

In a specific implementation manner, when the skipping manner is the PRBS addressing, the addressing unit 602 is specifically configured to obtain an addressing sequence corresponding to the PRBS addressing according to a random seed; and carrying out addressing operation on the storage units in the column according to the addressing sequence to obtain an addressing result.

In a specific implementation manner, the apparatus further includes: a writing unit (not shown in the figure);

the writing unit is configured to write the second data into the memory cells in the DRAM before the addressing unit 602 performs the addressing operation on the memory cells in the column according to the skipping manner.

In a specific implementation manner, the apparatus further includes: a write unit and a read unit (not shown in the figure);

the writing unit is used for writing third data into a storage unit in the DRAM when the first data is the same as the second data; aiming at any row of memory cells in the DRAM, carrying out addressing operation on the memory cells in the row according to the skipping mode until the opening times of the memory cells are matched with the hit coefficient;

the reading unit is used for acquiring fourth data in a storage unit in the DRAM;

the determining unit 603 is configured to determine a test result according to the third data and the fourth data.

In a specific implementation manner, the matching between the turn-on number of the storage unit and the hit coefficient includes that the turn-on number is equal to the hit coefficient, or that a difference between the turn-on number and the hit coefficient is smaller than a preset threshold.

It should be noted that, for specific implementation of each unit in this embodiment, reference may be made to related description in the method embodiment shown in fig. 2 or fig. 4, and details of this embodiment are not repeated herein.

Fig. 7 is a schematic structural diagram of a network device provided in an embodiment of the present application, where the network device may be, for example, a controller in the embodiment shown in fig. 2, or may also be a device implementation of the apparatus 600 in the embodiment shown in fig. 6.

Referring to fig. 7, the network device 700 includes at least a processor 710. Network device 700 may also include a communication interface 720 and memory 730. The number of the processors 710 in the network device 700 may be one or more, and fig. 7 illustrates one processor as an example. In the embodiment of the present application, the processor 710, the communication interface 720 and the memory 730 may be connected by a bus system or other means, wherein fig. 7 is exemplified by the connection via the bus system 740.

The processor 710 may be a CPU, an NP, or a combination of a CPU and an NP. The processor 710 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

When the network device is a controller, the processor 710 may perform related functions of obtaining the hit coefficient corresponding to the DRAM and performing an addressing operation on the memory cell according to a preset skipping manner in the foregoing method embodiment.

Communication interface 720 is used to receive and send messages, and in particular, communication interface 720 may include a receive interface and a transmit interface. The receiving interface may be configured to receive a message, and the sending interface may be configured to send a message. The number of the communication interfaces 720 may be one or more.

Memory 730 may include volatile memory (RAM), such as random-access memory (RAM); the memory 730 may also include a non-volatile memory (e.g., flash memory), a hard disk (HDD) or a solid-state drive (SSD); memory 730 may also comprise a combination of memories of the types described above.

Optionally, memory 730 stores an operating system and programs, executable modules or data structures, or subsets thereof, or expansions thereof, wherein the programs may include various operational instructions for performing various operations. The operating system may include various system programs for implementing various basic services and for handling hardware-based tasks. The processor 710 can read the program in the memory 730 to implement the testing method of the dynamic random access memory provided by the embodiment of the present application.

The storage 730 may be a storage device in the network device 700, or may be a storage device independent from the network device 700.

The bus system 740 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus system 740 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 7, but this is not intended to represent only one bus or type of bus.

Fig. 8 is a schematic structural diagram of another network device 800 provided in this embodiment of the present application, where the network device 800 may be configured as a controller in the foregoing embodiment, or implemented by the apparatus 600 in the embodiment shown in fig. 6.

The network device 800 includes: a main control board 810 and an interface board 830.

The main control board 810 is also called a Main Processing Unit (MPU) or a route processor card (route processor card), and the main control board 810 controls and manages each component in the network device 800, including routing computation, device management, device maintenance, and protocol processing functions. The main control board 810 includes: a central processor 811, and a memory 812.

The interface board 830 is also called a Line Processing Unit (LPU), a line card (line card), or a service board. The interface board 830 is used to provide various service interfaces and implement packet forwarding. The service interfaces include, but are not limited to, ethernet interfaces, such as Flexible Ethernet services interfaces (FlexE Ethernet Clients), POS (Packet over SONET/SDH) interfaces, and the like. The interface board 830 includes: a central processor 831, a network processor 832, a forwarding table entry memory 834, and a Physical Interface Card (PIC) 833.

The central processor 831 on the interface board 830 is used for controlling and managing the interface board 830 and communicating with the central processor 811 on the main control board 810.

The network processor 832 is used for implementing the forwarding process of the message. The network processor 832 may take the form of a forwarding chip. Specifically, the processing of the uplink packet includes: processing a message input interface and searching a forwarding table; and (3) downlink message processing: forwarding table lookups, etc.

The physical interface card 833 is used to implement the interfacing function of the physical layer, from which the original traffic enters the interface board 830, and the processed message is sent out from the physical interface card 833. Physical interface card 833 includes at least one physical interface, also referred to as a physical port. The physical interface card 833, also called a daughter card, may be installed on the interface board 830, and is responsible for converting the optical signal into a message, checking the validity of the message, and forwarding the message to the network processor 832 for processing. In some embodiments, the central processor 831 of the interface board 830 may also perform the functions of the network processor 832, such as implementing software forwarding based on a general purpose CPU, so that the network processor 832 is not required in the physical interface card 833.

Optionally, the network device 800 includes a plurality of interface boards, for example, the network device 800 further includes an interface board 840, and the interface board 840 includes: central processor 841, network processor 842, forwarding table entry memory 844, and physical interface card 843.

Optionally, the network device 800 further comprises a switch board 820. The switch board 820 may also be called a Switch Fabric Unit (SFU). In the case of a network device having a plurality of interface boards 830, the switch board 820 is used to complete data exchange between the interface boards. For example, interface board 830 and interface board 840 may communicate through switch board 820.

The master control board 810 is coupled to an interface board 830. For example. The main control board 810, the interface board 830, the interface board 840, and the switch board 820 are connected to the system backplane through the system bus to realize intercommunication. In a possible implementation manner, an inter-process communication protocol (IPC) channel is established between the main control board 810 and the interface board 830, and the main control board 810 and the interface board 830 communicate with each other through the IPC channel.

Logically, the network device 800 includes a control plane including the main control board 810 and the central processor 831, and a forwarding plane including various components performing forwarding, such as a forwarding table entry memory 834, a physical interface card 833, and a network processor 832. The control plane performs functions of a router, generating a forwarding table, processing signaling and protocol messages, configuring and maintaining the state of the device, and the like, and issues the generated forwarding table to the forwarding plane, and in the forwarding plane, the network processor 832 looks up a table of the messages received by the physical interface card 833 and forwards the messages based on the forwarding table issued by the control plane. The forwarding table issued by the control plane may be stored in a forwarding table entry memory 834. In some embodiments, the control plane and the forwarding plane may be completely separate and not on the same device.

It should be understood that the addressing unit 602 in the test apparatus 600 may correspond to the physical interface card 833 or the physical interface card 843 in the network device 800. The determination unit 601 or the like in the test apparatus 600 may correspond to the central processor 811 or the central processor 831 in the network device 800.

It should be understood that operations on the interface board 840 in the embodiment of the present application are the same as those of the interface board 830, and therefore, for brevity, detailed descriptions are omitted. It should be understood that the network device 800 of this embodiment may correspond to the controller in each of the above method embodiments, and the main control board 810, the interface board 830 and/or the interface board 840 in the network device 800 may implement the functions and/or the various steps of the controller in each of the above method embodiments, which are not described herein again for brevity.

It should be understood that the main control board may have one or more blocks, and when there are more blocks, the main control board may include an active main control board and a standby main control board. The interface board may have one or more blocks, and the stronger the data processing capability of the network device, the more interface boards are provided. There may also be one or more physical interface cards on an interface board. The exchange network board may not have one or more blocks, and when there are more blocks, the load sharing redundancy backup can be realized together. Under the centralized forwarding architecture, the network device does not need a switching network board, and the interface board undertakes the processing function of the service data of the whole system. Under the distributed forwarding architecture, the network device can have at least one switching network board, and the data exchange among a plurality of interface boards is realized through the switching network board, so that the high-capacity data exchange and processing capacity is provided. Therefore, the data access and processing capabilities of network devices in a distributed architecture are greater than those of devices in a centralized architecture. Optionally, the form of the network device may also be only one board card, that is, there is no switching network board, and the functions of the interface board and the main control board are integrated on the one board card, at this time, the central processing unit on the interface board and the central processing unit on the main control board may be combined into one central processing unit on the one board card to perform the function after the two are superimposed, and the data switching and processing capability of the device in this form is low (for example, network devices such as a low-end switch or a router, etc.). Which architecture is specifically adopted depends on the specific networking deployment scenario.

In some possible embodiments, the controller or the network device may be implemented as a virtualized device. For example, the virtualized device may be a Virtual Machine (VM) running a program for sending messages, and the VM is deployed on a hardware device (e.g., a physical server). A virtual machine refers to a complete computer system with complete hardware system functionality, which is emulated by software, running in a completely isolated environment. The virtual machine may be configured as a controller or a network device. For example, a controller or Network device may be implemented based on a general purpose physical server in conjunction with Network Function Virtualization (NFV) technology. The controller or network device is a virtual host, a virtual router, or a virtual switch. Through reading the present application, a person skilled in the art can combine the NFV technology to virtually create a controller with the above functions on a general physical server, and details are not described here.

It should be understood that the network devices in the above various product forms respectively have any function of the controller in the above method embodiments, and are not described herein again.

The embodiment of the application also provides a chip, which comprises a processor and an interface circuit, wherein the interface circuit is used for receiving the instruction and transmitting the instruction to the processor; a processor, which may be a specific implementation form of the testing apparatus 600 shown in fig. 6, for example, may be configured to execute the message transmission method described above. Wherein the processor is coupled to a memory for storing a program or instructions which, when executed by the processor, cause the system-on-chip to carry out the method of any of the method embodiments described above.

Optionally, the system on a chip may have one or more processors. The processor may be implemented by hardware or by software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, or the like. When implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory.

Optionally, the memory in the system-on-chip may also be one or more. The memory may be integrated with the processor or may be separate from the processor, which is not limited in this application. For example, the memory may be a non-transitory processor, such as a read only memory ROM, which may be integrated on the same chip as the processor, or may be separately disposed on different chips, and the type of the memory and the arrangement of the memory and the processor are not particularly limited in this application.

The chip system may be a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a system on chip (SoC), a Central Processor Unit (CPU), a Network Processor (NP), a Digital Signal Processor (DSP), a Microcontroller (MCU), a Programmable Logic Device (PLD) or other integrated chips.

The present application provides a computer-readable storage medium, which includes instructions or a computer program, when the computer-readable storage medium runs on a computer, the computer is caused to execute the dynamic random access memory testing method provided by the above embodiments.

Embodiments of the present application further provide a computer program product containing instructions or a computer program, which when run on a computer, causes the computer to execute the dynamic random access memory testing method provided in the above embodiments.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is only a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each service unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a hardware form, and can also be realized in a software service unit form.

The integrated unit, if implemented in the form of a software business unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Those skilled in the art will recognize that, in one or more of the examples described above, the services described in this disclosure may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the services may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The above embodiments are intended to explain the objects, aspects and advantages of the present invention in further detail, and it should be understood that the above embodiments are merely illustrative of the present invention.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for testing a dynamic random access memory, the method comprising:

the controller acquires a step skipping mode, wherein the step skipping mode is used for indicating an addressing mode;

aiming at any column in the DRAM, the controller carries out addressing operation on the storage unit in the column according to the skipping mode to obtain an addressing result;

and determining a test result according to the addressing result.

2. The method of claim 1, wherein determining a test result based on the addressing result comprises:

when the addressing result comprises that the memory unit cannot be addressed, the controller determines that the DRAM has address timing margin faults.

3. The method according to claim 1 or 2, wherein said determining a test result from said addressing result comprises:

when the addressing result comprises that the storage unit can be addressed, the controller determines a test result according to first data and second data, wherein the first data are data read from the storage unit when the storage unit is addressed, and the second data are data written into the storage unit in advance before the addressing operation.

4. The method of claim 3, wherein prior to the controller determining the test result from the first data and the second data, the method further comprises:

the controller reads first data from the memory cell.

5. The method of claim 4, wherein for any column in the DRAM, the controller performs an addressing operation on the memory cells in the column in the skipping manner to obtain an addressing result, and the method comprises:

the controller acquires a hit coefficient corresponding to a Dynamic Random Access Memory (DRAM), wherein the hit coefficient represents the average opening times of storage units in the DRAM;

and aiming at any column in the DRAM, the controller carries out addressing operation on the storage unit in the column according to the skipping mode until the starting times of the storage unit are matched with the hit coefficient, and an addressing result is obtained.

6. The method of any of claims 3-5, wherein the controller determines the test result based on the first data and the second data, comprising:

when the first data and the second data are not the same, the controller determines that a leakage fault exists in a memory cell in the DRAM.

7. The method of claim 6, wherein the leakage fault comprises a fault in which a frequently switched row causes leakage of memory cells of an adjacent row.

8. The method according to any one of claims 1 to 7, wherein the skipping manner comprises one or more of ascending addressing, descending addressing, skipping addressing, or Pseudo Random Binary Sequence (PRBS) addressing.

9. The method of claim 8, wherein when the skipping mode is the PRBS addressing, the controller performs an addressing operation on the memory cell in the column according to the skipping mode to obtain an addressing result, comprising:

the controller obtains an addressing sequence corresponding to the PRBS addressing according to a random seed;

10. The method of claim 3, wherein prior to the controller addressing the memory cells in the column in the skip mode, the method further comprises:

the controller writes the second data to memory cells in the DRAM.

11. The method of claim 3, further comprising:

the controller writes third data to memory cells in the DRAM when the first data is the same as the second data;

aiming at any row of storage units in the DRAM, the controller carries out addressing operation on the storage units in the row according to the step skipping mode until the opening times of the storage units are matched with the hit coefficient;

the controller acquires fourth data in a memory cell in the DRAM;

and determining a test result according to the third data and the fourth data.

12. The method of any of claims 1-11, wherein the addressing operation comprises a read operation on the memory cell.

13. The method of any of claims 1-12, wherein the controller tests the DRAM through a built-in self test BIST interface.

14. The method of claim 5, wherein different columns in the DRAM correspond to different hit coefficients.

15. The method of claim 5, wherein the matching of the number of times the memory cell is turned on to the hit coefficient comprises the number of times the memory cell is turned on being equal to the hit coefficient or a difference between the number of times the memory cell is turned on and the hit coefficient being less than a predetermined threshold.

16. A test system is characterized in that the system comprises a controller and a Dynamic Random Access Memory (DRAM), wherein the controller is connected with the DRAM through a peripheral circuit;

the controller acquires a step skipping mode, and the step skipping mode is used for indicating an addressing mode;

the controller is further configured to perform, for any one column in the dynamic random access memory DRAM, an addressing operation on the memory cell in the column according to the skipping mode to obtain an addressing result;

the controller is further configured to determine a test result according to the addressing result.

17. An apparatus for testing a dynamic random access memory, the apparatus comprising:

the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a step skipping mode, and the step skipping mode is used for indicating an addressing mode;

the addressing unit is used for addressing the storage unit in any column in the DRAM according to the skipping mode to obtain an addressing result;

and the determining unit is used for determining a test result according to the addressing result.

18. A communication device, the device comprising: a processor and a memory;

the memory for storing instructions or computer programs;

the processor configured to execute the instructions or computer program in the memory to cause the communication device to perform the method of any one of claims 1-15.

19. A computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any of claims 1-15 above.