CN115310392A - Chip design method based on transmission of comprehensive information flow - Google Patents

Abstract

The method not only obtains a logic sub netlist of each device group and other logic sub netlists of other circuit structures, but also obtains a physical scene netlist of each device group and transmits the netlist to a packing stage after identifying the device group based on an RTL (real time language) level description file in a logic synthesis stage; the packing result of each device group can be directly obtained according to the box structure expressed by the physical scene netlist of the device group and the connection relation between the device structures in the packing stage, the packing algorithm does not need to be searched for and packed, and the physical scene netlist is generated based on the functional information and the architecture information of the device group, so that the optimal packing result meeting the requirements of the functional information and the architecture information of the device group can be directly obtained in the packing stage, the packing efficiency and the packing quality are improved, and the efficiency and the quality of chip design are improved.

Description

Chip design method based on transmission of comprehensive information flow

Technical Field

The invention relates to the technical field of chip design, in particular to a chip design method based on comprehensive information flow transmission.

Background

Semiconductor technology and processes have been developed over decades, from the first discrete semiconductor device transistors to today's very large scale integrated circuits. With the development of semiconductor technology and technology, the Design technology of integrated circuits has also undergone the development from the original computer aided Design tools to the complete integrated circuit Design Automation process (Electronic Design Automation) of today, especially the invention and application of the integrated technology in the nineties of the last century, so that the Automation of the whole Design process from the description of Design concept to the final physical realization of the Design of integrated circuits becomes possible.

At present, the design flows of a commonly used FPGA chip and an ASIC chip are similar, taking a process of developing the FPGA chip by using EDA (Electronic design automation) development software and a programming tool as an example, please refer to the design flow chart shown in fig. 1, where the development flow of the EDA development software mainly includes a user design input stage, a logic synthesis stage, a binning stage, a layout stage, a wiring stage, and a design completion stage, and the design completion stage mainly includes operations such as timing analysis and code stream generation. The method comprises a logic synthesis stage, a first step of reading in the RTL level description file, a second step of converting the RTL level description file into a universal circuit to establish a universal netlist (irrelevant to a specific process), a third step of optimizing a circuit structure of the universal circuit according to a design target, a fourth step of mapping the optimized circuit structure to a target process library corresponding to an FPGA chip, and selecting a proper prototype device in the target process library to realize the optimized circuit structure, so that the logic netlist suitable for the FPGA chip is obtained.

With the rapid development of semiconductor technology, the chip design capacity is correspondingly and continuously enlarged, how to quickly and accurately convert the user design into a digital system and successfully install the digital system on a chip, the processing efficiency and the optimization level of the design of the ultra-large capacity FPGA/ASIC are improved, and a great challenge is provided for the design software matched with the chip. The method for improving the processing capacity and efficiency of the design of the ultra-large capacity chip to a certain extent can be realized by the method that a related or specific description sentence creating device group is identified and added into a corresponding target process library of the FPGA chip after an RTL-level description file is read in by a patent with the application number of 202110545652.3 and the patent name of 'a chip design method based on intelligent analysis'.

However, in both the conventional chip design method and the cited chip design method for modifying the target process library corresponding to the FPGA chip, as the chip scale increases, the number, types and connection relationships of the prototype devices included in the logic netlist generated in the logic synthesis stage are huge and complex, after the logic netlist is transferred to the boxing stage, global search and boxing are required to be performed on the prototype devices with connection relationships by using a boxing algorithm in the boxing stage, the boxing difficulty is often large, and finally obtained boxing results are not necessarily ideal, so the processing efficiency of the chip design flow is still not ideal.

Disclosure of Invention

The inventor provides a chip design method based on the transmission of comprehensive information flow aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a chip design method based on transmission of comprehensive information flow comprises the following steps:

obtaining an RTL level description file, analyzing description sentences in the RTL level description file, identifying the description sentences to obtain a plurality of device groups, and adding the device groups into a mapping library comprising a plurality of prototype devices;

performing logic comprehensive processing on the RTL level description file based on a mapping library to obtain a logic sub netlist and a physical scene netlist of each of a plurality of device groups and other logic sub netlists of other circuit structures except the device groups; each logic sub netlist is respectively expressed by using a prototype device with a connection relation as a basic unit; the physical scene netlist of each device group is expressed by taking a box structure with a connection relation as a basic unit, and the prototype devices in the logic sub netlist of each device group belong to the corresponding box structures based on the functional information and the architecture information of the device group determined in the logic synthesis stage;

in the packing stage, directly obtaining the packing result of each device group according to the physical scene netlist of each device group, and searching and packing the prototype devices contained in other logic sublists according to other logic sublists by using a packing algorithm to obtain the packing result;

and carrying out layout and wiring based on the global packing result, and finishing the chip design of the chip to be designed.

The method comprises the following steps that when a box structure to which each prototype device in the device group belongs is determined based on function information and architecture information of the device group in a logic comprehensive processing stage, the prototype devices used for realizing preset logic functions and/or included in a circuit structure with a preset circuit architecture in the device group are belonged to the box structure according to a corresponding preset optimal boxing mode.

The further technical scheme is that the method also comprises the following steps:

in the logic synthesis processing stage, the layout scene netlist of each device group is further obtained through the logic synthesis processing of the RTL-level description file, each layout scene netlist is expressed by taking a box structure with layout constraints as a basic unit, and the box structure in the physical scene netlist of each device group determines the layout constraints based on the functional information and the architecture information of the device group determined in the logic synthesis stage;

then, when the layout is performed based on the global packing result, the layout is completed on the global packing result based on the layout constraint of the box structure indicated by the layout scene netlist of each device group.

The method further comprises the step of determining layout constraints among a plurality of box structures with functional relevance and/or architecture relevance to lay out the box structures according to preset optimal relative positions corresponding to the functional relevance and/or the architecture relevance when the layout constraints of the box structures in the device group are determined based on the functional information and the architecture information of the device group in the logic comprehensive processing stage.

The method further comprises the step of determining layout constraints among all box structures in the same device group to be compact layout of all box structures in the same device group in the same local area when determining layout constraints of the box structures in the device group based on the functional information and the architecture information of the device group in the logic comprehensive processing stage.

The layout constraint of the box structures in each device group comprises the relative layout positions of the box structures in the virtual layout areas with the corresponding sizes of the device groups, each device group corresponds to different virtual layout areas, and the size of the virtual layout area corresponding to each device group corresponds to the total number of the box structures contained and the preset optimal relative positions among the box structures with functional relevance and/or architecture relevance.

The further technical scheme is that the relative layout position of each box structure in the device group in the virtual layout area corresponding to the device group is determined by aiming at minimizing the layout distance between the box structures with the direct drive relationship.

The method comprises the following steps that when layout is carried out based on a global packing result, a virtual layout area with the size corresponding to each device group and each box structure obtained by packing other logic sub netlists are used as basic units to carry out global layout, each device group directly obtains the relative layout position of each box structure in the corresponding virtual layout area according to the layout constraint of the box structure indicated by the layout scene netlist of the device group to realize compact layout, and in the obtained layout result, layout is directly carried out among a plurality of box structures with functional relevance and/or architecture relevance in each device group according to the preset optimal relative position.

The further technical scheme is that the layout constraint of the box structures in each device group comprises the layout weight of each box structure, all the box structures contained in the same device group have the same layout weight, and the box structures contained in different device groups have different layout weights.

The method comprises the following steps of carrying out overall layout by taking each box structure in an obtained packing result as a basic unit when the overall packing result is laid out, carrying out compact layout on the box structures with the same layout weight in the same local area according to the layout constraint of the box structure indicated by the layout scene netlist of each device group, and directly laying out a plurality of box structures with functional relevance and/or architecture relevance in each device group according to a preset optimal relative position.

The beneficial technical effects of the invention are as follows:

according to the method, after the device groups are identified in the logic synthesis stage, not only are logic sub netlists generated for the device groups, but also a netlist scene is constructed to generate a physical scene netlist and the netlist is transmitted to the subsequent boxing stage through information flow, so that the boxing result of the device groups can be directly obtained by using the physical scene netlist of the device groups in the boxing stage, the device groups do not need to participate in searching and boxing of a boxing algorithm, and the boxing efficiency is improved.

And because the physical scene netlist is generated based on the functional information and the architecture information of the device group, the optimal packing result meeting the requirements of the functional information and the architecture information of the device group can be directly obtained in the packing stage, the problem that the ideal packing result cannot be obtained due to the fact that only the connection relation of the prototype devices recorded by the logic netlist can be obtained in the packing stage but the functional information and the architecture information of the device group cannot be obtained in the conventional design method is solved, and therefore the quality of packing is improved.

Furthermore, a layout scene is also constructed in the logic synthesis stage to generate a layout scene netlist and the layout scene netlist is transmitted to the subsequent packing stage and the layout stage through information flow, so that the layout result can be quickly obtained by using layout constraints recorded by the layout scene netlist of the device group in the layout stage, and because the layout scene netlist is generated based on the functional information and the architecture information of the device group, the optimal layout result meeting the requirements of the functional information and the architecture information of the device group can be directly obtained in the layout stage, and the problem that in the conventional design method, because the layout stage can only obtain the connection relation of the prototype device recorded by the logic netlist and cannot obtain the functional information and the architecture information of the device group, the ideal layout result cannot be obtained is solved, so that the layout efficiency and the layout quality are improved.

When a network table scene is created for each device group, the relative independence between the device groups can be utilized, and the parallel processing computing resources can be used to the maximum extent, so that the design efficiency of the ultra-large-capacity FPGA is further improved.

Drawings

Fig. 1 is a schematic diagram of a design flow of a conventional chip design method.

Fig. 2 is a schematic design flow diagram of a chip design method implemented based on delivery of integrated information streams according to an embodiment of the present application.

FIG. 3 is a schematic diagram of a logic sub-netlist of a device group generated during a logic synthesis phase in one example.

FIG. 4 is a schematic diagram of a netlist generated during a logic synthesis phase by the device group in the example shown in FIG. 3.

FIG. 5 is a schematic diagram of a placement scenario netlist generated during a logic synthesis phase for the group of devices in the example shown in FIG. 3.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a chip design method based on the realization of transmitting comprehensive information flow, please refer to the flow chart shown in fig. 2, and the method comprises the following steps in each link of the chip design process:

1. user design input phase

The method comprises the steps of obtaining an RTL level description file of a chip to be designed, wherein the RTL level description file is obtained by writing any one of Verilog, system Verilog and VHDL. The chip to be designed is an FPGA chip or an ASIC chip.

2. Logic synthesis phase

1. Parsing RTL level description files

And analyzing description sentences in the RTL-level description file, identifying and obtaining a plurality of device groups, and adding the device groups into a mapping library comprising a plurality of prototype devices. Each device group is a circuit structure represented by at least two descriptive sentences having a predetermined association and/or at least one descriptive sentence conforming to a predetermined sentence characteristic.

One device group determined in the present application includes a circuit structure in the form of a general circuit model and/or a local netlist, and the circuit structure in the form of the general circuit model represents a macro cell having a preset architecture. Optionally, the macro unit with the preset architecture includes at least one of an N-bit arithmetic unit, an N-bit multiplexer, an N-bit comparator, a memory unit, a digital signal processing unit, a control circuit unit, and a microprocessor unit, where it should be noted that the above-mentioned N bits are only general terms, and do not indicate that the signal bit widths of the respective devices need to be equal. The arithmetic operation unit comprises at least one of an adder, a subtractor, a multiplier, a divider and an accumulator, the storage unit comprises at least one of a BRAM, a ROM and a RAM, the digital signal processing unit comprises at least one of a digital filter and a DSP, the control circuit unit comprises a FSM (Finite State Machine), and the microprocessor unit comprises at least one of a CPU, a GPU and an MPU. These macro cells with preset architectures are some common high-level modules, which can be marked as private cells, and the architecture of each macro cell is configured, set and formed in advance, so that the macro cells can directly exist in the form of a universal circuit model. In addition to the circuit structures forming the macro cells, the device assembly also includes random combinational logic that does not form macro cells of any predetermined architecture and therefore exists in the form of a netlist, and thus the circuit structures existing in the form of a partial netlist represent the circuit structures except for all macro cells having the predetermined architecture.

Therefore, the device group in the present application may include both macro cells and random combinational logic, and is a higher-level and higher-circuit-complexity module than a conventional macro cell. The method for identifying the device group is not described in detail, and can be obtained by identification based on the identification method provided in the chip design method based on intelligent analysis previously applied by the applicant.

After all the device groups are identified, all the device groups are added into a mapping library containing a plurality of prototype devices. The mapping library is a library that needs to be used when the existing chip to be designed is subjected to process mapping, and the mapping library internally comprises a plurality of prototype devices, such as LUTs and registers. The device group obtained by the identification is added on the basis of a conventional mapping library. The device group is a relatively independent module with certain functions, which cannot be determined and customized in advance before the design process starts and can be obtained and added to the mapping library only by analyzing the RTL level description file identification in the step.

2. Building a generic netlist

Module binding and refinement are carried out, the RTL level description file is converted into a general circuit irrelevant to a specific process to obtain a general netlist, the specific operation of the step is similar to that of a conventional method, but because the device groups in the RTL level description file are identified, the general netlist obtained by the step comprises the general sublists of the device groups and the general sublists of other circuit structures except the device groups.

3. Logic optimization

And performing logic optimization on the universal circuit represented by the universal netlist according to the design target optimization to obtain the optimized universal netlist. Because the universal netlist comprises the universal sub-netlists of the device groups and the universal sub-netlists of other circuit structures, the universal sub-netlists of the device groups and the universal sub-netlists of other circuit structures are optimized when logic optimization is performed in the step, and the correspondingly obtained optimized universal netlist also comprises the optimized universal sub-netlists of the device groups and the optimized universal sub-netlists of other circuit structures.

4. Performing device mapping and establishing a plurality of netlist scenes based on a mapping library, wherein the method comprises the following steps of establishing the netlist scenes and correspondingly obtaining the netlists:

(1) And obtaining a logic Netlist scene (Netlist View) of each of the plurality of device groups and other logic sublists of other circuit structures except the device groups, wherein each logic sublist is expressed by taking the original device with the connection relation as a basic unit.

And mapping the optimized general netlist to a mapping library of a chip to be designed to obtain a logic sub-netlist. Specifically, the method comprises the following steps: and mapping the optimized general sub netlist of each device group to a corresponding device group in a mapping library to obtain a logic sub netlist of each device group, and binding a plurality of prototype devices in the mapping library contained in the device group in the logic sub netlist of each device group. And binding the optimized general sub netlist of other circuit structures to the original devices in the mapping library to obtain other logic sub netlists of other circuit structures.

In the mapping process, for the circuit structures existing in the device group in the general circuit model, since the macro units formed by the circuit structures existing in the general circuit model are common structures, the physical implementation of the optimal mapping can be directly constructed according to the resources on the chip. Such as a one-out-of-N multiplexer, an N-bit adder, etc. Therefore, the optimal implementation architecture can be directly determined during mapping, and the logic sub-netlist with the optimal mapping effect is obtained.

Therefore, regardless of the logic sub netlist of the device group or other logic sub netlists of other circuit structures, each logic sub netlist obtained under the logic netlist scene is expressed by taking an original device as a basic unit, namely, each logic sub netlist is bound to the original device in the mapping library, and each logic sub netlist reflects the connection relation between the original devices contained in the corresponding circuit structure.

(2) And (2) boxing scenes (Packing View) to obtain a physical scene netlist of a plurality of device groups, wherein the physical scene netlist of each device group is expressed by taking a box structure (Slice) with a connection relation as a basic unit, all the prototype devices bound by the device groups are attributed to the corresponding box structures, and each prototype device is attributed to one box structure. When the prototype devices included in each of the two box structures have a connection relationship, the two box structures also have a connection relationship.

The prototype devices in the logic sub netlist of each device group are attributed to the corresponding box structures based on the function information and the architecture information of the device groups determined in the logic synthesis stage, that is, how all the prototype devices should be attributed to different box structures is determined by the function information and the architecture information of the device groups. And the functional information and the architecture information of the device groups are known in the logic synthesis stage, so that the boxing scene can be naturally constructed according to the information acquired in the logic synthesis stage to obtain the physical scene netlist of each device group.

Wherein the function information of the device group indicates a logic function realized by the device group as a whole and/or a logic function realized by a circuit configuration of a part of the device group. In one embodiment, for several typical and commonly used circuit structures for implementing a predetermined logic function, a preset optimal packing manner of the circuit structure with the predetermined logic function can be directly constructed according to resources on a chip: such as directly attributing the circuit structures for implementing the predetermined logic function to the same or multiple box structures, or other predetermined optimal packing manners. Predetermined logic functions are common such as a multiplexing function and an arithmetic function.

The architecture information of the device group indicates the circuit architecture of the circuit structure inside the device group, including the circuit architecture indicating each common circuit model included in the device group, the circuit architecture other than the common circuit model, the circuit architecture between each part of the circuit architecture, including the connection triggering relationship, and the like. In one embodiment, for several typical and commonly used predetermined circuit architectures, a preset optimal packing manner of a circuit structure of the predetermined circuit architecture may be directly constructed according to resources on a chip: such as directly attributing the circuit structure with the predetermined circuit architecture to the same or multiple box structures, and presetting an optimal boxing mode. Predetermined circuit architectures are common, such as circuit architectures built from multiple one-out-of-N selectors to form a multiplexing circuit.

In one embodiment, when determining the box structure to which each prototype device in the device group belongs based on the function information and the architecture information of the device group, the prototype devices included in the circuit structure for implementing the predetermined logic function and/or having the predetermined circuit architecture in the device group are assigned to the box structure according to the corresponding preset optimal boxing manner, and both the preset optimal boxing manner corresponding to the predetermined logic function and the preset optimal boxing manner corresponding to the predetermined circuit architecture can be preset. The device group may include multiple sets of circuit structures for implementing different predetermined logic functions and/or having different predetermined circuit architectures, and the device groups are respectively assigned according to corresponding preset optimal boxing modes. The device group may include other circuit structures besides the circuit structures for implementing the predetermined logic function and/or having the predetermined circuit architecture, and at this time, the remaining circuit structures may be categorized into other box structures according to the circuit scale, so as to finally obtain the physical scene netlist of the device group.

For example, in one example, the function information of a device group indicates that the device group implements a multi-way selection function of 256 to 1, and the architecture information of the device group indicates that the device group internally includes 17 selectors of 16 to 1, each selector of 16 to 1 having an optimal binning mode: the prototype devices bound by the same 16-out-of-1 selector are assigned to the same box structure. Then, based on the architecture information of the device group, the prototype devices bound to the circuit structure of each 16-to-1 selector are respectively attributed to the same box structure, so that the device group is directly attributed to 17 box structures respectively, and the connection relationship among the 17 box structures can be naturally determined, except for the 17 16-to-1 selectors, no other circuit structure which is not attributed yet exists in the device group, and thus, a physical scene netlist of the device group is finally obtained.

(3) And (4) obtaining respective layout scene netlists of a plurality of device groups by using a layout scene (layout View), wherein each layout scene netlist is expressed by using a box structure with layout constraints as a basic unit.

All box structures in the physical scene netlist of each device group determine layout constraints based on the functional information and the architecture information of the device group determined in the logic synthesis stage, that is, the layout of all box structures in each device group according to which layout constraints is determined by the functional information and the architecture information of the device group. And the functional information and the architecture information of the device groups are known in the logic synthesis stage, so that the layout scene can be naturally constructed according to the information acquired in the logic synthesis stage to obtain the layout scene netlist of each device group. In the present application, the layout constraint described in the layout scene netlist of the device group is generated based on the functional information and the architecture information of the device group, and is different from the layout constraint condition input by the user.

The layout constraint between box structures recorded by the device group layout scene netlist comprises two parts:

the first part is to constrain the relative positions of multiple box structures within the same device group that have functional and/or architectural relevance.

As described above, the logic synthesis stage may determine functional information and circuit architectures of the device groups, and functional associations may exist between circuit structures in the device groups for implementing different logic functions, and/or architectural associations may exist between circuit structures having different circuit architectures. Then, after obtaining the physical scene netlist of the device group and determining the box structures to which the prototype devices of the circuit structures in each part of the device group belong, it may naturally also be determined that functional association and/or architectural association also exists between the box structures to which the circuit structures having functional association and/or architectural association belong. That is, in the present application, a plurality of box structures having functional relevance and/or architectural relevance means that circuit structures formed of prototype devices included in the plurality of box structures have functional relevance and/or architectural relevance.

In one embodiment, for a combination of several typical and commonly used box structures with functional relevance and/or architectural relevance, a preset optimal relative position between the box structures may be directly constructed, and then a layout constraint between a plurality of box structures with functional relevance and/or architectural relevance is directly determined to lay out the plurality of box structures according to the preset optimal relative positions corresponding to the functional relevance and/or architectural relevance.

For example, in one example, if a circuit structure composed of prototype devices included in 4 box structures is used to implement the carry chain function together, the 4 box structures have functional relevance. Layout constraints directly added to the 4 box structures are preset optimal relative positions corresponding to the carry chain functions, and the preset optimal relative positions indicate that the 4 box structures are vertically arranged from bottom to top according to the carry sequence.

In the second part, regardless of whether the device group contains box structures with functional relevance and/or architecture relevance, the layout constraint between the box structures described in the layout scene netlist of the device group also needs to constrain the layout position relationship between different device groups.

Specifically, the layout constraints among all box structures in the same device group are determined as compact layout of all box structures in the same device group in the same local area, that is, it is desirable to finally achieve the goal that box structures in the same device group are laid out together as much as possible and different device groups are laid out in different local areas.

In an embodiment of the second part, the layout tool is adapted to use a virtual rectangular layout, that is, each device group is laid out in a virtual layout area.

In this embodiment, the layout constraints of the bin structures in each device group include the relative layout positions of the respective bin structures within the virtual layout area of the corresponding size of the device group, each device group corresponding to a different virtual layout area. In this embodiment, it is first necessary to determine the size of the virtual layout area corresponding to each device group, specifically, the size of the virtual layout area of the device group is determined according to the total number of box structures and the preset optimal relative position between the plurality of box structures having functional relevance and/or architecture relevance. Generally, the size of the virtual layout area may be determined according to the number of box structures included in the device group, but since the first part of the present application further needs to add layout constraints to ensure that the box structures with functional relevance and/or architectural relevance are laid out according to the preset optimal relative position, a plurality of box structures such as those used for cooperatively implementing a carry chain function in the foregoing example may have requirements on the height of the virtual layout area under the constraint of vertical layout, and in other cases, there may also be other requirements on the size of the virtual layout area when the box structures are laid out according to the preset optimal relative position, the size of the virtual layout area needs to satisfy the size requirement of the virtual layout area generated by the layout constraints of the first part in addition to the requirement on the number of box structures.

After determining the size of the virtual layout area required by a device group, determining the relative layout position of each box structure in the virtual layout area of the corresponding size of the device group. For a plurality of box structures with functional relevance and/or architecture relevance, the relative layout positions of the box structures in the virtual layout area also satisfy the preset optimal relative positions to be satisfied among the box structures.

When determining the relative layout position of each box structure in the virtual layout area, determining the relative layout position of each box structure in the virtual layout area according to the connection relationship between the box structures. If a plurality of box structures with functional relevance and/or architecture relevance exist, on the basis of meeting layout constraints of preset optimal relative positions among the plurality of box structures, determining the relative layout position of each box structure in the virtual layout area according to the connection relation among the box structures. In one embodiment, the relative layout position of each box structure in the device group within the virtual layout region to which the device group corresponds is determined with the objective of minimizing the layout distance between box structures for which a direct drive relationship exists.

That is, in combination with the first part and the second part, in a scenario where the layout tool uses a virtual rectangle layout manner, the layout constraints of the box structures described in the layout scenario netlist of the device group include the relative layout positions of the box structures in the virtual layout region of the corresponding size of the device group, and the relative layout positions of the box structures having functional relevance and/or architecture relevance in the virtual layout region are also the preset optimal relative positions corresponding to the functional relevance and/or architecture relevance.

In another embodiment of the second section, the layout tool is adapted to scenarios where the layout tool does not facilitate the use of a virtual rectangular layout style. In this embodiment, the layout constraints of the box structures in each device group include the layout weights of the box structures, all box structures included in the same device group have the same layout weight, and box structures included in different device groups have different layout weights.

That is, in combination with the first part and the second part, in a scenario where the layout tool is inconvenient to use the virtual rectangle layout manner, the layout constraints of the box structures recorded in the layout scenario netlist of the device group include the layout weights of the respective box structures, and the preset optimal relative positions of the plurality of box structures where the functional association and/or the architecture association exist.

According to the method, the logic sub netlist, the physical scene netlist and the layout scene netlist can be obtained for each device group respectively, relative independence among different device groups is utilized, and in one embodiment, parallel resources are utilized to build the netlist scene for each device group respectively and obtain three types of netlists.

3. Boxing stage

As noted in the background section, in conventional design methodologies, the logic synthesis stage generates only a global logic netlist (i.e., a logic sub-netlist including device groups and other circuit structures) that is passed to the binning stage. In the packing stage, the information that can be obtained based on the global logic netlist is the connection relations of all prototype devices and prototype devices bound in the logic netlist, the connection relations of the prototype devices in the logic netlist need to be analyzed, global searching and packing are performed on all the prototype devices by using a packing algorithm such as Heuristic, the difficulty is high, and a good packing result cannot be obtained. In addition, although the device groups are identified in the logic synthesis stage in the conventional method, the logic netlist transmitted to the boxing stage only contains information such as which prototype devices are bound to each device group and how the prototype devices have the connection relationship, and the like, and the functional information and the architecture information of the device groups cannot be obtained in the boxing stage like the logic synthesis stage, so that when the device groups and the prototype devices in other circuit structures are searched and boxed, the optimal boxing result meeting the requirements of the functional information and the architecture information of the device groups is often difficult to obtain.

Different from the conventional method, in the logic synthesis stage, after the device group and the logic sublist of other circuit structures are obtained through a logic Netlist View (Netlist View), the physical scene Netlist of the device group is obtained through a Packing View (Packing View), and the layout scene Netlist of the device group is obtained through a layout View (Packing View), the netlists are all transmitted to the Packing stage, so that the information flow transmitted from the synthesis logic stage can be used in the Packing stage. In the boxing stage, not only can the connection relation of the prototype devices be determined through the logic sub netlist, but also box structures to which the prototype devices in the device group belong can be directly determined according to the physical scene netlist of the device group, and layout constraints among the box structures in the device group can be determined according to the layout scene netlist of the device group.

Based on the method provided by the application, in the packing stage, the packing result of each device group is directly obtained according to the physical scene netlist of each device group, and the original devices contained in the other logic sub netlists are searched and packed according to the other logic sub netlists by using the packing algorithm to obtain the packing result of other circuit structures except the other device groups. That is, based on the method provided by the application, in the boxing stage, the prototype devices in each device group do not participate in searching and boxing, and in the boxing stage, only the prototype devices in other circuit structures except the device group are searched and boxed by using a boxing algorithm, so that the search space in the boxing stage is greatly reduced, and the efficiency in the boxing stage is improved.

And the physical scene netlist of the device group is obtained based on the functional information and the architecture information of the device group, the boxing result directly obtained according to the physical scene netlist of each device group is directly the optimal boxing result meeting the requirements of the functional information and the architecture information of the device group, and the device group can be accurately and efficiently boxed.

4. Layout phase

The layout stage is arranged based on a global packing result, in the conventional design method, the packing stage transmits each box structure obtained by packing and the connection relation between the box structures to the layout stage, and then each box structure is arranged in a global state, and the number of the box structures is large, so that the layout stage consumes a long time in the conventional design method. For example, in the above example, circuit structures included in 4 box structures are used to jointly implement a carry chain function, according to a conventional design method, only the 4 box structures can be determined to have connection relationships in a layout stage, and the 4 box structures cannot be accurately vertically arranged from bottom to top according to a carry sequence according to actual needs only based on the connection relationships between the 4 box structures, so that a layout result obtained based on the conventional design method is often inaccurate, or multiple iterative adjustments are usually required to obtain an accurate layout result.

In the method provided by the application, the logic sub netlist, the physical scene netlist and the layout scene netlist generated in the logic synthesis stage are sequentially transmitted to the packing stage and the layout stage, so that the information flow transmitted to the synthesis logic stage can be used in the layout stage. And when the layout is carried out based on the global packing result, the layout is completed on the global packing result based on the layout constraint of the box structure indicated by the layout scene netlist of each device group.

Under the scene that a layout tool uses a virtual rectangle layout mode, global layout is carried out by taking a virtual layout area with the size corresponding to each device group and each box structure obtained by boxing other logic sub netlists as basic units, and each device group directly obtains the relative layout position of each box structure in the corresponding virtual layout area according to the layout constraint of the box structure indicated by the layout scene netlist of the device group, so that the box structures in the same device group are all laid out in the virtual layout area with the size corresponding to the device group, and the compact layout of the same device group is realized. Moreover, because the relative layout positions of the box structures with the functional relevance and/or the architecture relevance in the virtual layout area are also the preset optimal relative positions corresponding to the functional relevance and/or the architecture relevance, the obtained layout result directly lays out the box structures with the functional relevance and/or the architecture relevance in each device group according to the preset optimal relative positions.

Under the scene that the layout tool uses a virtual rectangle layout mode, the box structures in the device groups are not respectively subjected to global layout, but each device group is regarded as a whole, processed by a single target body and in the same level as the box structures obtained by packing other logic sub-netlists, so that the number of basic units processed in the layout stage is greatly reduced, and the efficiency of global layout is improved. And based on the layout constraint recorded by the layout scene netlist of the device group, the optimal layout result meeting the requirements of the functional information and the architecture information of the device group can be directly obtained, and the device group can be accurately and efficiently laid out.

Under the scene that a layout tool is inconvenient to use a virtual rectangle layout mode, carrying out global layout on box structures contained in a device group and box structures obtained by packing other logic sub-netlists at the same level, namely carrying out global layout by taking each box structure in an obtained packing result as a basic unit, carrying out compact layout on the box structures with the same layout weight in the same local area according to layout constraints of the box structures indicated by a layout scene netlist of each device group, and directly carrying out layout according to preset optimal relative positions among a plurality of box structures with functional relevance and/or architecture relevance in each device group.

Under the scene that a layout tool is inconvenient to use a virtual rectangle layout mode, although the single box structure is still used as a basic unit for global layout, the layout constraint provided by the layout scene netlist can be combined to quickly realize compact layout of the same device group, and the optimal layout result meeting the requirements of the functional information and the architecture information of the device group can be directly obtained based on the layout constraint recorded by the layout scene netlist of the device group, so that the device group can be accurately and efficiently laid out.

For example, in the example of carry chain function, since the layout scene netlist is generated in the logic synthesis stage and is transferred to the layout stage, based on the layout constraint provided by the layout scene netlist, the 4 box structures can be directly and vertically laid out from bottom to top according to the carry sequence without multiple iterative adjustments, and an accurate and optimal layout result is obtained.

5. Routing stage

After the layout of the chip to be designed is completed, the wiring is performed based on the global layout result, which is similar to the method at this stage in the conventional chip design flow, and is not described in detail in this application,

6. completing the design phase

The stage mainly includes operations such as time sequence analysis and code stream generation, and is similar to the method in the stage in the conventional chip design flow, which is not described in detail in the application, and finally completes the chip design of the chip to be designed.

Based on the method provided by the application, in one example, assuming that a device group is included to select one of 256 multipath selection circuits, in the logic synthesis stage:

the logic sub-Netlist of the device group obtained through a logic Netlist View (Netlist View) is shown in fig. 3, due to limited space, the connection relation of the whole logic sub-Netlist of the device group cannot be shown in detail, but the connection relation of the 256-out-of-multiple selection circuit is known to those skilled in the art, and a broken line box shows an enlarged View of the logic sub-Netlist of a part of the circuit structure.

A physical scene netlist of the device group obtained through Packing View (fig. 4) is shown, the physical scene netlist of the device group includes 17 box structures S0 to S16, and the box structures S0 to S15 are directly connected to the box structure S16 and have a direct driving relationship, a specific connection relationship is shown in fig. 4, a 256-out-of-one multiplexer circuit includes 17 16-out-of-1 multiplexers, and each box structure includes a circuit structure of a 16-out-of-1 multiplexer.

A layout scene netlist obtained from a layout scene (layout View) is shown in fig. 5, and layout constraints between the layout scene netlist of the device group and the added box structures relative to the physical scene netlist include: the relative layout positions of each box structure S0 to S16 within the virtual layout area, as shown in fig. 5, for example, the box structure S0 is located at the horizontal coordinate X0 and the vertical coordinate Y0 of the virtual layout area. The device group comprises 17 box structures in total, and no box structure with functional relevance and/or architecture relevance exists, so that the width of the virtual layout area is determined to be 4 columns and respectively recorded as X0-X3, and the height of the virtual layout area is determined to be 5 rows and respectively recorded as Y0-Y4 according to the number of the box structures. The relative layout positions of the respective box structures within the virtual layout area are determined according to the connection relationships between the box structures, so that the layout distances between the box structures having the direct drive relationship, that is, the total layout distance of the box structures S0 to S15 with respect to the box structure S16, are minimized, thereby obtaining the relative layout positions of the respective box structures within the virtual layout area as shown in fig. 5.

And transferring the obtained logic sub netlist, the physical scene netlist and the layout scene netlist of the device group to a packing stage, wherein in the packing stage, a box structure in the device group does not need to be searched and packed, and a packing result shown in the figure 4 is directly obtained according to a structure indicated by the physical scene netlist. And transferring the layout scene netlist to a layout stage, wherein in the layout stage, the box structures in the device group do not need to be respectively laid out, the device group is used as a whole to determine the layout position of the virtual layout region of the device group, and then the layout as shown in FIG. 5 can be directly realized according to the information provided by the layout scene netlist.

Claims (10)

1. A chip design method realized based on transmission of comprehensive information flow is characterized by comprising the following steps:

acquiring an RTL-level description file, analyzing description sentences in the RTL-level description file, identifying the description sentences to obtain a plurality of device groups, and adding the device groups into a mapping library comprising a plurality of prototype devices;

performing logic synthesis processing on the RTL level description file based on the mapping library to obtain a logic sub netlist and a physical scene netlist of each of the plurality of device groups and other logic sub netlists of other circuit structures except the device groups; each logic sub netlist is respectively expressed by using a prototype device with a connection relation as a basic unit; the physical scene netlist of each device group is expressed by taking a box structure with a connection relation as a basic unit, and the prototype devices in the logic sub netlist of each device group belong to the corresponding box structures based on the functional information and the architecture information of the device group determined in the logic synthesis stage;

in the packing stage, directly obtaining the packing result of each device group according to the physical scene netlist of each device group, and searching and packing the original devices contained in the other logic sublist according to the other logic sublists by using a packing algorithm to obtain the packing result;

and carrying out layout and wiring based on the global packing result, and finishing the chip design of the chip to be designed.

2. Method according to claim 1, characterized in that when determining the bin structure to which each prototype device in the device group belongs based on the functional information and the architecture information of the device group in the logic synthesis processing stage, the prototype devices included in the device group for implementing the predetermined logic function and/or the circuit structure having the predetermined circuit architecture are assigned to the bin structure in a corresponding preset optimal binning manner.

3. The method of claim 1, further comprising:

in a logic synthesis processing stage, obtaining a layout scene netlist of each device group through logic synthesis processing of the RTL-level description file, wherein each layout scene netlist is expressed by taking a box structure with layout constraints as a basic unit, and the box structure in the physical scene netlist of each device group determines the layout constraints based on the functional information and the architecture information of the device group determined in the logic synthesis stage;

then, when the layout is performed based on the global packing result, the layout is completed on the global packing result based on the layout constraint of the box structure indicated by the layout scene netlist of each device group.

4. The method according to claim 3, wherein when determining the layout constraint of the box structures in the device group based on the functional information and the architecture information of the device group in the logic synthesis processing stage, determining the layout constraint between the box structures with functional relevance and/or architecture relevance to layout the box structures according to the preset optimal relative positions corresponding to the functional relevance and/or architecture relevance.

5. The method of claim 4, wherein determining layout constraints for box structures in a group of devices during a logic synthesis processing phase based on functional information and architectural information of the group of devices further comprises determining layout constraints between all box structures in the same group of devices as a compact layout of all box structures in the same group of devices within the same local area.

6. The method of claim 5, wherein the layout constraints of the box structures in each device group include relative layout positions of the respective box structures within a virtual layout area of corresponding size of the device group, each device group corresponds to a different virtual layout area, and the size of the virtual layout area corresponding to each device group corresponds to a preset optimal relative position between the total number of box structures included and the plurality of box structures included that have functional and/or architectural relevance.

7. The method of claim 6, wherein the relative layout position of each box structure in the device group within the virtual layout region corresponding to the device group is determined with the objective of minimizing the layout distance between the box structures for which the direct drive relationship exists.

8. The method according to claim 6, wherein when layout is performed based on a global packing result, global layout is performed by using a virtual layout area with a size corresponding to each device group and each box structure obtained by packing other logic sub netlists as a basic unit, and each device group directly obtains a relative layout position of each box structure in the corresponding virtual layout area according to layout constraints of the box structures indicated by a layout scene netlist of the device group to implement compact layout, and in the obtained layout result, layout is directly performed according to a preset optimal relative position between a plurality of box structures with functional relevance and/or architecture relevance in each device group.

9. The method of claim 5, wherein the layout constraints of the box structures in each device group include layout weights of the box structures, all box structures included in the same device group have the same layout weight, and box structures included in different device groups have different layout weights.

10. The method according to claim 9, wherein when performing layout based on the global binning result, performing global layout with each bin structure in the obtained binning result as a basic unit, and performing compact layout on bin structures with the same layout weight in the same local area according to the layout constraint of the bin structure indicated by the layout scene netlist of each device group, and performing layout directly according to the preset optimal relative position between multiple bin structures in each device group where functional relevance and/or architectural relevance exists.

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