CN115310391A

CN115310391A - FPGA configuration control system, FPGA configuration method and FPGA chip

Info

Publication number: CN115310391A
Application number: CN202210962791.0A
Authority: CN
Inventors: 阙小茜; 邢亚楠; 陶琼; 康暄; 李显军; 田征; 李曦晨
Original assignee: Chengdu Hua Microelectronics Technology Co ltd
Current assignee: Chengdu Hua Microelectronics Technology Co ltd
Priority date: 2022-08-11
Filing date: 2022-08-11
Publication date: 2022-11-08

Abstract

The FPGA configuration control system, the FPGA configuration method and the FPGA chip, the system comprises: the FPGA configuration system comprises a general FPGA configuration interface module, a JTAG interface module, a configurable parameterized eFlash array, an eFlash control module connected with the JTAG interface module and the eFlash array, a data bus control module connected with the JTAG interface module and the general FPGA configuration interface module, a frame data selector connected with the data bus control module and the eFlash control module, and a configurable parameterized configuration SRAM controller connected with the frame data selector, wherein the configurable parameterized configuration SRAM controller is used for being connected with an FPGA programmable system of an FPGA chip. The configuration interface and the configuration control function of the SRAM type FPGA are met, the characteristic of nonvolatile data stream storage of the data of the eFlash type FPGA configuration control system is met, two configuration paths are relatively independent, and the FPGA which is compatible with different bit stream sizes and configuration speed requirements can be expanded through different configurations.

Description

FPGA configuration control system, FPGA configuration method and FPGA chip

Technical Field

The application relates to the technical field of integrated circuit chip design, in particular to an FPGA configuration control system, an FPGA configuration method and an FPGA chip.

Background

There are three mainstream types of FPGAs on the market today: the first is the traditional SRAM type FPGA, the market scale is the largest, and an external host or a nonvolatile memory is needed to configure the FPGA when the system is powered on; the second is an anti-fuse FPGA, which adopts an anti-fuse technology to realize an internal array switch, but can only be programmed once; the third is the latest Embedded Flash (eFlash) type FPGA, which integrates eFlash IP in an FPGA chip and realizes the self-loading configuration data of the chip through nonvolatile eFlash after being electrified.

No matter what type of FPGA is, the whole structure of the FPGA is composed of a configuration control system and a programmable system. The configuration control system mainly realizes two functions: the first is to complete the loading of the FPGA configuration data stream, and the second is the overall control function of the FPGA, which has less association with the programmable system architecture and is more independent. The configuration control system architecture directly determines the supported configuration interface and configuration mode, power-on initialization and configuration time, chip wake-up flow and the like.

The current SRAM type FPGA configuration control system architecture can only provide rich configuration interfaces, the reusability and the expandability are poor, the configuration time is long, and the requirement of rapid configuration cannot be met; the antifuse-type FPGA can meet the requirement of fast configuration, but has poor flexibility and supports fewer configuration interfaces.

Disclosure of Invention

In order to solve the defects of the prior art, the present application provides an FPGA configuration control system, an FPGA configuration method, and an FPGA chip, where the system has high expansibility and can be flexibly configured, and can meet both the configuration interface and the control function of the configuration control system of an SRAM type FPGA and the characteristic of nonvolatile data stream storage of data of an eFlash type FPGA configuration control system, and two configuration paths are relatively independent, and FPGAs compatible with different bit stream sizes and configuration speed requirements can be extended through different configurations.

In order to achieve the above object, the present invention employs the following techniques:

an FPGA configuration control system comprising:

the general FPGA configuration interface module is used for providing a general configuration interface;

a JTAG interface module for providing a JTAG interface;

the configurable parameterized eFlash array is used for storing data, is a nonvolatile storage Flash unit embedded in a chip and is used for calling a plurality of eFlash IPs through parameter configuration;

the eFlash control module is connected with the JTAG interface module and the eFlash array and used for generating an eFlash read-write erasing control time sequence, writing configuration data into the eFlash array and loading and reading the configuration data from the eFlash array;

the data bus control module is connected with the JTAG interface module and the general FPGA configuration interface module and is used for converting bus data of the JTAG interface module and the general FPGA configuration interface module into an internal data structure and splitting the data to analyze the configuration data;

the frame data selector is connected with the data bus control module and the eFlash control module and used for selecting the configuration data from the data bus control module or the eFlash control module to be input to the FPGA programmable system of the FPGA chip;

the configurable parameterized configuration SRAM controller is connected with the frame data selector, is used for being connected with an FPGA programmable system of the FPGA chip, and is used for realizing the read-write operation of an FPGA configuration information storage array in the FPGA programmable system.

Further, the data bus control module includes:

the interface conversion module is connected with the JTAG interface module and the general FPGA configuration interface module and is used for converting bus data of the JTAG interface module and the general FPGA configuration interface module into an internal data structure so as to transmit the internal data structure to the data packet disassembling module;

and the data packet disassembling module is connected with the interface conversion module and the eFlash control module and is used for disassembling the input data and analyzing the configuration data so as to transmit the configuration data to the configuration SRAM controller through the frame data selector.

Further, the data bus control module further comprises a decryption module, which is connected with the interface conversion module, the data packet disassembling module and the eFlash control module, and is used for receiving the internal data structure converted by the interface conversion module when the bus data received by the interface conversion module is the encrypted configuration data, decrypting the encrypted configuration data by combining the KEY value of the eFlash control module, and outputting the plaintext configuration data to the data packet disassembling module.

Further, configuring the SRAM controller comprises:

the frame address control unit is used for generating a frame address for addressing the FPGA configuration information storage array;

the frame data input control unit is used for transmitting the configuration data output by the frame data selector to the FPGA configuration information storage array;

the frame data output control unit is used for receiving the configuration data read back from the FPGA configuration information storage array;

and the MBIST control unit is used for realizing self-test of the FPGA configuration information storage array.

And the system further comprises a configuration control module for controlling the configuration process of the FPGA chip.

An FPGA configuration method is applied to configuration of an FPGA chip, the FPGA chip comprises an FPGA configuration control system, and the configuration method comprises a power-on rapid configuration step and/or a data bit width configuration step;

a quick power-on configuration step: calculating the time required for configuring the whole FPGA chip when one eFlash is embedded according to the data bit width of the eFlash in the eFlash array and the corresponding data access time; according to the area allowance condition of the current FPGA chip, the quantity of eFlash in an eFlash array is configured in a parameterization mode to be n, wherein n is an integer larger than 1, the time required by the whole FPGA chip is divided by n to obtain the time required by the whole FPGA chip after the parameterization configuration, and the rapid configuration is realized;

and data bit width configuration: setting a data bit width parameter according to the configuration data shift chain module interface width in the FPGA programmable system; obtaining a shift setting number N by using a data bit width parameter divided by an eFlash bit width in an eFlash array, wherein N is an integer greater than 1; and moving the configuration data shift chain module once every N clock cycles until the configuration data shift chain module is filled with data, and loading data of one frame to the FPGA configuration information storage array.

An FPGA chip comprises the FPGA configuration control system.

The invention has the beneficial effects that:

1. according to the FPGA configuration control system framework, the configuration interface can be flexibly expanded, the configuration of an FPGA chip can be realized through an external interface (a JTAG interface and a general FPGA configuration interface), and the configuration data can be automatically loaded from an eFlash array and sent to the FPGA configuration information storage array after being electrified, so that the FPGA function required by a user can be quickly realized;

2. the configuration data stored in the eFlash can come from a JTAG configuration interface, and can also be directly read from the FPGA configuration information storage array and written into the eFlash array, so that the software operation steps are greatly simplified;

3. the configurable parameterized configuration SRAM controller and the configurable parameterized eFlash array which are arranged in the invention can greatly improve the adaptability of the configuration control system architecture, improve the power-on loading configuration rate of the eFlash type FPGA and increase the configuration data bit width in the FPGA configuration control system architecture through the parameter configuration step.

Drawings

Fig. 1 is a schematic structural diagram of an FPGA configuration control system and an FPGA chip according to an embodiment of the present application.

Fig. 2 is a flowchart of a power-on fast configuration procedure according to an embodiment of the present application.

Fig. 3 is a flowchart of data bit width configuration steps according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a chip operation stage according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings, but the described embodiments of the present invention are a part of the embodiments of the present invention, not all of the embodiments of the present invention.

The embodiment of the present application relates to integrated circuit chip design, and in one aspect, provides an FPGA configuration control system, as shown in fig. 1, an architecture of an FPGA configuration control system 101 of this example includes: a general FPGA configuration interface module 106, a JTAG interface module 107, a data bus control module 108, an eFlash control module 112, a frame data selector 113, a configurable parameterized configuration SRAM controller 114, a configurable parameterized eFlash array 120, and the like.

Here, in order to explain the FPGA configuration control system 101 of the present example, the FPGA programmable system of the FPGA is explained by taking the FPGA programmable system 102 shown in fig. 1 as an example. In this example, the FPGA programmable system 102 includes an FPGA configuration information storage array 123, and an address decoding module 121 and a configuration data shift chain module 122 connected thereto.

For the FPGA configuration control system 101 of the present example, in particular, the generic FPGA configuration interface module 106 is used to provide a generic configuration interface. Further, as some optional ways, the common configuration interface includes an interface supporting data transmission protocols of a master string, a master parallel, a slave string, a slave parallel, BPI, and SPI.

The JTAG interface module 107 is used to provide a JTAG interface, which supports the IEEE1149.1 (boundary scan test) and IEEE1532 (programmable device in system configuration) standards.

The configurable parameterized eFlash array 120 is a nonvolatile storage Flash unit embedded in a chip, and comprises a plurality of eFlash units, wherein the eFlash units are used for storing data, determining the configuration quantity and capacity according to FPGA configuration data, and then parameterizing the number of the eFlash units by combining layout area and the requirement of the electrified Loading time. Through parameter configuration, calling of a plurality of eFlash IPs is realized, and the configuration rate of the eFlash type FPGA after being electrified is improved.

The eFlash control module 112 is connected with the JTAG interface module 107 and the eFlash array 120 and is used for generating an eFlash read-write erasing control time sequence, writing configuration data into the eFlash array 120 and loading and reading the configuration data from the eFlash array 120; the JTAG interface module 107 can access the eFlash array 120 by reading and writing through the eFlash control module 112, and is used to transmit FPGA configuration data.

The data bus control module 108 is connected to the JTAG interface module 107 and the general FPGA configuration interface module 106, and is configured to convert bus data of the JTAG interface module 107 and the general FPGA configuration interface module 106 into an internal data structure, and split the data to analyze configuration data.

The frame data selector 113 is connected to the data bus control module 108 and the eFlash control module 112, and is configured to select configuration data from the data bus control module 108 or the eFlash control module 112 for input to the FPGA programmable system 102 of the FPGA.

The configurable parameterized configuration SRAM controller 114 is connected to the frame data selector 113, and is configured to be connected to the FPGA programmable system 102 of the FPGA, so as to implement read/write operations on the FPGA configuration information storage array 123 in the FPGA programmable system 102. The configuration SRAM controller 114 can configure FPGAs with different configuration data shift chain modules 122 data widths by adjusting parameters.

The FPGA configuration control system 101 of this embodiment supports flexible extension of configuration interfaces, and can directly configure the configuration information on the FPGA chip through the general FPGA configuration interface module 106 or the JTAG interface module 107, and each configuration interface module and the data bus control module are respectively interconnected through an internal standard bus, and are relatively independent, and configuration interfaces can be flexibly increased or decreased according to requirements.

After the FPGA completes online debugging, the eFlash control module 112 can directly read configuration data from the FPGA configuration information storage array 123 and write the configuration data into the eFlash array 120. In order to realize rapid configuration, after being powered on, the eFlash control module 112 can automatically load configuration data from the eFlash array 120, and send the configuration data to the FPGA configuration information storage array 123 through the frame data selector 113 and the configuration SRAM controller 114, so as to rapidly realize the FPGA function required by the user.

As some optional ways, the data bus control module 108 includes an interface conversion module 109 and a packet disassembly module 111. The interface conversion module 109 is connected with the JTAG interface module 107 and the general FPGA configuration interface module 106, and can convert bus data of the JTAG interface module 107 and the general FPGA configuration interface module 106 into an internal data structure to be transmitted to the data packet disassembling module 111; the data packet disassembling module 111 is connected to the interface conversion module 109 and the eFlash control module 112, and performs a disassembling process on the input data to analyze the configuration data, so as to transmit the configuration data to the configuration SRAM controller 114 through the frame data selector 113, and then the configuration SRAM controller 114 writes the configuration data into the FPGA configuration information storage array 123.

As a further preferred mode, the data bus control module 108 further comprises a decryption module 110. The decryption module 110 is connected to the interface conversion module 109, the packet disassembly module 111, and the eFlash control module 112. When the bus data received by the interface conversion module 109 is the encrypted configuration data, the decryption module 110 receives the internal data structure converted by the interface conversion module 109, decrypts the encrypted configuration data by combining the KEY value of the eFlash control module 112, outputs the plaintext configuration data to the data packet disassembling module 111, and then the data packet disassembling module 111 performs disassembling processing and analyzes to obtain the decrypted configuration data, so as to transmit the decrypted configuration data to the configuration SRAM controller 114 through the frame data selector 113, and then the configuration SRAM controller 114 writes the decrypted configuration data into the FPGA configuration information storage array 123.

As some optional ways, as shown in fig. 1, the configuration SRAM controller 114 includes a frame address control unit 115, a frame data input control unit 116, a frame data output control unit 117, and an MBIST control unit 118.

The frame address control unit 115 is configured to generate a frame address for addressing the FPGA configuration information storage array 123. The frame data input control unit 116 is used to transmit the configuration data output by the frame data selector 113 to the FPGA configuration information storage array 123. And a frame data output control unit 117, configured to receive configuration data read back from the FPGA configuration information storage array 123, so that an external host can read the configuration data through the JTAG interface module 107/the general FPGA configuration interface module 106, the data bus control module 108, and the frame data selector 113, or can read the data through the eFlash control module 112, and write the data into the eFlash array 120. The MBIST control unit 118 is used for realizing self-testing of the FPGA configuration information storage array 123, sending a self-testing instruction through the JTAG interface module 107, transmitting the self-testing instruction to the MBIST control unit 118 after passing through the data bus control module 108 and the frame data selector 113, automatically generating a testing pattern after the MBIST control unit 118 receives the self-testing instruction, carrying out self-testing on the FPGA configuration information storage array 123, and recording a testing result, wherein the testing result can be read out through the JTAG interface module 107.

As a more specific alternative, the architecture of the FPGA configuration control system 101 of this example further includes a configuration control module 119, as shown in fig. 1, where the configuration control module 119 is connected to the data bus control module 108 and the FPGA programmable system 102, and is used for controlling the configuration process of the FPGA. Specifically, the configuration control module 119 is connected to the parsing module of the packet parsing module 111.

Specifically, the configuration control module 119 includes a configuration register, an FPGA wakeup control unit, an FPGA configuration process control unit, and an FPGA multi-start control unit.

And the configuration register is used for storing configuration options, CRC data check and state record of the configuration process chip.

And the FPGA awakening control unit is used for sequentially starting or closing global signals such as RELEASE _ DONE, GTS, GWE, EOS and the like of the FPGA according to a starting sequence set by a user.

And the FPGA configuration process control unit is used for generating a configuration control signal according to the storage configuration options and ensuring the correct writing of the configuration data.

The FPGA multi-start control unit is used for realizing that the FPGA can be dynamically switched among a plurality of configuration graphs; and when an error is detected during the multi-boot configuration process, the control FPGA may trigger a rollback function to ensure that a known good design is loaded into the device.

The packet disassembling module 111 further sends the analyzed configuration data to the register array in the configuration control module 119, and controls data reading and writing of each register. The register array includes a configuration option register, a CRC register, an instruction register, a control register, a mask register, a status register, a device ID register, a warm boot address register, a watchdog register, a boot history status register, and the like.

In the architecture of the FPGA configuration control system 101 of the present example, as shown in fig. 1, a reset control module 103, a clock control module 104, and a configuration state machine 105 are further included.

The reset control module 103 is used as a reset management module, and a reset source is from a power-on reset pin and an external reset pin; the clock control module 104 serves as a clock management module, and the clock source comprises an internal clock and an external clock pin; the configuration state machine 105 is used as a status jump controller in the entire configuration process to control the operating state of the chip. The working state of the chip is mainly divided into three stages, as shown in fig. 4, a device establishing stage, a data stream loading stage and a wake-up stage. The device establishing stage comprises equipment power-on, configuration register clearing and sampling mode pins; the data stream loading stage comprises data synchronization, equipment ID check, configuration data downloading and CRC check; the wake-up phase includes a start-up sequence.

The FPGA configuration control system architecture of the embodiment supports a plurality of configuration paths, and each submodule and each path are independent from each other and can be flexibly adjusted according to actual requirements.

The FPGA configuration control system architecture of the embodiment can realize rapid configuration design of the eFlash type FPGA after being electrified. The power-on loading configuration rate of the FPGA is closely related to the data transmission rate of the eFlash, and the power-on loading configuration rate of the FPGA is improved by increasing the bit width of configuration data (data butted with a configuration data shift chain) in a configuration system architecture. In the embodiment, the calling of a plurality of eFlash IPs in the eFlash array 120 can be realized through parameter configuration, the configuration data bit width in the FPGA configuration control system 101 framework is increased, and the configuration rate of the eFlash type FPGA after being electrified is improved.

In this example, the data flow written into the FPGA configuration information by the interface module is described in detail as follows:

after receiving the configuration data, the general FPGA configuration interface module 106 or the JTAG interface module 107 sends the configuration data to the data bus control module 108, the interface conversion module 109 in the data bus control module 108 converts the bus data into an internal data structure to be transmitted to the data packet disassembling module 111, if the received data is encrypted data, the data is transmitted to the decryption module 110, the decryption module 110 decrypts the encrypted configuration data by combining with the KEY value of the eFlash control module 112, and outputs plaintext configuration data to the data packet disassembling module 111, and after the data is processed by the data packet disassembling module 111, the data is sent to the configuration control module 119 according to the data type to start a configuration option, or sent to the configuration SRAM controller 114. The frame address control 115 and the frame number write-in control 116 of the SRAM controller 114 are configured to cooperate to generate a control timing sequence for controlling the address decoding module 121 and the configuration data shift chain module 122 in the FPGA programmable system 102, thereby implementing data write-in to the FPGA configuration information storage array 123.

In this example, the data flow for reading out the FPGA configuration information through the interface module is described in detail as follows:

when a read-back command is sent to the configuration SRAM controller 114 from the general FPGA configuration interface module 106 or the JTAG interface module 107 through a write FPGA configuration information data stream, the frame address control 115 and the frame number output control 117 of the configuration SRAM controller 114 cooperate to generate a control timing sequence for controlling the address decoding module 121 and the configuration data shift chain module 122 in the FPGA programmable system 102, read data stored in the FPGA configuration information storage array 123 to the configuration SRAM controller 114, send the data to the data bus control module 108 through the frame data selector 113, the data bus control module 108 converts the data into an interface data format, and transmits the interface data format to the general FPGA configuration interface module 106 or the JTAG interface module 107, thereby implementing data reading. If read protection is turned on, the read-back data is invalid.

In this example, the details of the data stream for reading out and writing the FPGA configuration information into the eFlash array 120 are as follows:

after the FPGA completes online debugging, the eFlash control module 112 sends a read command to the data packet disassembling module 111, the analyzed eFlash read command is sent to the configuration SRAM controller 114 through the frame data selector 113, the frame address control 115 and the frame number output control 117 of the configuration SRAM controller 114 are matched to generate a control time sequence for controlling the address decoding module 121 and the configuration data shift chain module 122 in the FPGA programmable system 102, the data stored in the FPGA configuration information storage array 123 is read out to the configuration SRAM controller 114, the data is sent to the eFlash control module 112 through the frame data selector 113, the eFlash control module 112 generates a time sequence for writing the eFlash array 120, and the received FPGA configuration information is written into the eFlash array 120.

In this example, the data flow for reading data from the eFlash array 120 and writing the data into the FPGA configuration information is described in detail as follows:

after being electrified, the configuration data can be automatically loaded from the eFlash array 120 and sent to the configuration SRAM controller 114 through the frame data selector 113, and the FPGA configuration data is sent to the FPGA configuration information storage array 123 through the cooperation of the frame address control 115 and the frame data input control 116, so that the FPGA function required by a user can be quickly realized.

In another aspect of the embodiment of the present application, an FPGA configuration method is provided, where an FPGA chip is configured based on the FPGA configuration control system 101 described in the foregoing embodiment, and the FPGA chip includes the FPGA configuration control system 101 and the FPGA programmable system 102.

The configuration method comprises a power-on rapid configuration step and/or a data bit width configuration step.

As shown in fig. 2, the step of power-on fast configuration includes:

s101, calculating the time required for configuring the whole FPGA chip when one eFlash is embedded according to the data bit width of the eFlash in the eFlash array 120 and the corresponding data access time;

s102, configuring the quantity of the eFlash in the eFlash array 120 as n through parameterization according to the area allowance condition of the current FPGA chip, wherein the n is an integer larger than 1;

s103, configuring the time required by the whole FPGA chip after obtaining the parameterized configuration by dividing the time required by the whole FPGA chip by n, and realizing rapid configuration.

Taking an FPGA chip with configuration information of 20Mbit as an example, comparing the configuration of the FPGA chip by using the general FPGA configuration interface module 106 and the eFlash array 120:

after the chip is powered on, the FPGA chip is configured by using the FPGA general configuration interface module 106, if serial configuration is selected by the FPGA general configuration interface module 106, a data bit width is 1bit, a fastest clock frequency is 100MHz, and it is calculated that 210ms (20 × 1024 × 1024 ÷ 1 × 10= 209715200ns) is required for configuring the whole FPGA chip. This configuration requires either an external host or non-volatile memory hardware on the system application board.

After the chip is powered on, the general configuration interface module 106 of the FPGA chip is used to configure the FPGA, if the general configuration interface module 106 of the FPGA chip selects parallel configuration, the data bit width is 32bit, the fastest clock frequency is 100MHz, and it is calculated that 6.6ms (20 × 1024 × 1024 ÷ 32 × 10= 6553600ns) is required for configuring the whole FPGA chip. This configuration requires either an external host or non-volatile memory hardware on the system application board.

After the chip is powered on, the eFlash array 120 in the FPGA chip is started to configure the FPGA chip. If the data bit width of the eFlash is 64 bits, the data access time is 35ns (namely, the 64-bit data stored in the eFlash can be read out by 35 ns). Conventionally, one eFlash is embedded, and it can be calculated that 11.47ms (20 × 1024 × 35 ÷ 64= 11468800ns) is required for configuring the whole FPGA chip. Under the condition that the area is allowed, the number of the eFlash is configured in a parameterization mode is 4, and the calculation result shows that only 2.87ms (20 multiplied by 1024 multiplied by 35 ÷ 64 ÷ 4 =2867200ns) is needed for configuring the whole FPGA chip, so that the power-on configuration waiting time of the FPGA chip is greatly reduced, and the rapid configuration is realized; and by using the configuration mode, the system application board card does not need an external host or nonvolatile memory hardware.

As shown in fig. 3, the data bit width configuring step includes:

s201, setting a data bit width parameter according to the interface width of a configuration data shift chain module 122 in the FPGA programmable system 102;

s202, obtaining a displacement setting number N by using a data bit width parameter divided by an eFlash bit width in the eFlash array 120, wherein N is an integer greater than 1;

s203, moving the configuration data shift chain module 122 once every N clock cycles until the configuration data shift chain module 122 is filled with data, and loading data of one frame into the FPGA configuration information storage array 123.

Through the implementation of the FPGA configuration control system architecture and the data bit width configuration steps of the embodiment, the FPGA configuration control system architecture can be compatible with different sizes of SRAM type FPGAs, the configuration of the configuration data shift chain module 122 width FPGAs in different FPGA programmable systems 102 can be realized through parameter adjustment, and the FPGA configuration data shift chain module 122 with more bit width types can be compatible with the flexible FPGA configuration situation of the eFlash array 120.

The conventional configuration modules are designed in a customized manner according to the corresponding configuration data shift chain module 122, and can only adapt to configurations with fixed bit widths. For example, the length of the data frame is 3072 bits, the interface width of the configuration data shift chain module 122 of the FPGA programmable system 102 is 32 bits, the configuration module sends out data with a data bit width of 32 bits, the configuration data shift chain module 122 moves data once per clock cycle, and after 96 (3232 ÷ 32 × 1= 96) clock cycles, the configuration data shift chain module 122 is filled with data and starts to load the data into the FPGA configuration information storage array 123 corresponding to the frame address.

In this example, the bit width for accessing the configuration data is parameterized, and a shift counter is added to the configuration SRAM controller 114 to be used in cooperation with the bit width of the configuration data, thereby implementing data writing with different bit widths.

If the data frame length is 3072 bits, the interface width of the configuration data shift chain module 122 of the FPGA programmable system 102 is 256 bits, and the eflash bit width is 256 bits, the data bit width parameter is set to 256, the shift counter is set to 1 (256 ÷ 256= 1), the configuration data shift chain module 122 is moved once every clock cycle, the configuration data shift chain module 122 is filled with data after 12 (3072 ÷ 256 × 1= 12) cycles, and the data of one frame is loaded to the FPGA configuration information storage array 123.

If the data frame length is 3072 bits, the interface width of the configuration data shift chain module 122 of the FPGA programmable system 102 is 256 bits, and the eflash bit width is 64 bits, the data bit width parameter is set to 256, the shift counter is set to 4 (256 ÷ 64= 4), the configuration data shift chain module 122 moves once every 4 clock cycles, and after 48 (3072 ÷ 256 × 4= 48) cycles, the configuration data shift chain module 122 is filled with data, and data of one frame is loaded to the FPGA configuration information storage array 123.

If the data frame length is 3072 bits, the configuration data shift chain module 122 of the FPGA programmable system 102 has an interface width of 128bit, and the eflash bit width is 64bit, then the data bit width parameter is set to 128, the shift counter is set to 2 (128 ÷ 64= 2), the configuration data shift chain module 122 is configured to move once every 2 clock cycles, and the configuration data shift chain module 122 is configured to fill with data and start loading after 48 (3072 ÷ 128 × 2= 48) cycles.

The configuration of the FPGA with different configuration data shift chain modules 122 data widths can be realized by parameter adjustment in this example.

In another aspect of the embodiments of the present application, an FPGA chip is provided, which includes the FPGA configuration control system 101 and the FPGA programmable system described in the foregoing embodiments.

Specifically, as shown in fig. 1, which is an example of an overall structure of an FPGA chip of this example, the FPGA programmable system 102 shown in fig. 1 is only an example of one FPGA programmable system, and according to an implementation manner of an overall architecture of an FPGA, a person skilled in the art may select other suitable FPGA programmable systems.

In this example, the FPGA programmable system 102 is connected to a configurable parameterized configuration SRAM controller 114, which includes an FPGA configuration information storage array, and an address decoding module 121 and a configuration data shift chain module 122 connected thereto.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and it is apparent that those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application.

Claims

1. An FPGA configuration control system, characterized in that its architecture comprises:

a general FPGA configuration interface module (106) for providing a general configuration interface;

a JTAG interface module (107) for providing a JTAG interface;

an eFlash array (120) for storing data;

the eFlash control module (112) is connected with the JTAG interface module (107) and the eFlash array (120) and is used for generating an eFlash read-write erasing control time sequence, writing configuration data into the eFlash array (120) and loading and reading the configuration data from the eFlash array (120);

the data bus control module (108) is connected with the JTAG interface module (107) and the general FPGA configuration interface module (106) and is used for converting bus data of the JTAG interface module (107) and the general FPGA configuration interface module (106) into an internal data structure and splitting the data to analyze configuration data;

the frame data selector (113) is connected with the data bus control module (108) and the eFlash control module (112) and is used for selecting the configuration data from the data bus control module (108) or the eFlash control module (112) for inputting to the FPGA programmable system (102) of the FPGA chip;

and the configuration SRAM controller (114) is connected with the frame data selector (113), is used for being connected with the FPGA programmable system (102) of the FPGA chip, and is used for realizing the read-write operation of the FPGA configuration information storage array (123) in the FPGA programmable system (102).

2. The FPGA configuration control system of claim 1 wherein the generic configuration interface comprises one or more of a master string, a master parallel, a slave string, a slave parallel, a BPI, an SPI.

3. The FPGA configuration control system of claim 1, wherein the JTAG interface module (107) is configured to access the eFlash array (120) by read and write access of the eFlash control module (112) and to transmit FPGA configuration data.

4. The FPGA configuration control system of claim 1, wherein the data bus control module (108) comprises:

the interface conversion module (109) is connected with the JTAG interface module (107) and the general FPGA configuration interface module (106) and is used for converting bus data of the JTAG interface module (107) and the general FPGA configuration interface module (106) into an internal data structure to be transmitted to the data packet disassembling module (111);

and the data packet disassembling module (111) is connected with the interface conversion module (109) and the eFlash control module (112) and is used for performing disassembling processing on input data, analyzing configuration data and transmitting the configuration data to the configuration SRAM controller (114) through the frame data selector (113).

5. The FPGA configuration control system of claim 4, wherein the data bus control module (108) further comprises a decryption module (110), which is connected to the interface conversion module (109), the packet disassembly module (111), and the eFlash control module (112), and is configured to receive the internal data structure converted by the interface conversion module (109) when the bus data received by the interface conversion module (109) is the encrypted configuration data, decrypt the encrypted configuration data by combining the KEY value of the eFlash control module (112), and output the plaintext configuration data to the packet disassembly module (111).

6. The FPGA configuration control system of claim 1, wherein configuring the SRAM controller (114) comprises:

a frame address control unit (115) for generating a frame address for addressing the FPGA configuration information storage array (123);

a frame data input control unit (116) for transmitting the configuration data output by the frame data selector (113) to the FPGA configuration information storage array (123);

a frame data output control unit (117) for receiving configuration data read back from the FPGA configuration information storage array (123);

and the MBIST control unit (118) is used for realizing self-test of the FPGA configuration information storage array (123).

7. The FPGA configuration control system of claim 1, wherein the architecture further comprises a configuration control module (119) for controlling a configuration process of the FPGA chip.

8. The FPGA configuration control system of claim 7, wherein the configuration control module (119) comprises:

the configuration register is used for storing configuration options, CRC data check and state records of the FPGA chip in the configuration process;

the FPGA wake-up control unit is used for sequentially turning on or turning off global signals of the FPGA chip according to a start sequence set by a user;

the FPGA configuration process control unit is used for generating a configuration control signal according to the storage configuration options and ensuring the correct writing of the configuration data;

the FPGA multi-start control unit is used for realizing the dynamic switching of the FPGA chip among a plurality of configuration graphs; and when an error is detected in the multi-start configuration process, the FPGA chip is controlled to trigger the rollback function.

9. An FPGA configuration method is characterized in that an FPGA chip is configured based on the FPGA configuration control system as claimed in any one of claims 1 to 8, and the configuration method comprises a power-on rapid configuration step and/or a data bit width configuration step;

the power-on rapid configuration step comprises:

according to the data bit width of the eFlash in the eFlash array (120) and the corresponding data access time, calculating the time required for configuring the whole FPGA chip when one eFlash is embedded;

according to the area allowance condition of the current FPGA chip, the quantity of eFlash in an eFlash array (120) is configured in a parameterization mode to be n, n is an integer larger than 1, the time required by the whole FPGA chip is obtained by dividing the time required by the configuration of the whole FPGA chip by n, and the time required by the configuration of the whole FPGA chip is obtained after the parameterization configuration, so that the rapid configuration is realized;

the data bit width configuration step comprises the following steps:

setting a data bit width parameter according to the interface width of a configuration data shift chain module (122) in the FPGA programmable system (102);

obtaining a displacement setting number N by using a data bit width parameter divided by an eFlash bit width in an eFlash array (120), wherein N is an integer greater than 1;

the configuration data shift chain module (122) is moved once every N clock cycles until the configuration data shift chain module (122) is filled with data and one frame of data is loaded into the FPGA configuration information storage array (123).

10. An FPGA chip, characterized by comprising the FPGA configuration control system of any one of claims 1 to 8.