CN115310244B - Wiring pattern generation method, electronic device, storage medium, and program product - Google Patents
Wiring pattern generation method, electronic device, storage medium, and program product Download PDFInfo
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- CN115310244B CN115310244B CN202210964170.6A CN202210964170A CN115310244B CN 115310244 B CN115310244 B CN 115310244B CN 202210964170 A CN202210964170 A CN 202210964170A CN 115310244 B CN115310244 B CN 115310244B
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Abstract
The present disclosure provides a wiring diagram generation method, including: analyzing original house type data of the building unit to obtain point location characteristic information of each point location in the original house type data; acquiring at least one wiring loop based on point location characteristic information of each point location; for each wiring loop, acquiring inter-point characteristic information of each point; dividing each point location in each wiring loop into one or more than two areas based on the characteristic information among the point locations; acquiring the end point location of each fragment based on the point location characteristic information and the inter-point location characteristic information of each point location in each fragment; for each routing loop, the termination points of each tile are connected and the points in each tile are connected to generate a routing graph. The present disclosure also provides an electronic device, a readable storage medium, and a program product.
Description
Technical Field
The present disclosure relates to a wiring diagram generation method, an electronic device, a storage medium, and a program product.
Background
The Building Information Modeling (BIM) is a digital model which is used for carrying out full life cycle design, construction and operation service on decoration projects on the basis of various relevant Information data of the decoration projects. The designer uses the BIM software to design the finishing scheme.
Because the designer generally can not solve the rule of water and electricity wiring, can't manual design water and electricity circuit diagram, even know water and electricity wiring rule, manual design water and electricity circuit diagram is also more loaded down with trivial details, and designer and user expect that BIM software possesses the ability of intelligent wiring, can draw the water and electricity wiring that accords with the construction requirement automatically, reduce the design mistake when saving designer's work load.
And the use of pipeline material in the water and electricity wiring process accounts for the very big part of material use in whole fitment process, according to statistics, the single item water and electricity cost about 3 ten thousand yuan of 80 square meters's house, consequently, expects that automatic wiring system can be when guaranteeing the water and electricity position intercommunication, makes the line of walking shorter as far as possible with material cost saving.
Disclosure of Invention
The disclosure provides a wiring diagram generation method, an electronic device, a storage medium, and a program product.
According to an aspect of the present disclosure, there is provided a wiring diagram generation method including:
analyzing original house type data of the building unit to obtain point location characteristic information of each point location in the original house type data;
acquiring at least one wiring loop based on point location characteristic information of each point location;
for each wiring loop, acquiring inter-point characteristic information of each point;
dividing each point in each wiring loop into one or more than two regions based on the characteristic information among the points;
acquiring the end point location of each fragment based on the point location characteristic information and the inter-point location characteristic information of each point location in each fragment;
for each routing loop, the termination points of each tile are connected and the points in each tile are connected to generate a routing graph.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, acquiring point location characteristic information of each point location in original house type data includes:
and acquiring the point location type of each point location in the original house type data and the mapping relation between each point location and other elements in the original house type data.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, acquiring at least one wiring loop based on point location characteristic information of each point location includes:
and obtaining the wiring loop to which each point location belongs based on the point location type of each point location and the mapping relation between each point location and other elements so as to obtain at least one wiring loop.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, for each wiring loop, obtaining inter-point feature information of each point, includes:
point location ordering information of each point location in a preset direction (counterclockwise direction of each point location List) and point location horizontal distance information between adjacent point locations in each wiring loop are obtained.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, dividing each point location in each wiring loop into one or two or more segments based on the inter-point location characteristic information includes:
and carrying out partition division on the point positions based on the point position sequencing information in each wiring loop and the point position horizontal spacing information between the adjacent point positions so as to divide each point position of each wiring loop into one partition or more than two partitions.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, acquiring the end point position of each patch area based on the point position characteristic information and the inter-point position characteristic information of each point position in each patch area includes:
and acquiring the end point location based on the point location height information and the point location sequencing information of each point location in each fragment. Preferably, the point location characteristic information further includes point location height information.
According to a wiring pattern generation method of at least one embodiment of the present disclosure, for each wiring loop, connecting end point positions of respective patches and connecting point positions in the respective patches to generate a wiring pattern, includes:
each end point position is horizontally and directly connected after being arranged along the top position (such as the top edge of a wall body) so as to connect the end point positions of each plate area;
and performing horizontal direct connection after the upper edge of the point position in each sheet region reaches the maximum point position height in each sheet region so as to connect the point positions in each sheet region.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, acquiring at least one wiring loop based on point location characteristic information of each point location includes:
and storing the point location corresponding to each wiring loop into a point location List (List).
According to the wiring diagram generating method of at least one embodiment of the present disclosure, obtaining point location sorting information of each point location in each wiring loop in a preset direction (counterclockwise direction of each point location List), includes:
and sequencing all point locations of each wiring loop according to the preset direction, and sequencing more than two point locations in the same vertical direction based on the point location height from high to low to obtain the point location sequencing information.
According to the wiring diagram generation method of at least one embodiment of the present disclosure, partitioning point locations based on the point location ranking information and the point location horizontal pitch information between the adjacent point locations in each wiring loop, includes:
sequentially traversing each point location based on the point location sequencing information, and if the point location is a first point location, dividing the point location into a first fragment area; if the point location is not the first point location, calculating the horizontal distance between the point location and the previous point location, if the horizontal distance is smaller than or equal to a preset distance value (for example, 30 cm), dividing the point location into a segment where the previous point location is located, otherwise, newly building a segment, and dividing the newly built segment into the newly built segment until all the point locations are divided into corresponding segments.
According to another aspect of the present disclosure, there is provided an electronic device including:
a memory storing execution instructions;
a processor executing the execution instructions stored by the memory, such that the processor performs the wiring diagram generation method of any one of the embodiments of the present disclosure.
According to still another aspect of the present disclosure, there is provided a readable storage medium having stored therein an execution instruction, the execution instruction being executed by a processor to implement the wiring diagram generation method of any one of the embodiments of the present disclosure.
According to yet another aspect of the present disclosure, there is provided a computer program product comprising a computer program/instructions which, when executed by a processor, implement the wiring diagram generation method of any one of the embodiments of the present disclosure.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram of an automatic wiring result in the related art.
Fig. 2 is a flowchart illustrating a wiring diagram generation method according to an embodiment of the present disclosure.
FIG. 3 shows a flow diagram for zoning various sites of each routing loop according to one embodiment of the present disclosure
Fig. 4 is an example diagram of a dot patch area of one embodiment of the present disclosure.
Fig. 5 illustrates a wiring pattern generated by the wiring pattern generation method of one embodiment of the present disclosure.
Fig. 6 is an overall flow diagram of an automatic wiring process according to an embodiment of the present disclosure.
Fig. 7 is a schematic block diagram of a configuration of a wiring diagram generation apparatus using a hardware implementation of a processing system according to an embodiment of the present disclosure.
Description of the reference numerals
1000. Wiring pattern generating device
1002. Analysis module
1004. Loop acquisition module
1006. Inter-point characteristic information acquisition module
1008. Partition module
1010. End point location acquisition module
1012. Wiring pattern generation module
1100. Bus line
1200. Processor with a memory having a plurality of memory cells
1300. Memory device
1400. Other circuits.
Detailed Description
The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Thus, unless otherwise indicated, the features of the various embodiments/examples may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.
The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order reverse to the order described. In addition, like reference numerals denote like parts.
When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.
Fig. 1 is a schematic diagram of an automatic wiring result in the related art. In the related art, automatic wiring is performed, point locations are generally connected by hand pulling, each point location is taken as an independent point location, and adjacent point locations are connected by walking on the top or walking on the ground, as shown in fig. 1, four adjacent point locations in fig. 1 need to be connected with the next point location by firstly jacking up and then descending down the wall. The automatic wiring in the related art has the following problems.
After wiring, the circuit is complicated, the appearance is influenced, and the construction of workers is difficult to guide; each point location needs to be connected with the next point location by jacking or descending, so that the line is long, and the use cost of materials is high; the amount of line usage cannot be accurately estimated, resulting in excessive dispensing of the actual material, resulting in material waste.
The wiring diagram generation method/apparatus of the present disclosure is described in detail below with reference to fig. 2 to 7.
Fig. 2 is a flowchart illustrating a wiring diagram generation method according to an embodiment of the present disclosure.
Referring to fig. 2, the wiring diagram generation method S100 of the present disclosure includes:
s102, analyzing original house type data of the building unit to obtain point location characteristic information of each point location in the original house type data;
s104, acquiring at least one wiring loop based on point position characteristic information of each point position;
s106, for each wiring loop, obtaining inter-point feature information of each point;
s108, dividing each point position in each wiring loop into one or more than two areas based on the characteristic information among the point positions;
s110, acquiring the end point position of each block based on the point position characteristic information and the inter-point position characteristic information of each point position in each block;
and S112, for each wiring loop, connecting end point positions of each chip area and connecting point positions in each chip area to generate a wiring diagram.
According to the wiring diagram generation method, the point location characteristic information of the wiring point location is obtained by analyzing the original house type data of the building unit, the wiring loop to which each point location belongs is identified based on the point location characteristic information of each point location, then the point location fragment area based on the characteristic information between the point locations is carried out on each wiring loop, and the tail end point locations of each fragment area are connected, so that the logic of the wiring diagram generation is clear and accurate, and the pipeline consumption for carrying out actual wiring operation based on the wiring diagram can be reduced.
For wiring loops with a large number of points, such as heavy-current socket loops, wiring operations are performed by using the wiring patterns generated by the wiring pattern generation method disclosed by the invention, and all the socket points in a room can be connected by the shortest pipeline to communicate the whole loop. The amount of piping calculated based on the artwork generated by the artwork generation method of the present disclosure can guide workers in accurate material ordering.
In the present disclosure, the building unit may be a residential house, such as a residential house in three rooms and one living room, a residential house in two rooms and one living room, or other types of houses, such as a commercial house, and the like.
The elements in the original house type data of the building unit described in the present disclosure include wall surfaces, rooms (bedrooms, living rooms, etc.), water supply point locations, power supply point locations, doors, windows, etc., and the element data includes wall surface spatial position/length/height, room spatial position/area, point location type/spatial position, etc., door spatial position, window spatial position, etc., and these element data are preferably stored in a Json data format.
According to the wiring diagram generation method S100 of the preferred embodiment of the present disclosure, acquiring point location characteristic information of each point location in the original house type data includes:
and acquiring the point location type of each point location in the original house type data and the mapping relation between each point location and other elements in the original house type data.
In this embodiment, the point location feature information includes a point location type and a mapping relationship between a point location and other elements.
In the present disclosure, the point location types may include a strong current socket point location, a switch point location, a lamp point location, a weak current socket point location, a cold water point location, a hot water point location, and the like.
In the present disclosure, the mapping relationships between elements, especially the mapping relationships between point locations and other elements, may be obtained through geometric computation, and the mapping relationships between rooms and gates, rooms and point locations, walls and gates, and the like may be computed through geometric computation and stored in Map (Map), and the computing method adopted is conventional geometric knowledge, such as: vector calculation, point-to-line distance calculation, coordinate calculation of point translation on a line, and the like, and the calculation method of the mapping relationship is not particularly limited in the present disclosure.
In some embodiments of the present disclosure, when analyzing the original house type data of the building unit, the mapping relationship between the elements is obtained comprehensively.
For the wiring diagram generation method S100 of each of the above embodiments, preferably, obtaining at least one wiring loop based on the point location characteristic information of each point location includes:
and obtaining the wiring loop to which each point location belongs based on the point location type of each point location and the mapping relation between each point location and other elements so as to obtain at least one wiring loop.
In some embodiments of the present disclosure, the routing loops to which the respective point locations belong are identified based on the types of the respective point locations and the spatial association (i.e., mapping) relationship between the point locations and other elements, and all the point locations of each routing loop may be placed in a List for storage.
In some embodiments of the present disclosure, the correspondence between the routing loop and the point location type is specifically as follows:
a common socket loop: the point location type is a common socket;
galley/bathroom outlet loop: the point location type is a common socket and is placed in a kitchen/toilet;
air conditioner socket return circuit: the point location type is an air conditioner socket;
an illumination loop: the point location type is lamp/switch;
a weak current loop: the point location type is a weak current socket;
a cold water loop: the point location type is a cold water point location;
a hot water loop: the point location type is a hot water point location.
In some embodiments of the present disclosure, preferably, for each routing loop, acquiring inter-site feature information of each site includes:
point location ordering information of each point location in each wiring loop in a preset direction (anticlockwise direction of each point location List) and point location horizontal distance information between adjacent point locations are obtained.
In some embodiments of the present disclosure, the inter-point characteristic information includes point ordering information and point horizontal spacing information between adjacent points.
For the wiring diagram generation method S100 of each of the above embodiments, preferably, dividing each point location in each wiring loop into one or two or more segments based on the point location characteristic information includes:
and performing partition division on the point positions based on the point position sequencing information in each wiring loop and the point position horizontal spacing information between adjacent point positions so as to divide each point position of each wiring loop into one partition or more than two partitions.
In the wiring diagram generation method according to some embodiments of the present disclosure, preferably, the partitioning of the point locations based on the point location sorting information and the point location horizontal pitch information between adjacent point locations in each wiring loop includes:
sequentially traversing each point location based on the point location sequencing information, and if the point location is a first point location, dividing the point location into a first fragment area; if the point location is not the first point location, calculating the horizontal distance between the point location and the previous point location, if the horizontal distance is smaller than or equal to a preset distance value (for example, 30 cm), dividing the point location into a segment where the previous point location is located, otherwise, newly building a segment, and dividing the newly built segment into the newly built segment until all the point locations are divided into corresponding segments.
Wherein each patch is a set of N (N is greater than or equal to 1) point locations.
According to a preferred embodiment of the present disclosure, obtaining point location sorting information of each point location in each routing loop in a preset direction (counterclockwise direction of each point location List) includes:
and sequencing the point locations of each wiring loop according to a preset direction, and sequencing more than two point locations in the same vertical direction based on the point location height from high to low to obtain point location sequencing information.
For example, two points are located in the same vertical direction, and a point with a high point height is located before a point with a low point height in the sorting.
FIG. 3 illustrates a flow diagram for zoning various sites of each routing loop in accordance with one embodiment of the present disclosure. The processing steps shown in fig. 3 are performed for each point of each routing loop.
Fig. 4 is an example diagram of a dot patch area of one embodiment of the present disclosure.
Referring to FIG. 4, a circuit containing six points A, B, C, D, E, F is illustratively shown.
Traversing the point A: a is the first point of the loop, so it is divided into the 1 st segment;
traversing the point B: the horizontal distance between the B and the A is 26cm and less than 30cm (namely a preset distance value is adjustable), and the condition that the distance is less than or equal to 30cm is met, so that the B is divided into a 1 st area where the A is located;
traversing point C: a point B is arranged in front of the point C, the horizontal distance between the point C and the point B is 10cm and less than 30cm, and the condition that the distance is less than or equal to 30cm is met, so that the point C is divided into a 1 st area where the point B is located;
traversing the point D: a point C is arranged in front of the point D, the horizontal distance between the point D and the point C is 38cm, is more than 30cm, and does not meet the condition that the distance is less than or equal to 30cm, so a 2 nd area is newly built and is divided into the 2 nd area;
traversing the point E: a point D is arranged in front of the E, the horizontal distance between the E and the D is 30cm and is equal to 30cm, and the condition that the distance is less than or equal to 30cm is met, so that the point D is divided into a 2 nd area where the D is located;
traversing the point location F: f is preceded by a point E, the horizontal distance between F and E is 18cm and less than 30cm, the condition that the distance is less than or equal to 30cm is met, and therefore the point E is divided into a 2 nd area where E is located.
In this example, after traversing all the point locations of the loop, two regions may be generated:
the 1 st area comprises three point positions A, B and C; the 2 nd area comprises three point positions of D, E and F.
For the wiring diagram generation method S100 of the present disclosure, preferably, obtaining the end point location of each patch area based on the point location characteristic information and the inter-point location characteristic information of each point location in each patch area includes:
and acquiring the end point location based on the point location height information and the point location sequencing information of each point location in each fragment.
In this embodiment, the point location feature information further includes point location height information.
In some embodiments of the present disclosure, it is preferable to obtain the end point position of each patch based on the following method.
Traversing a point location list corresponding to each fragment, and if the point locations in the list are different in height, taking the point location with the highest height as the end point location; if there are multiple point locations (more than two point locations) with the highest height, the leftmost point location is the end point location by default; if the point locations in the list are all the same height, the default leftmost point location is the end point location.
The acquisition of the end point location is explained in conjunction with fig. 4.
In slice 1: A. the three point positions B and C are different in height, so that the highest point position B is the tail end point position in the 1 st area;
in slice 2 zone: D. the highest point positions of E and F are E and F, the heights of the point positions are the same, and the default left F is the end point position in the 2 nd zone.
In some embodiments of the present disclosure, for each routing loop, connecting end point locations of respective tiles and connecting point locations in respective tiles to generate a routing graph, comprises:
connecting the end points of the various sections by performing horizontal straight connection after each end point is located along the top position (such as the top edge of a wall);
and performing horizontal direct connection after the upper edge of the point position in each section reaches the maximum point position height in each section so as to connect the point positions in each section.
Fig. 5 illustrates a wiring diagram generated by the wiring diagram generation method of one embodiment of the present disclosure.
Referring to fig. 5, horizontal straight connections are shown from the top edges of each of the end point locations (B and F) to a top position (e.g., the top edge of a wall) to connect the end point locations of each tile, and horizontal straight connections are shown from the top edges of the point locations in each tile to the maximum point location height in each tile to connect the point locations in each tile.
In FIG. 5, for the same height points, e.g., E and F, the transverse slots may be directly connected; for different height points, such as D and E, A and B, B and C, transverse slots and vertical slots are required to be connected.
The present disclosure also provides a wiring diagram generating apparatus 1000, including:
the analysis module 1002 is used for analyzing the original house type data of the building unit by the analysis module 1002 to obtain point location characteristic information of each point location in the original house type data;
the loop obtaining module 1004, the loop obtaining module 1004 obtaining at least one routing loop based on the point location characteristic information of each point location;
an inter-point characteristic information obtaining module 1006, where the inter-point characteristic information obtaining module 1006 obtains, for each wiring loop, inter-point characteristic information of each point;
the partitioning module 1008 is used for partitioning each point position in each wiring loop into one or more than two areas based on the characteristic information among the point positions;
the end point location obtaining module 1010 obtains an end point location of each segment based on the point location feature information and the inter-point location feature information of each point location in each segment;
and the wiring diagram generating module 1012, wherein the wiring diagram generating module 1012 connects the end point of each patch area and the point in each patch area to generate a wiring diagram for each wiring loop.
It should be noted that the wiring diagram generation apparatus of the present disclosure may be implemented based on a computer software program architecture.
The wiring diagram generation method/device disclosed by the invention can be used in the wiring diagram generation process of an automatic wiring system. The automatic wiring system of the present disclosure may include a BIM device (i.e., a BIM client) and the wiring diagram generating device 1000 of the present disclosure.
Firstly, designing a house type scheme at a BIM client, and placing points such as a socket, weak current, water, a lamp and a switch in the house type; storing the designed scheme; the original house type data of the plan is pushed to the wiring diagram generating apparatus 1000. The wiring pattern generating apparatus 1000 generates a wiring pattern based on the wiring pattern generating method described above.
In some embodiments of the present disclosure, the wiring diagram generated by the wiring diagram generating apparatus 1000 is sent to a BIM client and/or a rendering module (e.g., webGL) of an automatic wiring system for rendering processing to generate a rendering diagram.
Fig. 6 shows an overall flow diagram of an automatic wiring process of one embodiment of the present disclosure.
Fig. 7 is a schematic block diagram of a configuration of a wiring diagram generation apparatus employing a hardware implementation of a processing system according to an embodiment of the present disclosure.
The apparatus may include corresponding means for performing each or several of the steps of the flowcharts described above. Thus, each step or several steps in the above-described flow charts may be performed by a respective module, and the apparatus may comprise one or more of these modules. The modules may be one or more hardware modules specifically configured to perform the respective steps, or implemented by a processor configured to perform the respective steps, or stored within a computer-readable medium for implementation by a processor, or by some combination.
The hardware architecture may be implemented using a bus architecture. The bus architecture may include any number of interconnecting buses and bridges depending on the specific application of the hardware and the overall design constraints. The bus 1100 couples various circuits including the one or more processors 1200, the memory 1300, and/or the hardware modules together. The bus 1100 may also connect various other circuits 1400 such as peripherals, voltage regulators, power management circuits, external antennas, and the like.
The bus 1100 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one connection line is shown, but this does not indicate only one bus or one type of bus.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process, and alternate implementations are included within the scope of the preferred embodiment of the present disclosure in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the implementation of the present disclosure. The processor performs the various methods and processes described above. For example, method embodiments in the present disclosure may be implemented as a software program tangibly embodied in a machine-readable medium, such as a memory. In some embodiments, some or all of the software programs may be loaded and/or installed via memory and/or a communication interface. When the software program is loaded into memory and executed by a processor, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform one of the methods described above by any other suitable means (e.g., by means of firmware).
The logic and/or steps represented in the flowcharts or otherwise described herein may be embodied in any readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
For the purposes of this description, a "readable storage medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the readable storage medium include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable read-only memory (CDROM). In addition, the readable storage medium may even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in the memory.
It should be understood that portions of the present disclosure may be implemented in hardware, software, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following technologies, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps of the method implementing the above embodiments may be implemented by hardware that is instructed to be associated with a program, which may be stored in a readable storage medium, and which, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present disclosure may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
An electronic device according to an embodiment of the present disclosure includes:
a memory storing execution instructions;
the processor executes the execution instructions stored in the memory, so that the processor executes the wiring diagram generation method of any one embodiment of the disclosure.
According to a readable storage medium of an embodiment of the present disclosure, the readable storage medium has stored therein an execution instruction, and the execution instruction is executed by a processor to implement the wiring diagram generation method of any one embodiment of the present disclosure.
The computer program product according to an embodiment of the present disclosure includes a computer program/instruction that when executed by a processor implements the wiring diagram generation method of any one of the embodiments of the present disclosure.
In the description herein, reference to the description of the terms "one embodiment/implementation," "some embodiments/implementations," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/implementation or example is included in at least one embodiment/implementation or example of the present application. In this specification, the schematic representations of the terms described above are not necessarily the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
It will be understood by those skilled in the art that the foregoing embodiments are provided merely for clarity of explanation and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.
Claims (9)
1. A wiring pattern generation method, comprising:
analyzing original house type data of the building unit to obtain point location characteristic information of each point location in the original house type data;
acquiring at least one wiring loop based on point location characteristic information of each point location;
for each wiring loop, acquiring inter-point feature information of each point location, wherein the inter-point feature information of each point location of each wiring loop comprises point location sequencing information of each point location in a preset direction and point location horizontal spacing information between adjacent point locations;
dividing each point location in each wiring loop into one or more than two regions based on the characteristic information among the point locations, including: performing partition on the point locations based on the point location sequencing information in each wiring loop and the point location horizontal spacing information between the adjacent point locations, so as to partition each point location of each wiring loop into one partition or more than two partitions;
acquiring the end point location of each parcel based on the point location characteristic information and the inter-point location characteristic information of each point location in each parcel, comprising: acquiring end point positions based on point position height information and point position sequencing information of each point position in each block; and
for each routing loop, terminal point locations of the respective tiles are connected and point locations in the respective tiles are connected to generate a routing graph.
2. A wiring diagram generating method according to claim 1, wherein obtaining point location characteristic information of each point location in the original house type data includes:
and acquiring the point location type of each point location in the original house type data and the mapping relation between each point location and other elements in the original house type data.
3. The artwork generation method of claim 2, wherein obtaining at least one routing loop based on point location characteristic information of each point location comprises:
and obtaining the wiring loop to which each point location belongs based on the point location type of each point location and the mapping relation between each point location and other elements so as to obtain at least one wiring loop.
4. A wiring pattern generation method according to claim 1, wherein, for each wiring loop, connecting end point positions of the respective chip areas and connecting point positions in the respective chip areas to generate a wiring pattern, comprises:
carrying out horizontal and direct connection after each terminal point position is from the upper edge to the top position so as to connect the terminal point positions of each fragment area; and
and performing horizontal direct connection after the upper edge of the point position in each section reaches the maximum point position height in each section so as to connect the point positions in each section.
5. The artwork generation method of claim 1, wherein obtaining at least one routing loop based on point location characteristic information of each point location comprises:
the point locations corresponding to each routing loop are stored in a point location List (List).
6. A wiring diagram generating method according to claim 5, wherein obtaining point location ordering information of each point location in each wiring loop in a preset direction comprises:
and sequencing all point locations of each wiring loop according to the preset direction, and sequencing more than two point locations in the same vertical direction based on the point location height from high to low to obtain the point location sequencing information.
7. A wiring pattern generation method as described in claim 1, wherein the partitioning of the dots based on said dot sorting information and dot horizontal pitch information between said adjacent dots in each wiring loop comprises:
sequentially traversing each point location based on the point location sequencing information, and if the point location is a first point location, dividing the point location into a first fragment area; if the point location is not the first point location, calculating the horizontal distance between the point location and the previous point location, if the horizontal distance is smaller than or equal to a preset distance value, dividing the point location into a segment where the previous point location is located, otherwise, newly building a segment, and dividing the newly built segment to the newly built segment until all the point locations are divided into corresponding segments.
8. An electronic device, comprising:
a memory storing execution instructions; and
a processor that executes execution instructions stored by the memory to cause the processor to perform the wiring pattern generation method of any one of claims 1 to 7.
9. A readable storage medium, characterized in that the readable storage medium has stored therein an execution instruction, which when executed by a processor, is used to implement the wiring pattern generation method of any one of claims 1 to 7.
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| CN202210964170.6A CN115310244B (en) | 2022-08-11 | 2022-08-11 | Wiring pattern generation method, electronic device, storage medium, and program product |
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| CN202210964170.6A CN115310244B (en) | 2022-08-11 | 2022-08-11 | Wiring pattern generation method, electronic device, storage medium, and program product |
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| JP2020107121A (en) * | 2018-12-27 | 2020-07-09 | トヨタホーム株式会社 | Wiring design device |
| CN112926124A (en) * | 2021-03-26 | 2021-06-08 | 杭州后博科技有限公司 | Hydropower wiring planning scheme generation and adjustment method and system |
| CN113111424B (en) * | 2021-04-22 | 2022-02-22 | 贝壳找房(北京)科技有限公司 | Automatic wiring method and device, storage medium, and electronic device |
| CN114282293A (en) * | 2021-12-23 | 2022-04-05 | 贝壳找房网(北京)信息技术有限公司 | Automatic wiring method and device |
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