CN115308572A

CN115308572A - Quick charging circuit detection method and related device

Info

Publication number: CN115308572A
Application number: CN202210950444.6A
Authority: CN
Inventors: 周宁
Original assignee: Purple Light Communication Huizhou Co ltd
Current assignee: Purple Light Communication Huizhou Co ltd
Priority date: 2022-08-09
Filing date: 2022-08-09
Publication date: 2022-11-08

Abstract

The embodiment of the application discloses a quick charging circuit detection method and a related device. Wherein, the method comprises the following steps: the method comprises the steps that first equipment sends a first instruction, correspondingly, second equipment receives the first instruction, and the first instruction is used for indicating the second equipment to enter a quick charging mode; the second equipment responds to the first instruction and enters a quick charging mode; the second equipment acquires detection data of the quick charging circuit in a quick charging mode; the second equipment sends detection data to the first equipment, and correspondingly, the first equipment receives the detection data of the fast charging circuit of the second equipment in the fast charging mode; and the first equipment outputs the detection result of the quick charging circuit according to the detection data of the quick charging circuit. Therefore, by adopting the embodiment of the application, the device to be tested can enter the quick charging mode without considering the quick charging protocol supported by the device to be tested, and the universality of the test environment is improved.

Description

Quick charging circuit detection method and related device

Technical Field

The present disclosure relates to circuit detection technologies, and in particular, to a method and an apparatus for detecting a fast charging circuit.

Background

In the production of Printed Circuit Board Assemblies (PCBA), hardware testing of the PCBA is required in order to ensure that the hardware soldering of the PCBA is normal. As terminal devices supporting a fast charging function become common, a PCBA in such terminal devices needs to detect a fast charging circuit included therein.

At present, when a fast charging circuit of a terminal device supporting a fast charging function is detected, the terminal device needs to identify a fast charging protocol of a charger first, and then can enter a fast charging mode to detect the fast charging circuit. However, there are many fast charging protocols on the market, and there are differences in protocols supported by terminal devices of different companies, so that in a test environment, it is necessary to test a fast charging circuit in a terminal device by using a charger supporting a corresponding fast charging protocol for different types of terminal devices, and thus, the test environment is not universal between different terminal devices.

Disclosure of Invention

The application provides a quick charging circuit detection method and a related device, which can improve the universality of a test environment.

In a first aspect, an embodiment of the present application provides a method for detecting a fast charging circuit, where the method includes:

receiving a first instruction, wherein the first instruction is used for indicating to enter a quick charging mode;

responding to a first instruction, and entering a quick charging mode;

acquiring detection data of a quick charging circuit in a quick charging mode;

and sending the detection data to the first device.

Therefore, by adopting the embodiment of the application, the fast charging mode can be entered by initializing the fast charging interface after the first instruction is received without considering the fast charging protocol supported by the device to be tested, and the universality of the test environment is improved.

In an alternative embodiment, the method further comprises:

determining whether the universal serial bus voltage provided by the power supply equipment to the quick charging circuit is greater than or equal to the lowest working voltage of the quick charging circuit;

and if so, determining to enter a quick charging state, and executing the step of acquiring the detection data of the quick charging circuit.

In an optional implementation manner, before the detection data of the fast charge circuit is acquired, the method further includes:

and receiving a second instruction, wherein the second instruction is used for indicating to acquire the detection data of the quick charging circuit.

In an optional implementation, before receiving the first instruction, the method further includes:

receiving a third instruction, wherein the third instruction is used for indicating to close the common charging mode; the lowest working voltage of the charging circuit in the normal charging mode is less than that of the quick charging circuit in the quick charging mode;

closing the normal charging mode in response to a third instruction;

a message that the normal charging mode has been turned off is transmitted to the first device.

In an optional implementation, before receiving the third instruction, the method further includes:

receiving a fourth instruction, wherein the fourth instruction is used for indicating to enter a test mode;

in response to a fourth instruction, entering a test mode;

a message is sent to the first device that the test mode has been entered.

In an optional implementation manner, after entering the fast charge mode in response to the first instruction, the method further includes:

and sending a message that the fast charging mode is entered to the first device.

In an alternative embodiment, the method further comprises:

receiving a fifth instruction, wherein the fifth instruction is used for indicating to close the quick charging mode;

closing the quick charging mode in response to a fifth instruction;

and sending a message that the fast charging mode is closed to the first device.

In a second aspect, an embodiment of the present application provides a method for detecting a fast charging circuit, where the method includes:

sending a first instruction, wherein the first instruction is used for indicating the second equipment to enter a quick charging mode;

receiving detection data of a quick charging circuit of second equipment in a quick charging mode;

and outputting the detection result of the quick charging circuit according to the detection data of the quick charging circuit.

Therefore, by adopting the embodiment of the application, the test equipment can send the instruction for indicating to enter the quick charging mode to the equipment to be tested, so that the equipment to be tested can enter the quick charging mode without identifying the quick charging protocol supported by the equipment to be tested, and the universality of the test environment is improved.

In an alternative embodiment, the method further comprises:

and controlling the universal serial bus voltage provided by the power supply equipment to the quick charging circuit to be greater than or equal to the lowest working voltage of the quick charging circuit, and receiving detection data of the quick charging circuit of the second equipment in a quick charging mode.

In an optional implementation manner, before receiving detection data of a fast charging circuit of the second device in the fast charging mode, the method further includes:

and sending a second instruction, wherein the second instruction is used for instructing second equipment to acquire the detection data of the quick charging circuit.

In an optional embodiment, before sending the first instruction, the method further comprises:

sending a third instruction, wherein the third instruction is used for instructing the second equipment to close the ordinary charging mode, and the lowest working voltage of the charging circuit in the ordinary charging mode is smaller than the lowest working voltage of the quick charging circuit in the quick charging mode;

a message from the second device that the normal charging mode has been turned off is received.

In an optional implementation manner, before sending the third instruction, the method further includes:

sending a fourth instruction, wherein the fourth instruction is used for indicating the second equipment to enter a test mode;

a message is received from the second device that the test mode has been entered.

In an optional embodiment, after sending the first instruction, the method further comprises:

a message is received from the second device that the fast charge mode has been entered.

In an alternative embodiment, the method further comprises:

sending a fifth instruction, wherein the fifth instruction is used for instructing the second equipment to close the quick charging mode;

a message is received from the second device that the fast charge charging mode has been turned off.

In an alternative embodiment, the method further comprises:

and adjusting the universal serial bus voltage provided by the power supply equipment to the quick charging circuit to the initial voltage.

In a third aspect, an embodiment of the present application provides a device for detecting a fast charging circuit, where the device includes:

the receiving unit is used for receiving a first instruction, and the first instruction is used for indicating to enter a quick charging mode;

the processing unit is used for responding to the first instruction and entering a quick charging mode;

the acquisition unit is used for acquiring the detection data of the quick charging circuit in a quick charging mode;

and the sending unit is used for sending the detection data to the first equipment.

Optionally, for optional implementation and beneficial effects of the detection device for a fast charging circuit, reference may be made to the related contents of the first aspect, and details are not described here.

In a fourth aspect, an embodiment of the present application provides a device for detecting a fast charging circuit, where the device includes:

the sending unit is used for sending a first instruction, and the first instruction is used for indicating the second equipment to enter a quick charging mode;

the receiving unit is used for receiving detection data of the fast charging circuit of the second equipment in a fast charging mode;

and the processing unit is used for outputting the detection result of the quick charging circuit according to the detection data of the quick charging circuit.

Optionally, for alternative embodiments and advantageous effects of the detection device for a fast charging circuit, reference may be made to the related contents in the above second aspect, and details are not described here.

In a fifth aspect, an embodiment of the present application provides an apparatus, including: a processor, a memory, the processor and the memory being interconnected, wherein the memory is configured to store a computer program comprising program instructions, wherein the processor executes the program instructions to perform the steps of the method as designed by the first aspect.

In a sixth aspect, an embodiment of the present application provides an apparatus, including: a processor, a memory, the processor and the memory being interconnected, wherein the memory is configured to store a computer program comprising program instructions, wherein the processor executes the program instructions to implement the steps of the method as designed by the second aspect.

In a seventh aspect, an embodiment of the present application provides a chip, where the chip includes a processor, where the processor executes the steps in the method designed in the first aspect or the second aspect. Optionally, the chip may further include a memory and a computer program or instructions stored on the memory, and the processor executes the computer program or instructions to implement the method of the first aspect or the second aspect.

In an eighth aspect, an embodiment of the present application provides a chip module, which includes a transceiver component and a chip, where the chip includes a processor, where the processor executes the steps in the method designed in the first aspect or the second aspect. Optionally, the chip may further include a memory and a computer program or instructions stored on the memory, and the processor executes the computer program or instructions to implement the method of the first aspect or the second aspect.

In a ninth aspect, the present application provides a computer-readable storage medium, which stores a computer program, where the computer program includes program instructions, and the program instructions, when executed, implement the steps in the method designed by the first aspect or the second aspect.

In a tenth aspect, embodiments of the present application provide a computer program product, which includes a computer program or program instructions, and when executed, the computer program or program instructions implement the method of the first aspect or the second aspect.

Drawings

Fig. 1 is a schematic diagram of an architecture of a detection system for a fast charging circuit according to an embodiment of the present disclosure;

fig. 2 is a hardware block diagram of a fast charging circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a method for detecting a fast charging circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic flowchart of another fast charging circuit detection method according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a detection apparatus for a fast charging circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another detection apparatus for a fast charging circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of an apparatus provided in an embodiment of the present application.

Detailed Description

All other embodiments obtained by a person of ordinary skill in the art without making any creative effort with respect to the embodiments in the present application belong to the protection scope of the present application.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by a person skilled in the art that the embodiments described herein can be combined with other embodiments.

It should be noted that "first", "second", "third", etc. in this application are used for distinguishing similar objects and are not necessarily used for describing a particular order or sequence. Furthermore, the term "comprises" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, software, product, or apparatus that comprises a list of steps or elements is not limited to those listed but may include other steps or elements not listed or inherent to such process, method, product, or apparatus. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items.

The embodiment of the application can be applied to the production test scene of the equipment product supporting quick charging. For example, please refer to fig. 1, wherein fig. 1 is a schematic diagram of an architecture of a detection system for a fast charging circuit according to an embodiment of the present disclosure. As shown in fig. 1, the system for detecting a fast charging circuit may include a first device 101 and a second device 102, wherein the first device 101 may also be referred to as a test device, which may be a device with a test function, such as a desktop computer with a circuit testing tool, a tablet computer with a circuit testing tool, a notebook computer with a circuit testing tool, and the like, which is not limited herein. The second device 102 may also be referred to as a device under test, and may be a device supporting fast charging, such as a mobile phone supporting fast charging, a tablet computer supporting fast charging, a wearable device supporting fast charging, and the like, which is not limited herein. The apparatus configuration shown in fig. 1 is for illustration and is not to be construed as limiting the embodiments of the present application.

In an optional implementation manner, the first device 101 and the second device 102 are connected via a Universal Serial Bus (USB), and the first device 101 may output a detection result of the fast charging circuit according to received detection data of the fast charging circuit, which is obtained by the second device 102 in the fast charging mode. In this way, since data interaction is possible between the first device 101 and the second device 102 through the USB, automation of the test can be realized, and test efficiency can be improved.

In an alternative embodiment, fig. 1 may further include a power supply device, in this embodiment, the first device 101 may control the power supply device to provide a Universal Serial Bus (USB) voltage, which is greater than or less than a minimum operating voltage of a fast charging circuit in the second device 102, to the fast charging circuit, so that the second device 102 may enter a fast charging state, and may obtain detection data of the fast charging circuit. It should be noted that the first device may control the power supply device to output two paths of voltages, where the first path of voltage is used to supply power to a battery of the second device, and the second path of voltage is used to supply power to a USB of the second device (an initial voltage value of the USB is 5V).

Optionally, the fast charging circuit may include at least one fast charging chip. Optionally, the fast charging Circuit may further include an Over Voltage Protection (OVP), a Power Management Integrated Circuit (PMIC), a charging chip (charging Integrated Circuit), and a Battery (Battery). The OVP is used to provide protection for the downstream circuit from damage by excessive voltage. The PMIC is an integrated circuit for voltage conversion, voltage stabilization and battery management, can process the time sequence of a power supply system, supplies power to various loads, and can provide a protection function under the conditions of overvoltage, undervoltage, overcurrent, thermal fault and the like.

Referring to fig. 2, fig. 2 is a hardware block diagram of a fast charging circuit according to an embodiment of the present disclosure. As shown in fig. 2, it includes Battery, OVP, PMIC, charge IC, fast Charge chip (fast Charge chip a, fast Charge chip B, etc.), battery Voltage (Voltage of Battery, VBAT), charging Voltage (Voltage of Charge, vcharge), universal Serial Bus Voltage (Voltage of Universal Serial Bus, VBUS). VBAT is the aforementioned first path voltage output by the power supply device, that is, the voltage provided by the power supply device to the battery of the second device. VBUS is the second voltage output by the aforementioned power supply device, i.e. the voltage provided by the power supply device to the USB of the second device. As shown in fig. 2, the fast charging chips, such as the fast charging chip a and the fast charging chip B, are connected in parallel. When VBUS is larger than or equal to the lowest working voltage of the quick charging chips such as the quick charging chip A and the quick charging chip B, the quick charging chips such as the quick charging chip A and the quick charging chip B can normally work, so that the equipment corresponding to the quick charging circuit enters a quick charging state.

The embodiments of the present application are explained below with reference to the drawings.

Referring to fig. 3, fig. 3 is a schematic flow chart of a method for detecting a fast charging circuit according to an embodiment of the present disclosure. The method shown in fig. 3 may be used to detect the fast charging circuit shown in fig. 2, and as shown in fig. 3, the fast charging circuit detection method may include, but is not limited to, the following steps:

s301, the first device sends a first instruction, correspondingly, the second device receives the first instruction, and the first instruction is used for indicating the second device to enter a quick charging mode.

The fast charge mode refers to a charging mode that causes the second device to quickly reach or approach a fully charged state. It should be noted that the lowest operating voltage of the fast charging circuit in the fast charging mode is greater than the lowest operating voltage of the charging circuit in the normal charging mode. It will be appreciated that the length of time required for the second device to charge from 0 to 100% in the normal charging mode is greater than the length of time required for the second device to charge from 0 to 100% in the fast charging mode. That is, the charging speed in the fast charge mode is faster than that in the normal charge mode. And S302, the second equipment responds to the first instruction and enters a quick charging mode.

In an alternative embodiment, the second device, in response to the first instruction, entering the fast charge mode may include: and initializing the quick charging interface, and entering a quick charging mode.

In an optional implementation manner, after the second device enters the fast charge mode in response to the first instruction, the method further includes: and correspondingly, the first equipment receives the message of entering the quick charging mode from the second equipment. Optionally, the first device may further control the usb voltage provided by the power supply device to the fast charging circuit to be greater than or equal to the lowest operating voltage of the fast charging circuit.

And S303, the second equipment acquires the detection data of the quick charging circuit in the quick charging mode.

In an optional embodiment, the second device may further determine whether the universal serial bus voltage provided by the power supply device to the fast charging circuit is greater than or equal to the lowest operating voltage of the fast charging circuit; and if so, determining to enter a quick charging state, and executing the step of acquiring the detection data of the quick charging circuit.

In an optional implementation manner, before the second device obtains the detection data of the fast charging circuit, the method further includes: and receiving a second instruction, and correspondingly, sending the second instruction by the first equipment, wherein the second instruction is used for instructing the second equipment to acquire the detection data of the quick charging circuit.

S304, the second device sends the detection data of the quick charging circuit to the first device, and correspondingly, the first device receives the detection data of the quick charging circuit of the second device in the quick charging mode.

And S305, outputting a detection result of the quick charging circuit by the first equipment according to the detection data of the quick charging circuit.

The detection data of the quick charging circuit comprises the output current value of each quick charging chip in at least one quick charging chip.

In an optional implementation manner, the outputting, by the first device, the detection result of the fast charge circuit according to the detection data of the fast charge circuit may include: and outputting the detection result of the quick charging circuit according to the output current value and the target current threshold of each quick charging chip.

Optionally, the target current threshold includes a first current threshold, and the outputting, by the first device, the detection result of the fast charging circuit according to the output current value of each fast charging chip and the target current threshold may include: if the sum of the output current values of each quick charging chip is greater than or equal to the first current threshold, outputting the detection result of the quick charging circuit as passing detection; and if the sum of the output current values of each quick charging chip is smaller than the first current threshold, outputting the detection result of the quick charging chip as failed detection.

For example, if the first current threshold is 15 amperes (a), one fast charging circuit includes 5 fast charging chips, and if the output current values of the 5 fast charging chips are 2A, 5A, 3A, 4A, and 1A, respectively, the sum of the current values of the 5 fast charging chips (2 +5+3+4+1= 15a) is equal to the first current threshold, then the detection result of the fast charging circuit is output as a pass detection. If the output current values of the 5 fast charging chips are 2A, 4A, 3A and 1A respectively, the sum of the current values of the 5 fast charging chips (2 +4+3+ 1= 13a) is smaller than the first current threshold value and equal, and then the detection result of the fast charging circuit is output as a non-passing detection.

Optionally, the target current threshold comprises a second current threshold, and the second current threshold is smaller than the first current threshold. The first device outputs a detection result of the fast charging circuit according to the output current value and the target current threshold of each fast charging chip, and may include: if the output current value of each quick charge chip is greater than or equal to the second current threshold value, outputting the detection result of the quick charge circuit as pass detection; and if the output current value of any one quick charging chip is smaller than the second current threshold value, outputting the detection result of the quick charging chip as failed detection. In this way, the first device can confirm the hardware welding quality of each fast charging chip according to the relationship between the output current of each fast charging chip and the second current threshold value.

For example, assuming that the second current threshold is 3A, one fast charge circuit includes 5 fast charge chips, and if the output current values of the 5 fast charge chips are 4A, 5A, 6A, 4A and 3A, respectively, since the output current value of each of the 5 fast charge chips is greater than or equal to the second current threshold (3A), the detection result of the fast charge circuit is output as a pass detection. If the output current values of the 5 fast charging chips are 2A, 5A, 6A, 4A and 3A respectively, and the current value of one fast charging chip is 2A and is smaller than the second current threshold (3A), the detection result of the fast charging circuit is output as failed detection.

In another optional implementation, the first device may output the detection result of the fast charging circuit according to the detection data of the fast charging circuit and the input data of the fast charging circuit; the detection data of the quick charging circuit comprises an output current value and an output voltage value of each quick charging chip in at least one quick charging chip; the input data of the quick charging circuit comprises an input voltage value and an input current value of each quick charging chip in at least one quick charging chip. Optionally, in this embodiment, the first device further obtains input data of the fast charging circuit. Optionally, the first device outputs the detection result of the fast charging circuit according to the detection data of the fast charging circuit and the input data of the fast charging circuit, and the method may include: if the product of the output voltage value and the output current value of each quick charge chip is equal to the product of the input current value and the input voltage value of the quick charge chip, outputting the detection result of the quick charge circuit as pass detection; and if the product of the output voltage value and the output current value of any one quick charge chip is not equal to the product of the input current value and the input voltage value of the quick charge chip, outputting the detection result of the quick charge circuit as failed detection.

For example, if a fast charging circuit includes 5 fast charging chips, an input voltage of one of the fast charging chips is 10 volts (V), an input current of the fast charging chip is 1A, an output voltage of the fast charging chip is 5V, and an output current of the fast charging chip is 3A, since input power (10 × 1=10 watts (W)) is not equal to output power (5 × 3= 15w), a detection result of the output fast charging circuit is a failed detection.

It can be understood that, if the detection result of the fast charging circuit is that the detection is passed, it indicates that each fast charging chip can normally operate, thereby indicating that the fast charging function of the second device is normal. That is, the second device can be charged quickly.

Optionally, the detection data of the fast charging circuit may further include the number of the fast charging chips.

In the embodiment of the application, the first equipment sends a first instruction to indicate the second equipment to enter a quick charging mode; the second equipment responds to the first instruction to enter a quick charging mode; the second equipment acquires detection data of the quick charging circuit in a quick charging mode; the second equipment sends the detection data of the quick charging circuit to the first equipment; therefore, the first equipment can output the detection result of the quick charging circuit according to the detection data sent by the second equipment. Therefore, by adopting the embodiment of the application, the fast charging protocol supported by the device to be tested (namely the second device) does not need to be considered, the fast charging mode can be entered by initializing the fast charging interface after the first instruction is received, the universality of the test environment is improved, and the test cost can be saved.

Referring to fig. 4, fig. 4 is a schematic flow chart of another method for detecting a fast charge circuit according to an embodiment of the present disclosure. In the method for detecting a fast charging circuit shown in fig. 4, the first device further sends a third instruction to the second device, instructing the second device to close the normal charging mode. And the first equipment also sends a fourth instruction to the second equipment before sending the third instruction to the second equipment, and the fourth instruction instructs the second equipment to enter the test mode. As shown in fig. 4, the method for detecting a fast charging circuit includes, but is not limited to, the following steps:

s401, the first device sends a fourth instruction, correspondingly, the second device receives the fourth instruction, and the fourth instruction is used for indicating the second device to enter a test mode.

S402, the second device responds to the fourth instruction and enters a test mode.

S403, the second device sends a message that the first device has entered the test mode to the first device, and correspondingly, the first device receives the message that the second device has entered the test mode.

S404, the first device sends a third instruction, and correspondingly, the second device receives the third instruction, where the third instruction is used to instruct the second device to close the normal charging mode.

The lowest working voltage of the charging circuit in the ordinary charging mode is lower than that of the quick charging circuit in the quick charging mode. Therefore, the first device instructs the second device to close the ordinary charging mode, and loss of the ordinary charging chip caused by overlarge subsequent charging voltage can be avoided.

It should be noted that the lowest operating voltage of the charging circuit in the normal charging mode refers to the lowest operating voltage of each of at least one normal charging chip included in the normal charging circuit. The lowest working voltage of the quick charging circuit refers to the lowest working voltage of each quick charging chip in at least one quick charging chip included in the quick charging circuit.

And S405, the second equipment responds to a third instruction, and closes the common charging mode.

S406, the second device sends a message to the first device, where the normal charging mode is closed, and correspondingly, the first device receives the message from the second device, where the normal charging mode is closed.

And S407, the first device sends a first instruction, and correspondingly, the second device receives the first instruction, wherein the first instruction is used for indicating the second device to enter a quick charging mode.

And S408, the second equipment responds to the first instruction and enters a quick charging mode.

S409, the second device sends a message that the first device has entered the fast charging mode to the first device, and correspondingly, the first device receives a message that the second device has entered the fast charging mode.

In the embodiment of the application, the first device receives the message from the second device that the fast charging mode has been entered, which is beneficial for the first device to definitely know when the universal serial bus voltage provided by the power supply device to the fast charging circuit is raised to the lowest working voltage of the fast charging chip.

And S410, the first device controls the universal serial bus voltage provided by the power supply device to the quick-charging circuit to be greater than or equal to the lowest working voltage of the quick-charging circuit.

As can be seen from the foregoing, the lowest operating voltage of the fast charging circuit refers to the lowest operating voltage of each fast charging chip in at least one fast charging chip included in the fast charging circuit. Therefore, the universal serial bus voltage provided by the first device control power supply device to the quick-charging circuit is greater than or equal to the lowest working voltage of the quick-charging circuit, that is, the universal serial bus voltage provided by the first device control power supply device to the quick-charging circuit is greater than or equal to the lowest working voltage of each quick-charging chip.

Alternatively, when the second device detects that the universal serial bus voltage provided by the power supply device to the fast charging circuit is greater than or equal to the lowest operating voltage of the fast charging circuit, the second device may enter a fast charging state and perform step S411.

Taking the fast charging circuit shown in fig. 2 as an example, assuming that the minimum operating voltages of the fast charging chips, such as the fast charging chip a and the fast charging chip B, are all 8.5V, the first device needs to control the second path of voltage (i.e., VBUS in fig. 2) output by the power supply device to be increased from the initial voltage value (5V) to 8.5V. Namely, the first device controls the universal serial bus voltage provided by the power supply device to the quick-charging circuit to be greater than or equal to the lowest working voltage of the quick-charging circuit. Therefore, when the second device determines that VBUS is greater than or equal to the lowest working voltage of the quick charging chip A and the quick charging chip B, the second device determines to enter a quick charging state.

S411, the first device sends a second instruction, and correspondingly, the second device receives the second instruction, wherein the second instruction is used for instructing the second device to acquire detection data of the quick charging circuit.

And S412, the second device responds to the second instruction to acquire the detection data of the quick charging circuit.

S413, the second device sends the detection data of the fast charging circuit to the first device, and correspondingly, the first device receives the detection data of the fast charging circuit from the second device.

And S414, the first device outputs the detection result of the quick charging circuit according to the detection data of the quick charging circuit.

In an alternative embodiment, the implementation process of step S414 can refer to the description in step S305, and is not described herein again.

In an optional embodiment, after step S414, steps S415 to S418 may be further included.

S415, the first device sends a fifth instruction, and correspondingly, the second device receives the fifth instruction, where the fifth instruction is used to instruct the second device to close the fast charging mode.

And S416, the second equipment responds to a fifth instruction, and closes the quick charging mode.

S417, the second device sends a message that the fast charging mode has been closed to the first device, and correspondingly, the first device receives the message that the fast charging mode has been closed from the second device.

And S418, the first device adjusts the universal serial bus voltage provided by the power supply device to the quick charging circuit to an initial voltage. In this way, it is facilitated for the first device to perform further tests.

Therefore, by adopting the embodiment of the application, the device to be tested (namely, the second device) can definitely know when to enter the test mode according to the received fourth instruction, so that the test device (namely, the first device) can timely detect the quick charging circuit; after the device to be tested receives the third instruction, the common charging mode can be closed, so that the loss of the common charging chip caused by overlarge charging voltage in the quick charging mode can be avoided, and the device to be tested also sends a message of closing the common charging mode to the testing device, so that the testing device can definitely know when the USB voltage supplied to the quick charging circuit by the power supply device is lifted to the lowest working voltage of the quick charging chip, the device to be tested can timely enter the quick charging state, and the detection data of the quick charging circuit can be acquired.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a detection device of a fast charging circuit according to an embodiment of the present disclosure. As shown in fig. 5, the fast charging circuit detection device may include, but is not limited to:

a receiving unit 501, configured to receive a first instruction, where the first instruction is used to instruct to enter a fast charging mode;

a processing unit 502, configured to enter a fast charging mode in response to a first instruction from a first device;

an obtaining unit 503, configured to obtain detection data of the fast charging circuit in the fast charging mode;

a sending unit 504, configured to send the detection data to the first device.

In an optional implementation manner, the detection apparatus for a fast charging circuit further includes:

a determining unit 505, configured to determine whether a universal serial bus voltage provided by the power supply device to the fast charging circuit is greater than or equal to a lowest operating voltage of the fast charging circuit; and if so, determining to enter a quick charging state, and executing the step of acquiring the detection data of the quick charging circuit.

In an alternative embodiment, before the obtaining unit 503 obtains the detection data of the fast charging circuit, the receiving unit 501 further receives a second instruction, where the second instruction is used to instruct to obtain the detection data of the fast charging circuit.

In an optional implementation manner, the receiving unit 501 is further configured to receive a third instruction before being configured to receive the first instruction, where the third instruction is configured to instruct to turn off the normal charging mode; the lowest working voltage of the charging circuit in the normal charging mode is less than that of the quick charging circuit in the quick charging mode;

the processing unit 502 is further configured to close the normal charging mode in response to a third instruction;

the sending unit 504 is further configured to send a message that the normal charging mode is turned off to the first device.

In an alternative embodiment, the receiving unit 501 is further configured to receive a fourth instruction before being configured to receive the third instruction, where the fourth instruction is configured to instruct to enter the test mode;

the processing unit 502 is further configured to enter a test mode in response to the fourth instruction;

the sending unit 504 is further configured to send a message that the test mode has been entered to the first device.

In an alternative embodiment, after the processing unit 502 enters the fast charge mode in response to the first instruction, the sending unit 504 is further configured to send a message that the fast charge mode has been entered to the first device.

In an optional implementation manner, the receiving unit 501 is further configured to receive a fifth instruction, where the fifth instruction is used to instruct to close the fast charging mode;

the processing unit 502 is further configured to close the fast charging mode in response to a fifth instruction;

the sending unit 504 is further configured to send a message that the fast charging mode is turned off to the first device.

It can be understood that specific implementation and achievable beneficial effects of each unit in the detection device for the fast charging circuit provided in the embodiment of the present application may refer to the description of any embodiment of the detection method for the fast charging circuit, and are not described herein again.

Referring to fig. 6, fig. 6 is a schematic structural diagram of another detection device for a fast charging circuit according to an embodiment of the present disclosure.

As shown in fig. 6, the fast charging circuit detection device may include, but is not limited to:

a sending unit 601, configured to send a first instruction, where the first instruction is used to instruct a second device to enter a fast charging mode;

a receiving unit 602, configured to receive detection data of a fast charging circuit of a second device in a fast charging mode;

the processing unit 603 is configured to output a detection result of the fast charging circuit according to the detection data of the fast charging circuit.

In an optional embodiment, the fast charging circuit detection device further includes a control unit 604.

The control unit 604 is configured to control the usb voltage provided by the power supply device to the fast charging circuit to be greater than or equal to the lowest operating voltage of the fast charging circuit.

In an optional implementation manner, before the receiving unit 602 receives the detection data of the fast charging circuit of the second device in the fast charging mode, the sending unit 601 is further configured to send a second instruction, where the second instruction is used to instruct the second device to obtain the detection data of the fast charging circuit.

In an optional embodiment, before the sending unit 601 is configured to send the first instruction, the sending unit is further configured to send a third instruction, where the third instruction is used to instruct the second device to turn off the normal charging mode, and a lowest operating voltage of the charging circuit in the normal charging mode is lower than a lowest operating voltage of the fast charging circuit in the fast charging mode;

the receiving unit 602 is further configured to receive a message from the second device that the normal charging mode is turned off.

In an alternative embodiment, the sending unit 601 is further configured to send a fourth instruction before being configured to send the third instruction, where the fourth instruction is configured to instruct the second device to enter the test mode;

the receiving unit 602 is further configured to receive a message from the second device that the test mode has been entered.

In an optional implementation manner, after the sending unit 601 sends the first instruction, the receiving unit 602 is further configured to receive a message from the second device that the fast charging mode has been entered.

In an optional implementation manner, the sending unit 601 is further configured to send a fifth instruction, where the fifth instruction is used to instruct the second device to close the fast charging mode;

the receiving unit 602 is further configured to receive a message from the second device that the fast charging mode is turned off.

In an alternative embodiment, the control unit 604 is further configured to adjust the usb voltage provided by the power supply device to the fast charging circuit to the initial voltage.

Referring to fig. 7, fig. 7 is a schematic structural diagram of an apparatus according to an embodiment of the present disclosure. The device comprises a processor 701, a transceiver 703 and a memory 702. The processor 701 and the memory 702 are connected by one or more communication buses.

The transceiver 703 is used for transmitting data or receiving data.

The memory 702 is used for storing commands or computer programs, the memory 702 includes, but is not limited to, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a portable read-only memory (CD-ROM), and the memory 702 is used for storing executed program codes and transmitted data and providing commands and data to the processor 701. A portion of the memory 702 may also include non-volatile random access memory.

The Processor 701 may be a Central Processing Unit (CPU), and the Processor 701 may also be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor, and optionally, the processor 701 may be any conventional processor or the like.

In an alternative embodiment, the device may be the second device described above. The processor 701 may be used to execute computer programs or commands stored by the memory 702 to cause the apparatus to perform:

entering a fast charging mode in response to a first instruction from a first device;

acquiring detection data of a quick charging circuit in a quick charging mode;

and sending the detection data to the first device.

In this embodiment, the processor 701 is further configured to determine whether the universal serial bus voltage provided by the power supply device to the fast charging circuit is greater than or equal to the lowest operating voltage of the fast charging circuit; and if so, determining to enter a quick charging state, and executing the step of acquiring the detection data of the quick charging circuit.

In this embodiment, before being used to obtain the detection data of the fast charging circuit, the processor 701 is further configured to:

In this embodiment, the processor 701, before being configured to receive the first instruction, is further configured to:

closing the normal charging mode in response to a third instruction;

a message is sent to the first device that the normal charging mode has been turned off.

In this embodiment, before being configured to receive the third instruction, the processor 701 is further configured to:

entering a test mode in response to the fourth instruction;

a message is sent to the first device that the test mode has been entered.

In this embodiment, after the processor 701 is configured to enter the fast charge mode in response to the first instruction, the processor is further configured to:

In this embodiment, the processor 701 is further configured to:

closing the quick charging mode in response to a fifth instruction;

In another alternative embodiment, the device may be the first device described above. The processor 701 may be used to execute computer programs or commands stored by the memory 702 to cause the apparatus to perform:

In this embodiment, the processor 701 is further configured to control the usb voltage provided by the power supply device to the fast charging circuit to be greater than or equal to the lowest operating voltage of the fast charging circuit.

In this embodiment, before being configured to receive the detection data of the fast charging circuit of the second device in the fast charging mode, the processor 701 is further configured to:

In this embodiment, before being configured to send the first instruction, the processor 701 is further configured to:

In this embodiment, before being configured to send the third instruction, the processor 701 is further configured to:

In this embodiment, after being configured to send the first instruction, the processor 701 is further configured to:

In this embodiment, the processor 701 is further configured to:

In this embodiment, the processor 701 is further configured to adjust the usb voltage provided by the power supply device to the fast charging circuit to the initial voltage.

It is to be understood that for specific implementation and beneficial effects of the processor 701, reference may be made to the description of the foregoing embodiment of the method for detecting a fast charging circuit, and details are not described herein again.

The embodiment of the present application further provides a chip, where the chip includes a processor, and the processor executes the steps described in the foregoing method embodiment. Optionally, the chip may further include a processor, a memory, and a computer program or instructions stored on the memory, wherein the processor executes the computer program or instructions to implement the steps described in the above method embodiments.

The embodiment of the present application further provides a chip module, which includes a transceiver component and a chip, where the chip includes a processor, and the processor executes the steps described in the foregoing method embodiments. Optionally, the chip may further include a memory and a computer program or instructions stored on the memory, and the processor executes the computer program or instructions to implement the steps described in the above method embodiments.

Embodiments of the present application also provide a computer-readable storage medium, which stores a computer program or instructions, and when the computer program or instructions are executed, the steps described in the above method embodiments are implemented.

Embodiments of the present application further provide a computer program product, which includes a computer program or instructions, and when executed, the computer program or instructions implement the steps described in the above method embodiments.

Each device and product described in the above embodiments includes modules/units, which may be software modules/units, or hardware modules/units, or may be partly software modules/units and partly hardware modules/units. For example, for each device and product of an application or integrated chip, each module/unit included in the application or integrated chip may all be implemented in a hardware manner such as a circuit, or at least a part of the modules/units may be implemented in a software program, which runs on an integrated processor inside the chip, and the remaining part of the modules/units may be implemented in a hardware manner such as a circuit; for each device and product corresponding to or integrating a chip module, each module/unit included in the device and product may be implemented in a hardware manner such as a circuit, different modules/units may be located in the same piece (e.g., a chip, a circuit module, etc.) or different components of the chip module, at least part of/units may be implemented in a software program manner, and the remaining part of the module/unit of the integrated processor running inside the chip module may be implemented in a hardware manner such as a circuit; for each device or product corresponding to or integrating the terminal, the modules/units included in the device or product may all be implemented by hardware such as circuits, different modules/units may be located in the same component (e.g., chip, circuit module, etc.) or different components in the terminal, or at least some of the modules/units may be implemented by software programs, the programs run on a processor integrated in the terminal, and the remaining sub-modules/units may be implemented by hardware such as circuits.

The steps of a method or algorithm described in the embodiments of the present application may be implemented in hardware, or may be implemented by a processor executing software instructions. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash memory, read-only memory (ROM), erasable Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a compact disc read only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). In addition, the ASIC may reside in a terminal device or a network device. Of course, the processor and the storage medium may reside as discrete components in a terminal device or a network device.

Those skilled in the art will appreciate that in one or more of the examples described above, the functionality described in the embodiments of the present application may be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

The above-mentioned embodiments are further described in detail for the purpose, technical solutions and advantages of the embodiments of the present application, and it should be understood that the above-mentioned embodiments are only specific for the embodiments of the present application, and are not intended to limit the scope of the embodiments of the present application, and any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims

1. A method for detecting a fast charging circuit is characterized by comprising the following steps:

responding to the first instruction, and entering the quick charging mode;

acquiring detection data of a quick charging circuit in the quick charging mode;

and sending the detection data to the first equipment.

2. The method of claim 1, further comprising:

determining whether a universal serial bus voltage provided by a power supply device to the quick charging circuit is greater than or equal to the lowest working voltage of the quick charging circuit;

3. The method of claim 2, wherein prior to obtaining the detection data of the fast charge circuit, the method further comprises:

4. The method of claim 1, wherein prior to receiving the first instruction, the method further comprises:

receiving a third instruction, wherein the third instruction is used for indicating that the common charging mode is closed; the lowest working voltage of the charging circuit in the ordinary charging mode is lower than the lowest working voltage of the quick charging circuit in the quick charging mode;

turning off the normal charging mode in response to the third instruction;

sending a message to the first device that the normal charging mode has been turned off.

5. The method of claim 4, wherein prior to receiving the third instruction, the method further comprises:

entering the test mode in response to the fourth instruction;

sending a message to the first device that the test mode has been entered.

6. The method of claim 1, wherein after entering a fast charge mode in response to the first instruction, the method further comprises:

7. The method of any of claims 1 to 6, further comprising:

receiving a fifth instruction, wherein the fifth instruction is used for instructing to close the quick charging mode;

closing the quick charging mode in response to the fifth instruction;

and sending a message that the quick charging mode is closed to the first equipment.

8. A method for detecting a fast charging circuit is characterized by comprising the following steps:

sending a first instruction, wherein the first instruction is used for indicating second equipment to enter a quick charging mode;

receiving detection data of a quick charging circuit of the second equipment in the quick charging mode;

9. The method of claim 8, further comprising:

and controlling the universal serial bus voltage provided by the power supply equipment to the quick charging circuit to be greater than or equal to the lowest working voltage of the quick charging circuit.

10. The method of claim 9, wherein prior to receiving the detection data of the second device during the fast charge mode, the method further comprises:

11. The method of claim 8, wherein prior to sending the first instruction, the method further comprises:

sending a third instruction, wherein the third instruction is used for instructing second equipment to close a common charging mode, and the lowest working voltage of a charging circuit in the common charging mode is smaller than the lowest working voltage of a quick charging circuit in the quick charging mode;

receiving a message from the second device that the normal charging mode has been turned off.

12. The method of claim 8, wherein prior to sending the third instruction, the method further comprises:

sending a fourth instruction, wherein the fourth instruction is used for instructing the second equipment to enter a test mode;

receiving a message from the second device that the test mode has been entered.

13. The method of claim 8, wherein after the sending the first instruction, the method further comprises:

receiving a message from the second device that the fast charge mode has been entered.

14. The method of any one of claims 8 to 13, further comprising:

sending a fifth instruction, where the fifth instruction is used to instruct the second device to close a fast charging mode;

receiving a message from the second device that the fast charge mode has been turned off.

15. The method of claim 14, further comprising:

and adjusting the universal serial bus voltage provided by the power supply equipment to the quick charging circuit to an initial voltage.

16. A quick charge circuit detection device, the device comprising:

the processing unit is used for responding to a first instruction from first equipment and entering the quick charging mode;

the acquisition unit is used for acquiring the detection data of the quick charging circuit in the quick charging mode;

17. The utility model provides a fill charging circuit detection device soon which characterized in that, the device includes:

the device comprises a sending unit, a receiving unit and a processing unit, wherein the sending unit is used for sending a first instruction, and the first instruction is used for indicating the second equipment to enter a quick charging mode;

the receiving unit is used for receiving detection data of a quick charging circuit of the second equipment in the quick charging mode;

18. An apparatus comprising a processor and a memory, the processor and the memory being interconnected, wherein the memory is configured to store a computer program comprising program instructions, the processor being configured to invoke the program instructions to perform the rapid charge circuit detection method of any of claims 1 to 7, or to perform the rapid charge circuit detection method of any of claims 8 to 15.

19. A computer-readable storage medium, characterized in that it stores a computer program comprising program instructions that, when executed by a processor, cause the processor to carry out the method of detection of a fast charge circuit according to any one of claims 1 to 7, or cause the processor to carry out the method of detection of a fast charge circuit according to any one of claims 8 to 15.

20. A chip comprising a processor that performs the method of detecting a fast charge circuit of any of claims 1 to 7 or the method of detecting a fast charge circuit of any of claims 8 to 15.

21. A chip module, wherein the chip module comprises a transceiver component and a chip, and the chip comprises a processor, and the processor performs the method for detecting a fast charging circuit according to any one of claims 1 to 7, or performs the method for detecting a fast charging circuit according to any one of claims 8 to 15.