CN115308489A - Patch electronic element impedance measurement method based on simulation and de-embedding technology - Google Patents
Patch electronic element impedance measurement method based on simulation and de-embedding technology Download PDFInfo
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- CN115308489A CN115308489A CN202210868329.4A CN202210868329A CN115308489A CN 115308489 A CN115308489 A CN 115308489A CN 202210868329 A CN202210868329 A CN 202210868329A CN 115308489 A CN115308489 A CN 115308489A
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- 238000002847 impedance measurement Methods 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004088 simulation Methods 0.000 title claims abstract description 26
- 238000005516 engineering process Methods 0.000 title claims abstract description 14
- 238000012360 testing method Methods 0.000 claims abstract description 29
- 238000005259 measurement Methods 0.000 claims abstract description 10
- 238000012805 post-processing Methods 0.000 claims abstract description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000008878 coupling Effects 0.000 abstract description 4
- 238000010168 coupling process Methods 0.000 abstract description 4
- 238000005859 coupling reaction Methods 0.000 abstract description 4
- 238000000605 extraction Methods 0.000 abstract description 4
- 230000007246 mechanism Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 239000000523 sample Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000005284 excitation Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
Abstract
The invention discloses a patch electronic element impedance measuring method based on simulation and de-embedding technologies, which comprises the steps of firstly designing three types of impedance test PCBs (printed circuit boards), and carrying out full-wave simulation on the impedance test PCBs to obtain a network parameter file; after the impedance measurement PCB is manufactured, the embedding removing technology is used for realizing that the calibration surface extends from the coaxial end surface to the measurement end surface; and then, a vector network analyzer is adopted to perform embedded measurement to obtain an S parameter file, and the S parameter file is subjected to post-processing to obtain the impedance of the surface mount electronic element. The method has the advantages that the impedance of the patch electronic element can be measured only by using the vector network analyzer, the coaxial cable and the calibration piece without an impedance measurement probe worktable and the calibration piece (sheet) of the patch electronic element. The invention is suitable for measuring the impedance of the patch electronic element and has wide application range. The invention has important effect on the extraction of the parasitic parameters of the circuit and the element of the circuit board and the analysis of the electromagnetic interference coupling mechanism.
Description
Technical Field
The invention relates to the technical field of radio frequency microwave and electromagnetic compatibility, in particular to a patch electronic element impedance measuring method based on simulation and de-embedding technology.
Background
The printed circuit board comprises a microstrip line, a discrete component, an Integrated Circuit (IC) chip and the like, the coupling mechanism of electromagnetic interference to the printed circuit board is that when the circuit works at a higher frequency, parasitic parameters exist in a conducting wire, a printed circuit board wiring, a component lead and the like, the parasitic parameters provide a path for electromagnetic interference noise on an interference coupling path and greatly influence the anti-electromagnetic interference performance of equipment, therefore, the electromagnetic interference coupling mechanism is researched to model the electromagnetic interference path, and firstly, the impedance parameters of a device need to be accurately extracted to establish a high-frequency model of the device. In the prior art, in order to reduce the parasitic parameters of the lead, the elements of the circuit are generally selected from patch elements, and the smaller the package size is, the smaller the parasitic parameters are. But parasitic parameter extraction of the patch element is difficult due to its small size, no leads, and non-coaxial devices.
Disclosure of Invention
The invention aims to provide a patch electronic element impedance measuring method based on simulation and de-embedding technology, aiming at the problem that the parasitic parameter extraction of a patch element in the background technology is difficult in impedance extraction due to small size, no lead and non-coaxial devices; this patent paster electronic component mainly be passive paster electronic component, specifically be the chip resistor, electric capacity and the inductance of two pins.
The technical scheme of the invention is that the impedance measurement method of the patch electronic element based on the simulation and de-embedding technology comprises the steps of 1, respectively designing a reflection type impedance measurement PCB, a series through type impedance measurement PCB and a parallel through type impedance measurement PCB; and estimating the impedance value of the measured patch element and selecting a proper impedance to measure the PCB.
And 2, performing three-dimensional modeling on the reflection-type impedance measurement PCB, the series-connection through-type impedance measurement PCB, the parallel-connection through-type impedance measurement PCB and a connector (such as an SMA connector) thereof by using simulation software, and performing full-wave simulation on the models to obtain a network parameter file (such as an snp file) of the impedance measurement PCB.
And 3, manufacturing the reflection-type impedance measurement PCB, the series-connection through-type impedance measurement PCB and the parallel-connection through-type impedance measurement PCB, and selecting a proper impedance measurement PCB according to the estimated impedance of the patch element.
And 4, calibrating the coaxial cable for measurement by using the vector network analyzer and the calibration piece, wherein the reference plane is positioned on the end face of the tail end of the coaxial cable connector after calibration.
And 5, using a vector network analyzer and the network parameter file (such as a snp file) obtained by the simulation in the step 2 to perform de-embedding test on the impedance measurement PCB provided with the patch element, and acquiring test data such as S parameters.
And 6, carrying out post-processing on the test data obtained by the embedding test of the vector network analyzer to obtain the impedance parameters of the surface mount element.
The impedance measurement PCB in the step 1 comprises three types, respectively: the schematic diagrams of the designed impedance measurement PCB are shown in FIGS. 2, 3 and 4.
The method for selecting a suitable impedance measurement PCB board according to the estimated patch element impedance value in step 1 is applied with reference to the agilent impedance measurement method, and is specifically shown in fig. 5.
The specific method for modeling the impedance measurement PCB by using the simulation software in the step 2 is to import the engineering file of the PCB into the simulation software to perform three-dimensional modeling, and perform three-dimensional modeling on the connector. And acquiring a network parameter file between the excitation port of the coaxial connector in the model and the front end of the patch element on the impedance measurement PCB by performing full-wave simulation on the established model, and providing a necessary file for extension of a calibration plane in the process of realizing de-embedding measurement.
Compared with the prior art, the invention has the following beneficial technical effects:
1. the invention designs three types of impedance test PCBs, and performs full-wave simulation on the impedance test PCBs to obtain a network parameter file; after the impedance measurement PCB is manufactured, the embedding removing technology is used for realizing that the calibration surface extends from the coaxial end surface to the measurement end surface; and using a vector network analyzer with high popularity rate, a coaxial calibration piece and other instrument equipment, acquiring a network parameter file of the impedance measurement PCB by using full-wave simulation, performing de-embedding test on the PCB impedance measurement board provided with the patch element, and performing post-processing on the data obtained by the test to obtain the impedance parameter of the patch element.
2. The invention has the advantages of less used instruments, simple test configuration and more accurate test result.
Drawings
FIG. 1 is a flow chart of a method of measuring impedance of a patch electronic component based on simulation and de-embedding techniques of the present invention;
FIG. 2 is a schematic diagram of a reflection type impedance measurement PCB of the patch electronic component of the present invention;
FIG. 3 is a schematic diagram of a parallel connection through type impedance measurement PCB of the patch electronic component of the present invention;
FIG. 4 is a schematic diagram of a PCB board for measuring the series-connected through-type impedance of the chip electronic component of the present invention;
FIG. 5 is a diagram of a method for selecting a suitable impedance measurement PCB based on the estimated impedance for use in the present invention;
FIG. 6 is a graph of reflective impedance measurement PCB and SMA modeling of the invention using ANSYS HFSS;
FIG. 7 is a schematic diagram of the present invention showing the impedance testing of a surface mount electronic component using a vector network analyzer and a reflective impedance measurement PCB board;
FIG. 8 is a comparison graph of impedance parameters resulting from post-processing of test data according to the present invention.
Detailed Description
A patch electronic element impedance measurement method based on simulation and de-embedding technology comprises the following steps:
Selecting a reflection type impedance measurement PCB within the range of 0.1-1000 omega of impedance value; selecting a series-connection through-type impedance measurement PCB within the impedance value range of 1-500 k omega; and selecting a parallel through type impedance measurement PCB within the range of 1m omega-50 omega of impedance value.
The characteristic impedance of the microstrip line on the impedance measurement PCB board is 50 omega, and is consistent with the characteristic impedance of a vector network analyzer of a test instrument and a coaxial cable.
And 2, performing three-dimensional modeling on the impedance measurement PCB and the SMA connector by using simulation software, performing full-wave simulation on the impedance measurement PCB and the SMA connector, acquiring network parameters between an excitation port of the coaxial connector in the established model and the front end of a patch element on the impedance measurement PCB, and preparing for extension of a calibration reference plane during impedance measurement.
And 3, manufacturing the reflection-type impedance measurement PCB, the series-connection through-type impedance measurement PCB or the parallel-connection through-type impedance measurement PCB, and welding and installing the device and the connector according to the estimated impedance of the patch element.
And 4, calibrating the coaxial cable for measurement and instrument equipment by using the vector network analyzer and the coaxial calibration piece, wherein the calibration plane is positioned on the end face of the tail end of the coaxial cable connector after calibration. If the reflecting impedance measurement PCB is selected, calibrating the single-port Short-Open-Load; and if the series-Through impedance measurement PCB or the parallel-Through impedance measurement PCB is selected, the calibration is carried out for the double-port Short-Open-Load-Through calibration.
And 5, using the calibrated vector network analyzer and the coaxial cable as test instrument equipment, and performing de-embedding test on the impedance measurement PCB provided with the patch element by adopting the network parameter file (such as a snp file) obtained by the simulation in the step 2 to obtain S parameter test data.
Selecting S11 parameters if a reflection-type impedance measurement PCB is selected; and if the series through type impedance measurement PCB or the parallel through type impedance measurement PCB is selected, selecting S21 parameters.
And 6, carrying out post-processing on the test data obtained by the embedding test of the vector network analyzer, and obtaining the impedance parameters of the surface mounted element.
The measured patch element with a medium impedance value was measured by using a reflectometry method, and the conversion relationship between the impedance and S11 was:
Z dut ＝50×(1+S11)/(1-S11) (1)
the conversion relation between the impedance and S21 of the tested patch element with medium to large impedance value is measured by using the series direct connection method:
Z dut ＝50×2×(1-S21)/S21 (2)
and (3) measuring the tested patch element with a very small impedance value by using a parallel through method, wherein the conversion relation of the impedance and S21 is as follows:
Z dut ＝50×S21/(2×(1-S21)) (3)
the process of the invention is further illustrated below with reference to specific examples:
example 1
The capacitance value tested was 22nF, the package was 0603, the model number GRM033B10J223KE01, and the brand name is the parasitic parameter of the muRata capacitor.
And 3, selecting a reflection type impedance measurement PCB as a measurement board according to the estimated patch element impedance 22nF patch capacitance impedance, and carrying out welding installation on the device and the connector.
And 4, performing single-port Short-Open-Load calibration on the reflection type impedance measurement PCB by using the vector network analyzer and the coaxial calibration piece, wherein the reference plane after calibration is positioned on the end face of the tail end of the coaxial cable connector, such as the surface A shown in fig. 7.
And 5, using the calibrated vector network analyzer and the coaxial cable as test instrument equipment, and performing de-embedding test on the impedance measurement PCB provided with the patch element by adopting the network file (such as a snp file) obtained by the simulation in the step 2 to obtain S parameter test data.
And 6, post-processing the test data obtained by the embedding test of the vector network analyzer, wherein S11 parameters are selected when the PCB is measured by using the reflection impedance, and the formula (1) is selected as parameters for calculating the impedance of the surface mount device electronic element, as shown in fig. 8.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited thereto, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (7)
1. A patch electronic element impedance measurement method based on simulation and de-embedding technology is characterized by comprising the following specific steps:
s1, designing a reflection-type impedance measurement PCB, a series-connection through-type impedance measurement PCB and a parallel-connection through-type impedance measurement PCB respectively; estimating the impedance value of the measured patch element and selecting a proper impedance measurement PCB;
s2, performing three-dimensional modeling on the reflection-type impedance measurement PCB, the series-connection straight-through-type impedance measurement PCB, the parallel-connection straight-through-type impedance measurement PCB and the connectors thereof by using simulation software, and performing full-wave simulation on the models to obtain network parameter files, namely snp files, of the impedance measurement boards;
s3, manufacturing the reflection-type impedance measurement PCB, the series-connection through-type impedance measurement PCB and the parallel-connection through-type impedance measurement PCB, and welding and installing devices and connectors by using the impedance measurement PCB;
s4, calibrating the coaxial cable for measurement and the test instrument by using the vector network analyzer and the calibration piece, wherein the reference surface is arranged on the end face of the tail end of the coaxial cable connector after calibration;
s5, using a vector network analyzer and the network parameters of the impedance measurement board obtained by full-wave simulation in S2, and performing de-embedding test on the impedance measurement PCB provided with the patch element by using the snp file to obtain S parameters;
and S6, carrying out post-processing on the test data obtained by the embedded test of the vector network analyzer to obtain the impedance parameters of the surface mount device electronic element.
2. A method of patch electronic impedance measurement based on simulation and de-embedding techniques according to claim 1, wherein the simulation software comprises ANSYS HFSS, FEKO or CST STUDIOs SUITE.
3. The method for measuring impedance of chip electronic component based on simulation and de-embedding technique as claimed in claim 1, wherein in S5, if a reflective impedance measurement PCB is used, S11 parameters are obtained;
if the PCB is measured by using series-connection through type or parallel-connection through type impedance, S21 parameters are acquired.
4. The method for measuring impedance of chip electronic component based on simulation and de-embedding technology as claimed in claim 1, wherein the measured chip component with medium impedance value is measured by reflection measurement, and the conversion relation of impedance and S11 is:
Z dut ＝50×(1+S11)/(1-S11)
the conversion relation between the impedance and S21 of the tested patch element with medium to large impedance value is measured by using the series direct connection method:
Z dut ＝50×2×(1-S21)/S21
and (3) measuring the tested patch element with a very small impedance value by using a parallel through method, wherein the conversion relation of the impedance and S21 is as follows:
Z dut ＝50×S21/(2×(1-S21))
5. the method for measuring impedance of chip electronic component based on emulation and de-embedding technique as claimed in claim 1, wherein the reflection type impedance measurement PCB board comprises a microstrip line with characteristic impedance of 50 Ω; one end of the microstrip line is an SMA connector, the other end of the microstrip line is a pin bonding pad corresponding to the packaged patch element, and the other pin of the bonding pad of the patch element is grounded.
6. The method for measuring the impedance of the chip electronic component based on the simulation and de-embedding technology as claimed in claim 1, wherein the series through type impedance measurement PCB comprises two microstrip lines with equal length and characteristic impedance of 50 Ω; one end of each microstrip line is connected to the two pin bonding pads of the patch element, and the other end of each microstrip line is connected to the two SMA connectors.
7. The method for measuring impedance of a patch electronic element based on simulation and de-embedding technology according to claim 1, wherein the parallel through type impedance measurement PCB board comprises two microstrip lines with equal length and characteristic impedance of 50 Ω, one end of the two microstrip lines is commonly connected to one pin pad of the patch element, the other end is respectively connected to two SMA connectors, and the other pin pad of the patch element is grounded.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100171517A1 (en) * | 2009-01-06 | 2010-07-08 | Nec Electronics Corporation | Impedance measurement method and impedance measurement device |
| CN112684253A (en) * | 2020-11-12 | 2021-04-20 | 西安交通大学 | Non-contact load impedance test system and working method thereof |
| CN112710977A (en) * | 2020-12-11 | 2021-04-27 | 西安电子科技大学 | Surface-mounted passive device S parameter measuring device and method based on TRM calibration |
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- 2022-07-22 CN CN202210868329.4A patent/CN115308489A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100171517A1 (en) * | 2009-01-06 | 2010-07-08 | Nec Electronics Corporation | Impedance measurement method and impedance measurement device |
| CN112684253A (en) * | 2020-11-12 | 2021-04-20 | 西安交通大学 | Non-contact load impedance test system and working method thereof |
| CN112710977A (en) * | 2020-12-11 | 2021-04-27 | 西安电子科技大学 | Surface-mounted passive device S parameter measuring device and method based on TRM calibration |
Non-Patent Citations (3)
| Title |
|---|
| 杨晨光: "工程介电材料介电特性射频测量技术及其应用", 《优秀硕士学位论文 信息科技》, no. 04, pages 12 - 18 * |
| 贺同云;江岩;: "表面贴装器件S参数测量方法研究", 电子测试, no. 06, pages 75 - 78 * |
| 陶峰;黄成;吴建辉;: "射频阻抗测量夹具建模技术的研究及应用", 电子器件, no. 03, pages 349 - 352 * |
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