CN115296283A

CN115296283A - IO port and power port enhancement protection circuit of chip

Info

Publication number: CN115296283A
Application number: CN202210868716.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Chengdu Aich Technology Co Ltd
Current assignee: Chengdu Aich Technology Co Ltd
Priority date: 2022-07-22
Filing date: 2022-07-22
Publication date: 2022-11-04

Abstract

The invention discloses an IO port and power port enhanced protection circuit of a chip, relates to the technical field of chip protection, and aims to solve the problem that an existing chip protection circuit cannot protect an IO port and a power port from ESD impact or us-level impact at the same time. The enhanced protection circuit includes: the discharging branch circuits are arranged between the IO port and the ground and between the power supply port and the ground and used for discharging current when the IO port or the power supply port is impacted; the control branch comprises a primary control branch and a secondary control branch, the secondary control branch is used for controlling whether the primary control branch is conducted or not, and the primary control branch is used for controlling whether the discharge branch is conducted or not; and the detection branch circuit is used for triggering the control branch circuit when detecting that the IO port and the power supply port are subjected to ESD impact or us-level impact, and the control branch circuit controls the discharging branch circuit to discharge current. The enhanced protection circuit provided by the invention is used for releasing energy impact from the IO port and the power supply port of the chip and protecting the internal circuit of the chip.

Description

IO port and power port enhancement protection circuit of chip

Technical Field

The invention relates to the technical field of chip protection, in particular to an IO port and power supply port enhanced protection circuit of a chip.

Background

With the continuous reduction of the size of the chip manufacturing process, the maximum voltage which can be borne by a CMOS circuit inside the chip is also continuously reduced, and in a severe environment, an IO port and a power supply port of the chip have ns-level instantaneous ESD and us-level surge impact discharge processes, so that the chip is damaged.

The existing chip protection circuit only protects against ESD impact or us-level impact on an IO port and ignores the impact on a power port, when the power port is impacted by us-level surge and overvoltage impact, the charging time of an RC in the chip is limited to hundreds of ns levels, the existing chip protection circuit can only respond to ns-level instantaneous ESD impact to carry out discharge clamping, for us-level surge and overvoltage impact, the RC circuit is charged to saturation and cannot respond to trigger the protection circuit, permanent damage can be caused to a chip along with the rise of voltage of us-level surge and overvoltage impact, and the robustness of the chip protection performance is poor.

Disclosure of Invention

The invention aims to provide an IO port and power port enhanced protection circuit of a chip, which is used for solving the problem of poor chip protection robustness caused by the fact that the conventional chip protection circuit cannot simultaneously protect ESD impact and us-level impact of the IO port and the power port.

In order to achieve the above purpose, the invention provides the following technical scheme:

the invention provides an IO port and power port enhanced protection circuit of a chip, which comprises:

the discharging branch circuits are arranged between an IO port and the ground and between a power supply port and the ground and used for discharging current when the IO port or the power supply port is impacted; the shock comprises an ESD shock or a us-level shock;

the control branch comprises a primary control branch and a secondary control branch, the secondary control branch is used for controlling whether the primary control branch is conducted or not, and the primary control branch is used for controlling whether the discharge branch is conducted or not;

the detection branch comprises a first detection branch and a second detection branch, the first detection branch is used for triggering the primary control branch when detecting that the IO port or the power supply port is impacted by ESD, and the primary control branch controls the discharge branch to discharge current under the impact of the ESD; the second detection branch circuit is used for triggering the second-stage control branch circuit when the IO port or the power supply port is subjected to us-stage impact, the second-stage control branch circuit controls the first-stage control branch circuit to be conducted, and the first-stage control branch circuit controls the bleeding branch circuit to bleed current of the us-stage impact.

Optionally, the bleeding branch includes a first power tube, a second power tube, and a third power tube, where the first power tube is an NMOS tube, and the second power tube and the third power tube are diodes; the drain electrode of the first power tube is connected with the power supply port, the anode of the second power tube is connected with the cathode of the third power tube, the first power tube is arranged between the power supply port and the ground, the second power tube is arranged between the power supply port and the IO port, and the third power tube is arranged between the IO port and the ground; the first power tube is used for discharging current of ESD impact or us-level impact of the power port and the IO port, the second power tube is used for transmitting the current of the ESD impact of the IO port to the first detection branch, and the third power tube is used for discharging the current of negative ESD impact of the IO port.

Optionally, the primary control branch includes a first field effect transistor and a second field effect transistor, the first field effect transistor is a PMOS transistor, the second field effect transistor is an NMOS transistor, the first field effect transistor is connected in series with the second field effect transistor, and the first field effect transistor and the second field effect transistor cooperate to control whether the first power transistor is turned on or not.

Optionally, the second grade control branch road includes current-limiting resistor, divider resistance and triode, the collecting electrode of triode with the first grade control branch road links to each other, current-limiting electric group series connection the base electrode of triode, divider resistance with the triode is parallelly connected, divider resistance with current-limiting resistor is parallelly connected, divider resistance is used for doing the triode provides the partial pressure and makes the triode switches on, when the triode switches on, first field effect transistor switches on just the second field effect transistor ends.

Optionally, the first detection branch includes a resistor and a capacitor, the resistor is connected in series with the capacitor, a connection point of the resistor and the capacitor in series is connected to a collector of the triode, the resistor is connected in parallel with the first field-effect transistor, the resistor is connected to the power port, and the capacitor is grounded; the resistor is used for providing divided voltage for the first field effect tube to enable the first field effect tube to be conducted.

Optionally, the second detects the branch road and includes IO detection branch road and power detection branch road, IO detection branch road connects the IO port with the secondary control branch road, IO detection branch road includes first zener diode and first diode, the negative pole of first zener diode is connected the IO port, the positive pole of first zener diode is connected the positive pole of first diode, works as when the IO port receives us level and strikes, first zener diode reverse breakdown switches on, triggers the secondary control branch road switches on, the threshold voltage of first zener diode is greater than chip operating voltage's peak value.

Optionally, the power supply detection branch circuit includes a second zener diode and a second diode, a cathode of the second zener diode is connected to the power supply port, an anode of the second zener diode is connected to an anode of the second diode, and when the power supply port is subjected to us-level impact, the second zener diode is in reverse breakdown conduction to trigger the secondary control branch circuit to be in conduction; the threshold voltage of the second Zener diode is larger than the peak value of the working voltage of the chip.

Optionally, when the IO port or the power port is impacted by ESD, the resistor and the capacitor are charged to turn on the first field effect transistor and the second field effect transistor, so as to drive the first power transistor to be turned on, and realize ESD impact discharge current to the IO port or the power port.

Optionally, when the second detection branch detects a us-level impact, a high level is provided for a base electrode of the triode through the voltage dividing resistor and the current limiting resistor, so that a gate of the first field effect transistor is turned on at a low level, a gate of the second field effect transistor is turned off at a low level, and at this time, a gate of the first power transistor is turned on at a high level.

Optionally, when the chip normally works, the collector of the triode is connected with the power supply through the resistor and is at a high level, the first field effect transistor is controlled to be turned off, the second field effect transistor is controlled to be turned on, and at this time, the gate of the first power transistor is turned off at a low level.

Compared with the prior art, the IO port and power supply port enhanced protection circuit of the chip provided by the invention comprises: the discharging branch circuits are arranged between the IO port and the ground and between the power supply port and the ground and used for discharging current when the IO port or the power supply port is impacted; shock includes ESD shock or us-level shock; the control branch comprises a primary control branch and a secondary control branch, the secondary control branch is used for controlling whether the primary control branch is conducted or not, and the primary control branch is used for controlling whether the discharge branch is conducted or not; the detection branch comprises a first detection branch and a second detection branch, the first detection branch is used for triggering a primary control branch when detecting that the IO port or the power supply port is impacted by ESD, and the primary control branch controls the discharging branch to discharge current for the ESD impact; the second detection branch circuit is used for triggering the second-level control branch circuit when detecting that the IO port or the power supply port is subjected to us-level impact, the second-level control branch circuit controls the first-level control branch circuit to be conducted, and the first-level control branch circuit controls the discharging branch circuit to discharge current of the us-level impact. ESD impact received by the power port and the IO port is detected through the first detection branch, us-level impact received by the IO port and the power port is detected through the second detection branch, and when the detection branch detects ESD impact or us-level impact, the control circuit is triggered, so that the discharge branches arranged between the power port and the ground and between the IO port and the ground are rapidly conducted, overvoltage energy of clamp impact is discharged, a chip internal circuit is protected, and robustness of chip protection performance is enhanced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not limit the invention. In the drawings:

fig. 1 is a structure diagram of an enhanced protection circuit for an IO port and a power port of a chip according to an embodiment of the present invention.

Reference numerals:

10-a bleeder branch, 11-a primary control branch, 12-a secondary control branch, 13-a first detection branch, 14-an IO detection branch and 15-a power supply detection branch.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The overvoltage current caused by Electrostatic Discharge (ESD) and surge is a main cause of failure of an integrated circuit in a chip, ESD impact or surge impact Discharge occurs at a power port and an IO port of the chip, and the chip is damaged.

Based on the above problems, the invention provides an enhanced protection circuit for an IO port and a power port of a chip, the enhanced protection circuit is provided with detection branches at the IO port and the power port of the chip respectively, each detection branch is provided with a zener diode, the zener diode is rapidly conducted when the detection branch is subjected to us-level impact, and the discharge branch is triggered to discharge and voltage clamp through two stages of control branches, so as to protect an internal circuit of the chip. The us-grade impact is the us-grade surge impact and the overvoltage impact, and the invention is called us-grade impact for short. The following description is made with reference to the drawings.

Fig. 1 is a structure diagram of an enhanced protection circuit for an IO port and a power port of a chip according to an embodiment of the present invention, as shown in fig. 1, the enhanced protection circuit includes: the device comprises a discharge branch 10, a primary control branch 11, a secondary control branch 12, a first detection branch 13, an IO detection branch 14 and a power supply detection branch 15, wherein the discharge branch 10 is arranged between an IO port and the ground and between a power supply port and the ground, the primary control branch 11 is connected with the discharge branch 10, the secondary control branch 12 is connected with the primary control branch 11, the first detection branch 13 is arranged between the power supply and the ground and is respectively connected with the primary control branch 11 and the secondary control branch 12, the power supply detection branch 15 is respectively connected with the power supply port and the secondary control branch 12, and the IO detection branch 14 is respectively connected with the IO port and the secondary control branch 12;

the bleeding branch 10 is used for bleeding current when the IO port or the power supply port is impacted; the shock comprises an ESD shock or an us-level shock;

the primary control branch 11 and the secondary control branch 12 form a control branch of the enhanced protection circuit, the secondary control branch 12 is used for controlling whether the primary control branch 11 is conducted, and the primary control branch 11 is used for controlling whether the discharge branch 10 is conducted;

the IO detection branch 14, the power supply detection branch 15 and the first detection branch 13 form a detection branch of the enhanced protection circuit, the first detection branch 13 is used for triggering the primary control branch 11 when detecting that the IO port or the power supply port is impacted by ESD, and the primary control branch 11 controls the discharging branch 10 to discharge current after the ESD impact; the power supply detection branch circuit 15 is used for triggering the secondary control branch circuit 12 when detecting that the power supply port is subjected to us-level impact, the secondary control branch circuit 12 controls the primary control branch circuit 11 to be conducted, and the primary control branch circuit 11 controls the discharge branch circuit 10 to discharge us-level impact current; the IO detection branch 14 is configured to trigger the second-stage control branch 12 when it is detected that the IO port is subjected to us-level impact, the second-stage control branch 12 controls the first-stage control branch 11 to be conducted, and the first-stage control branch 11 controls the bleeding branch 10 to bleed current of the us-level impact.

In specific implementation, when the IO port or the power port is impacted by ESD, the first detection branch 13 detects an impact current and provides a conduction voltage for the primary control branch 11, so as to drive the discharging branch 10 to discharge current; when the power port receives the us-level impact, the power detection branch 15 detects the impact current, a conduction voltage is provided for the second-level control branch 12, the second-level control branch 12 provides a conduction voltage for the first-level control branch 11, and then drives the discharging branch 10 to discharge the current, when the IO port receives the us-level impact, the IO detection branch 14 detects the impact current, a conduction voltage is provided for the second-level control branch 12, the second-level control branch 12 provides a conduction voltage for the first-level control branch 11, and then drives the discharging branch 10 to discharge the current, and the protection of the chip internal circuit is realized.

According to the structure and the specific implementation process of the enhanced protection circuit, the first detection branch 13 detects ESD impact on a power port and an IO port, the power detection branch 15 detects us-level impact on the power port, the IO detection branch 14 detects us-level impact on the IO port, and when the detection branch detects ESD impact or us-level impact, the control branch is triggered to enable the discharge branches arranged between the power port and the ground and between the IO port and the ground to be rapidly conducted, so that over-voltage energy of clamp impact is discharged, an internal circuit of a chip is protected, and robustness of protection performance of the chip is enhanced.

As a possible implementation manner, referring to fig. 1, the bleeding branch 10 includes a first power transistor Q3, a second power transistor D1, a third power transistor D2, and a resistor R5, where the first power transistor Q3 is an NMOS transistor, and the second power transistor D1 and the third power transistor D2 are diodes; the drain electrode of the first power tube Q3 is connected with a power supply port, the cathode of the second power tube D1 is connected with the drain electrode of the first power tube Q3, the anode of the second power tube D1 is connected with the cathode of the third power tube D2, the first power tube Q3 is arranged between the power supply port and the ground, the second power tube D1 is arranged between the power supply port and an IO port, and the third power tube D2 is arranged between the IO port and the ground; the resistor R5 is connected with the first power tube Q3 in parallel, the resistor R5 is connected with the primary control branch 11, the first power tube Q3 is used for discharging ESD impact current or us impact current of the power port and the IO port, the second power tube D1 is used for transmitting the ESD impact current of the IO port to the first detection branch, and the third power tube D2 is used for discharging negative ESD impact current of the IO port.

The first power tube Q3 is low in impedance when being conducted between VDD and GND, and can effectively protect ESD and us-level impact of an IO port and a power supply port. The second power tube D1 and the third power tube D2 have a reverse isolation function, and the second power tube D1 can prevent an impulse current of the power supply port from flowing to the IO port.

As a possible implementation manner, referring to fig. 1, the primary control branch 11 includes a first field effect transistor Q1 and a second field effect transistor Q2, the first field effect transistor Q1 is a PMOS transistor, the second field effect transistor Q2 is an NMOS transistor, the first field effect transistor Q1 is connected in series with the second field effect transistor Q2, and a junction between a source of the first field effect transistor Q1 and a drain of the second field effect transistor Q2 is connected to a gate of the first power transistor Q3 and a resistor R5.

The primary control branch 11 is used for controlling the on/off of a first power tube Q3 in the discharge branch 10, and the first field effect tube Q1 and the second field effect tube Q2 cooperate to control whether the first power tube Q3 is on or off, specifically, when the chip normally works, the second field effect tube Q2 is on, the first field effect tube Q1 is off, and at this time, the first power tube Q3 is off; when the ESD impact occurs, the first field effect tube Q1 and the second field effect tube Q2 are conducted together, and the first power tube Q3 is controlled to be conducted through voltage division of the conducting resistors Q1 and Q2; when the us-level impact is applied, the first field effect tube Q1 is switched on, the second field effect tube Q2 is switched off, and the first power tube Q3 is switched on; the grid of the first field effect transistor Q1 is conducted when being at low level and is cut off when being at high level, and the grid of the second field effect transistor Q2 is conducted when being at high level and is cut off when being at low level.

As a possible implementation manner, referring to fig. 1, the secondary control branch 12 includes a current limiting resistor R2, a voltage dividing resistor R3, and a transistor Q4, a collector of the transistor Q4 is connected to a junction of a gate of the first field effect transistor Q1 and a gate of the second field effect transistor, the current limiting resistor R2 is connected in series to a base electrode of the transistor Q4, the voltage dividing resistor R3 is connected in parallel to the current limiting resistor R2, the voltage dividing resistor R3 is configured to provide a divided voltage for the transistor Q4 to turn on the transistor Q4, and when the transistor Q4 is turned on, the first field effect transistor Q1 is turned on and the second field effect transistor Q2 is turned off.

The transistor Q4 can be selected from models 2N1070, 2N1069, and the like. When the second detection branch detects us-level impact, a high level is provided for the base electrode of the triode Q4 through the voltage division resistor R3 and the current limiting resistor R2, so that the grid of the first field effect transistor Q1 is in a low level and is conducted, the grid of the second field effect transistor is in a low level and is cut off, and at the moment, the grid of the first power transistor Q3 is in a high level and is conducted.

As a possible implementation manner, referring to fig. 1, the first detection branch 13 includes a resistor R4 and a capacitor C1, the resistor R4 is connected in series with the capacitor C1, a collector of the triode Q4 is connected at a connection point where the resistor R4 is connected in series with the capacitor C1, the resistor R4 is connected in parallel with the first field-effect transistor Q1, the resistor R4 is connected to a power port, and the capacitor C1 is grounded; the resistor R4 is used for providing a divided voltage for the first field effect transistor Q1 to turn on the first field effect transistor Q1.

As a possible implementation manner, referring to fig. 1, the IO detection branch 14 includes a first zener diode D3 and a first diode D4, a cathode of the first zener diode D3 is connected to the IO port, an anode of the first zener diode D3 is connected to an anode of the first diode D4, when the IO port is impacted by us level, the first zener diode D3 is in reverse breakdown conduction to trigger the second-level control branch 12 to be in conduction, and a threshold voltage of the first zener diode D3 is greater than a peak value of a chip operating voltage.

As a possible implementation manner, referring to fig. 1, the power supply detection branch 15 includes a second zener diode D5 and a second diode D6, a cathode of the second zener diode D5 is connected to the power supply port, an anode of the second zener diode D5 is connected to an anode of the second diode D6, and when the power supply port is subjected to a us-level impact, the second zener diode D5 is in reverse breakdown conduction to trigger the secondary control branch 12 to be in conduction; the threshold voltage of the second zener diode D5 is greater than the peak value of the chip operating voltage.

The first diode D4 and the second diode D6 have a reverse isolation function, and can avoid interference of the current of the secondary control branch 12 on the IO port and the power supply port.

In order to avoid the situation that the duration of the impact encountered by the IO port or the power port exceeds the charging time of R4 and C1, and the two zener diodes are not broken down, it is necessary to match and design that the two zener diodes break down in advance before the R4 and C1 are saturated.

The operation of the enhanced protection circuit of the present invention is described with reference to fig. 1: when the chip normally works, the first Zener diode D3 in the IO detection branch circuit and the second Zener diode D5 in the power supply detection branch circuit are reversely cut off, the base electrode of the triode Q4 is in a low level and is not conducted, the collector electrode of the triode Q4 is connected with the power supply VDD through the resistor R4 and is in a high level, the first field effect tube Q1 is controlled to be cut off, the second field effect tube Q2 is controlled to be conducted, at the moment, the grid electrode of the first power tube Q3 is in a low level and is not conducted, and the enhanced protection circuit does not influence the normal work of the chip.

When an IO port of the chip is impacted by ESD, an impact current flows to the first detection branch 13 through the second power tube D1, and is charged through the resistor R4 and the capacitor C1, so that the first field-effect tube Q1 and the second field-effect tube Q2 in the primary control branch 11 are switched on, and the first power tube Q3 in the discharge branch 10 is driven to be switched on, thereby realizing the ESD impact discharge current of the IO port.

When the power port of the chip is impacted by ESD, the impact current flows to the first detection branch 13, and is charged through the resistor R4 and the capacitor C1, so that the first field-effect tube Q1 and the second field-effect tube Q2 in the primary control branch 11 are turned on, the first power tube Q3 in the discharge branch 10 is driven to be turned on, and the ESD impact discharge current of the IO port is realized.

When the IO port of the chip encounters us-level impact and the duration exceeds the charging time of R4 and C1, the gate voltage and the drain voltage of the first field-effect transistor Q1 in the first-level control branch 11 are equal to VDD and are turned off, and the conduction of the first power transistor Q3 in the bleeding branch 10 cannot be continuously maintained; at this time, the overshoot voltage exceeds the reverse breakdown threshold of the first zener diode D3 of the IO detection branch 14, D3 is turned on, a high level is provided for the base electrode of the triode Q4 through the first diode D4, the voltage dividing resistor R3 and the current limiting resistor R2, the triode Q4 is turned on, so that the gate of the first field effect transistor Q1 in the primary control branch 11 is turned on for a low level, the gate of the second field effect transistor Q2 is turned off for a low level, at this time, the gate of the first power transistor Q3 in the discharge branch 10 is turned on for a high level continuously, the us-level impact discharge clamp of the IO port is performed, and the internal circuit of the chip is protected continuously.

When the power port of the chip encounters us-level impact and the duration exceeds the charging time of R4 and C1, the gate voltage and the drain voltage of the first field-effect transistor Q1 in the first-level control branch 11 are equal to VDD and are turned off, and the conduction of the first power transistor Q3 in the bleeding branch 10 cannot be continuously maintained; at this time, the overshoot voltage exceeds the reverse breakdown threshold of the second zener diode D5 of the power detection branch 15, D5 is turned on, a high level is provided for the base electrode of the triode Q4 through the second diode D6, the voltage dividing resistor R3 and the current limiting resistor R2, the triode Q4 is turned on, so that the gate of the first field effect transistor Q1 in the primary control branch 11 is turned on due to the low level, the gate of the second field effect transistor Q2 is turned off due to the low level, and at this time, the gate of the first power transistor Q3 in the discharge branch 10 is turned on due to the high level, so that the us-level surge discharge clamp of the power port is turned on, and the internal circuit of the chip is protected continuously.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. The utility model provides a IO port and power port reinforcing protection circuit of chip which characterized in that includes:

the bleeding branch circuits are arranged between the IO port and the ground and between the power supply port and the ground and are used for bleeding current when the IO port or the power supply port is impacted; the shock comprises an ESD shock or an us-level shock;

the detection branch circuit comprises a first detection branch circuit and a second detection branch circuit, the first detection branch circuit is used for triggering the primary control branch circuit when the IO port or the power supply port is detected to be impacted by ESD, and the primary control branch circuit controls the discharge branch circuit to discharge current to the ESD impact; the second detection branch circuit is used for triggering the second-level control branch circuit when detecting that the IO port or the power port is subjected to us-level impact, the second-level control branch circuit controls the first-level control branch circuit to be conducted, and the first-level control branch circuit controls the bleeding branch circuit to bleed current of the us-level impact.

2. The enhanced protection circuit of claim 1, wherein the bleeding branch comprises a first power transistor, a second power transistor and a third power transistor, the first power transistor is an NMOS transistor, and the second power transistor and the third power transistor are diodes; the drain electrode of the first power tube is connected with the power supply port, the anode of the second power tube is connected with the cathode of the third power tube, the first power tube is arranged between the power supply port and the ground, the second power tube is arranged between the power supply port and the IO port, and the third power tube is arranged between the IO port and the ground; the first power tube is used for discharging current of ESD impact or us-level impact of the power port and the IO port, the second power tube is used for transmitting the current of the ESD impact of the IO port to the first detection branch, and the third power tube is used for discharging the current of negative ESD impact of the IO port.

3. The enhanced protection circuit of claim 2, wherein the primary control branch comprises a first fet and a second fet, the first fet being a PMOS transistor, the second fet being an NMOS transistor, the first fet being connected in series with the second fet, the first fet and the second fet cooperating to control whether the first power transistor is turned on.

4. The enhanced protection circuit of claim 3, wherein the secondary control branch comprises a current limiting resistor, a voltage dividing resistor, and a transistor, wherein a collector of the transistor is connected to the primary control branch, the current limiting resistor is connected in series with a base electrode of the transistor, the voltage dividing resistor is connected in parallel with the current limiting resistor, the voltage dividing resistor is configured to provide a divided voltage to the transistor to turn on the transistor, and when the transistor is turned on, the first FET is turned on and the second FET is turned off.

5. The enhanced protection circuit of claim 4, wherein the first detection branch comprises a resistor and a capacitor, the resistor is connected in series with the capacitor, a junction of the resistor and the capacitor in series is connected to a collector of the triode, the resistor is connected in parallel with the first field effect transistor, the resistor is connected to the power port, and the capacitor is grounded; the resistor is used for providing divided voltage for the first field effect transistor to enable the first field effect transistor to be conducted.

6. The enhanced protection circuit according to claim 1, wherein the second detection branch comprises an IO detection branch and a power supply detection branch, the IO detection branch is connected to the IO port and the secondary control branch, the IO detection branch comprises a first zener diode and a first diode, a cathode of the first zener diode is connected to the IO port, an anode of the first zener diode is connected to an anode of the first diode, when the IO port is subjected to a us-level impact, the first zener diode is turned on in a reverse breakdown manner to trigger the secondary control branch to be turned on, and a threshold voltage of the first zener diode is greater than a peak value of a chip operating voltage.

7. The enhanced protection circuit of claim 1, wherein the power detection branch comprises a second zener diode and a second diode, a cathode of the second zener diode is connected to the power port, an anode of the second zener diode is connected to an anode of the second diode, and when the power port is impacted by us class, the second zener diode is in reverse breakdown conduction to trigger the secondary control branch to be in conduction; the threshold voltage of the second Zener diode is larger than the peak value of the working voltage of the chip.

8. The enhanced protection circuit according to claim 5, wherein when the IO port or the power port is subjected to ESD impact, the resistor and the capacitor are charged to turn on the first field effect transistor and the second field effect transistor, so as to drive the first power transistor to be turned on, and thus ESD impact discharge current to the IO port or the power port is realized.

9. The enhanced protection circuit as claimed in claim 4, wherein when the second detection branch detects a us-level surge, a high level is provided to the base electrode of the triode through the voltage dividing resistor and the current limiting resistor, so that the gate of the first fet is turned on at a low level, the gate of the second fet is turned off at a low level, and the gate of the first fet is turned on at a high level.

10. The enhanced protection circuit of claim 5, wherein when the chip is in normal operation, the collector of the triode is connected to the power supply via the resistor to be at a high level, so as to control the first fet to be turned off and the second fet to be turned on, and at this time, the gate of the first fet is turned off at a low level.