CN115295484A

CN115295484A - Self-aligned stacked via processing method, wafer, isolator and preparation method thereof

Info

Publication number: CN115295484A
Application number: CN202210967902.7A
Authority: CN
Inventors: 叶蕾; 王峰; 黄永彬
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2022-08-12
Filing date: 2022-08-12
Publication date: 2022-11-04

Abstract

The invention provides a self-aligned laminated through hole processing method, a wafer, an isolator and a preparation method of the isolator. The self-aligning stacking through hole processing method comprises the steps of sequentially forming a first metal interconnection layer, at least one stacking layer, a top dielectric layer and a second metal interconnection layer on the upper surface of a substrate, wherein the stacking layer is a structure formed by a middle dielectric layer and an insulating layer formed on the upper surface of the middle dielectric layer, and sequentially stacking and mutually communicating through hole structures are formed in the process of stacking the structures, the through hole positioned at the bottommost corresponds to a first drop point of the first metal interconnection layer, and the through hole positioned at the topmost corresponds to a second drop point of the second metal interconnection layer, so that metal in the through hole is communicated with the metal interconnection layers at two sides. The processing method of the self-aligned laminated through hole can enable the upper layer through hole to be accurately positioned above the lower layer through hole, and a metal layer does not need to be formed between the dielectric layers, so that the process is simpler, and metal materials are saved.

Description

Self-aligned stacked via processing method, wafer, isolator and preparation method thereof

Technical Field

The specification relates to the technical field of semiconductors, in particular to a self-aligned laminated through hole processing method, a wafer, an isolator and a preparation method of the wafer.

Background

In semiconductor structures, it is often desirable to interconnect conductive structures across multiple layers through vias (via). In the conventional wafer production, a self-alignment process is used, and as the size of a device is continuously reduced, the alignment performance between a through hole and a multi-layer conductive structure connected with the through hole needs to be improved. In addition, the multi-layer stacked via structure needs to be implemented by multiple vias and multiple metal layers, and the multiple metal layers used are usually only used as a stop layer and a transition layer of the vias, and the self-alignment process needs to be improved.

Disclosure of Invention

Embodiments of the present disclosure provide a self-aligned stacked via processing method, a wafer and an isolator, and a method for manufacturing the same. The self-aligned laminated through hole processing method can conveniently communicate laminated through holes of all layers, and metal layers and process steps are saved.

The embodiment of the specification provides the following technical scheme:

a self-aligned stacked via processing method, comprising:

sequentially forming a first metal interconnection layer, at least one stacking layer, a top dielectric layer and a second metal interconnection layer from the upper surface of a substrate, wherein the stacking layer is a structure formed by a middle dielectric layer and an insulating layer formed on the upper surface of the middle dielectric layer;

forming a stacked through hole structure in the process of forming each layer structure, wherein the stacked through hole structure is a through hole structure interconnected between the first metal interconnection layer and the second metal interconnection layer;

wherein the process of forming the stacked via structure comprises: after the first metal interconnection layer is formed, forming a first drop point corresponding to the stacking through hole on the first metal interconnection layer; after the stacked layers are formed, forming a first through hole in the stacked layers, and depositing and forming a first metal into the first through hole, wherein the first through hole of a first stacked layer corresponds to the first falling point, the first through holes of the front and rear stacked layers correspond to each other, the top surface of the first metal is located at a preset position below a first target surface, and the first target surface is a plane where the upper surface of an insulating layer in the first stacked structure is located; after the top dielectric layer is formed, forming a second through hole corresponding to the first through hole in the top dielectric layer, and depositing a second metal into the second through hole; and finally, after the second metal interconnection layer is formed, forming a second landing point corresponding to the second through hole on the second metal interconnection layer.

According to the self-aligned stacked through hole processing method, through holes of all layers are simultaneously generated in the process of forming the dielectric layers and the insulating layers which are sequentially stacked, the through holes positioned on the upper layer can be accurately positioned above the through holes on the lower layer, a metal layer does not need to be formed between the dielectric layers, the process is simpler, and metal materials are saved.

The embodiment of the present specification also provides a solution, when there is more than one of the stacked layers, in the stacked layers adjacent in front and behind, setting the aperture of the first through hole of the next stacked layer to be different from the aperture of the first through hole of the previous stacked layer;

and/or, the aperture of the second through hole is set to be different from the aperture of the first through hole adjacent to the second through hole.

The embodiment of the present specification further provides a solution, where an aperture of the first through hole of the next stacked layer is 1.1 to 1.5 times an aperture of the first through hole of the previous stacked layer.

The embodiments of the present disclosure further provide a solution, after depositing a first metal into the first via, when a top surface of the first metal is not located at a predetermined position below the first target surface, performing a chemical mechanical polishing process on the insulating layer to remove a portion of the first metal at a top end position of the first via, so that the top surface of the first metal is located at the predetermined position below the first target surface.

The embodiment of the present disclosure further provides a solution, where the chemical mechanical polishing process includes a main polishing step and an over-polishing step, where in the main polishing step, a polishing liquid adapted to the first metal is used to polish the insulating layer, and the main polishing step is completed by an end point detection method, and the over-polishing step is used to continue performing a corrosion reaction on the first metal after the main polishing step is completed, so that a top surface of the first metal is lower than a predetermined position below the first target surface.

Embodiments of the present specification also provide an approach in which a top surface of the first metal is located at a predetermined position between upper and lower surfaces of the insulating layer.

Embodiments of the present specification also provide an approach, where the first metal and/or the second metal comprise tungsten;

and/or the insulating layer is an insulating medium layer formed by silicon nitride.

The embodiment of the present specification further provides a solution, where the method for processing a self-aligned stacked via further includes: and forming the first through hole and/or the second through hole by using a dry etching process, and stopping etching operation on the upper surface of the first metal interconnection layer and/or the upper surface of the insulating layer by controlling the selection ratio in the etching process.

The embodiment of the specification also provides a scheme, in the etching process, the laser wavelength is 355-400 nm, the laser pulse width is less than 12ps, the laser frequency is 1800-2000 kHz, the power is 2.5-4W, the scanning speed is 1400-1800 mm/s, and the aperture of the first through hole is 1-2 μm.

Embodiments of the present disclosure also provide a wafer, where the wafer includes:

the structure comprises a laminated structure, a first metal interconnection layer, at least one stacking layer, a top dielectric layer and a second metal interconnection layer, wherein the laminated structure is formed on the upper surface of a substrate and is formed by an intermediate dielectric layer and an insulating layer, the intermediate dielectric layer and the insulating layer are sequentially formed on the upper surface of the intermediate dielectric layer;

and a plurality of stacked vias for interconnecting between the first metal interconnection layer and the second metal interconnection layer, wherein the stacked vias are formed by using a self-aligned stacked via processing method such as any one of the above methods.

Embodiments of the present specification further provide a semiconductor isolator, including:

a substrate;

the semiconductor isolator comprises a first metal interconnection layer, at least one stacking layer, a top layer dielectric layer and a second metal interconnection layer which are sequentially stacked from the upper surface of a substrate, wherein the stacking layer is a structure formed by an intermediate dielectric layer and an insulating layer on the upper surface of the intermediate dielectric layer, the first metal interconnection layer and the second metal interconnection layer are metal connection layers of an isolator, and the stacking layer and the top layer dielectric layer form a dielectric layer structure in the semiconductor isolator;

and a plurality of stacked vias interconnected between the first metal interconnection layer and the second metal interconnection layer, wherein the stacked vias are formed by using any one of the self-aligned stacked via processing methods.

The embodiment of the present specification further provides a scheme, where the intermediate dielectric layer and/or the top dielectric layer include a silicon oxide layer, and a dielectric constant of the silicon oxide layer is 4.2;

and/or the insulating layer comprises a silicon nitride layer.

The embodiment of the present specification further provides a solution, wherein the thickness of the silicon oxide layer is 3 to 8 μm;

and/or the thickness of the silicon nitride layer is 1-3 mu m.

An embodiment of the present specification further provides a method for manufacturing a semiconductor isolator, including:

preparing a semiconductor body of an isolator by using the self-aligned stacked via processing method of any one of the preceding claims, wherein the semiconductor body comprises a substrate, a first metal interconnection layer, at least one stacked layer, a top dielectric layer, a second metal interconnection layer and a plurality of stacked vias interconnected between the first metal interconnection layer and the second metal interconnection layer, wherein the first metal interconnection layer, the at least one stacked layer, the top dielectric layer and the second metal interconnection layer are sequentially stacked from the upper surface of the substrate;

and bonding interconnection lines on the first metal interconnection layer and the second metal interconnection layer to form a pin connecting line of the semiconductor isolator.

Compared with the prior art, the beneficial effects that can be achieved by the at least one technical scheme adopted by the embodiment of the specification at least comprise:

according to the processing method for the self-aligned stacked through hole, the dielectric layer and the insulating layer are sequentially formed between the metal interconnection layers at the upper end and the lower end, so that the stacked structure is formed, through holes penetrating through each stacked structure are formed layer by layer in the forming process of the stacked structure, the through hole at the upper layer is accurately positioned above the through hole at the lower layer, positioning and communication among the through holes are carried out, a metal layer is not needed, the generation process is simplified, and consumption of metal materials is saved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a stacked via structure in the prior art;

FIG. 2 is a schematic diagram of a stacked via structure in one embodiment of the invention;

fig. 3 is a schematic diagram of a process of forming a stacked via structure according to an embodiment of the present invention (fig. 3 (a) is a schematic diagram of sequentially forming a first interlayer dielectric layer and a first insulating layer on an upper surface of a first metal interconnection layer, fig. 3 (b) is a schematic diagram of forming a first via in a deposition of the first interlayer dielectric layer and the first insulating layer, fig. 3 (c) is a schematic diagram of depositing a first metal in the first via, fig. 3 (d) is a schematic diagram of removing a portion of the first metal on top of the first metal, fig. 3 (e) is a schematic diagram of sequentially forming a second interlayer dielectric layer and a second insulating layer on an upper surface of the first insulating layer, fig. 3 (f) is a schematic diagram of forming a first via in a deposition of the second interlayer dielectric layer and the second insulating layer, fig. 3 (g) is a schematic diagram of depositing the first metal in the stacked first via, and fig. 3 (h) is a schematic diagram of removing a portion of the first metal on top of the stacked first metal;

fig. 4 is a schematic view showing a process of forming an upper layer via hole having a diameter larger than that of a lower layer via hole in an embodiment of the present invention (fig. 4 (a) is a schematic view of removing a part of a first metal in a first lamination mechanism, fig. 4 (b) is a schematic view of forming a first via hole having a larger diameter in a second lamination structure, and fig. 4 (c) is a schematic view of depositing a first metal in the first via hole of the second lamination structure and removing the first metal of a top end portion);

10, a first through hole, 11, a first drop point, 12, a first metal, 13, a first recess, 20, a second through hole, 21, a second drop point, 22 and a second metal.

Detailed Description

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The following embodiments of the present application are described by specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The application is capable of other and different embodiments and its several details are capable of modifications and various changes in detail without departing from the spirit of the application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. In addition, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to or other than one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

It is to be understood that "the component a is connected to the component B" means that the component a is directly connected to the component B in contact therewith, or the component a is indirectly connected to the component B through other components. The terms of orientation of "upper", "lower", "inner", "outer", "side", and the like described in the exemplary embodiments of the present specification are described with respect to the angles shown in the drawings, and should not be construed as limiting the exemplary embodiments of the present specification.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

In semiconductor structures, it is often desirable to interconnect conductive structures across multiple layers through vias (via). For example, a semiconductor isolator, requires a thicker dielectric layer (transition layer) to be formed to realize a high withstand voltage, and it is a common practice to stack a plurality of dielectric layers. At this time, if the electrode plates on both sides of the separator need to be connected, a connection line (such as a metal line) needs to be disposed in each dielectric layer to achieve electrical connection. Because the positions of the connecting lines in each dielectric layer are different, a metal layer needs to be arranged between the adjacent dielectric layers, and the connecting lines on the two adjacent sides are communicated by using the metal layer, as shown in fig. 1, the connecting lines of the lower plate need to be realized by multiple through holes (through holes in TV1, TV2 and TV 3) and metal layers (TM 1, TM2 and TM 3), and the metal layers (TM 1, TM2 and TM 3) are only used as passing stop layers and transition layers, so that unnecessary waste is formed. Moreover, as the size of the device is continuously reduced, the alignment difficulty between the through hole and the multi-layer conductive structure connected with the through hole is increased, and the requirement of the processing technology is improved.

In order to solve the above problems, the present invention provides a self-aligned stacked via processing method, a wafer and an isolator, and a method for manufacturing the same. The self-aligned laminated through hole processing method comprises the steps of forming an insulating layer to replace a metal layer in the original process after an intermediate medium layer is formed, then forming a first through hole in the intermediate medium layer and the insulating layer, finally depositing metal in the first through hole and removing the metal at the top end part, so that the upper surface of the metal is lower than the upper surface of the insulating layer, the self-aligned laminated through hole processing method is used for positioning the first through hole to be constructed on the upper layer, and the metals in the through holes are better communicated with each other. And repeating the processes to form the number of the intermediate dielectric layers and the insulating layers meeting the design requirements, and keeping the position of the first through hole in each layer unchanged in the forming process of each laminated structure, so that the first through hole in the upper layer structure is accurately positioned above the first through hole in the lower layer structure. And stacking a top dielectric layer on the upper surface of the uppermost insulating layer, and forming a second through hole in the top dielectric layer, wherein the second through hole is exactly positioned above the first through hole in the lower layer structure, so that the second through hole is communicated with metal in each first through hole to form a stable structure for electrically connecting two sides of the multi-layer structure.

The technical solutions provided by the embodiments of the present application are described below with reference to the accompanying drawings.

As shown in fig. 2 and fig. 3, the method for processing a self-aligned stacked via is exemplified by a structure in which two stacked layers and a top dielectric layer are formed, wherein each stacked layer includes an intermediate dielectric layer and an insulating layer formed on an upper surface of the intermediate dielectric layer, and the method for processing a self-aligned stacked via includes the following steps:

step S1, providing a substrate, forming a first metal interconnection layer (TM 1) on the upper surface of the substrate, and forming a first landing point 11 on the upper surface of the first metal interconnection layer (TM 1);

step S2, as shown in fig. 3 (a), forming a first stacked layer on the upper surface of the first metal interconnection layer (TM 1), that is, sequentially forming a first intermediate dielectric layer (TV 1) and a first insulating layer (SIN 1);

step S3, as shown in fig. 3 (b), forming a first through hole 10 in the first intermediate dielectric layer (TV 1) and the first insulating layer (SIN 1), wherein a lower end of the first through hole 10 is located at the first landing point 11;

step S4, as shown in fig. 3 (c), depositing a first metal 12 in the first via hole 10;

step S5, as shown in fig. 3 (d), removing the first metal 12 at the top portion of the first metal 12, so that the top surface of the first metal 12 (i.e. the upper surface at the top position of the first metal 12) is lower than the upper surface of the first insulating layer (SIN 1) and is located at a predetermined position, thereby forming a first recess 13;

step S6, as shown in fig. 3 (e), forming a second stacked layer on the upper surface of the first insulating layer (SIN 1), that is, sequentially forming a second intermediate medium layer (TV 2) and a second insulating layer (SIN 2);

step S7, as shown in fig. 3 (f), forming a second first through hole 10 in the second intermediate dielectric layer (TV 2) and the second insulating layer (SIN 2), wherein the lower end of the first through hole 10 corresponds to the first recess 13 (at the "TV2 landing point" in fig. 3 (f));

step S8, as shown in fig. 3 (g), depositing a first metal 12 in the first via hole 10 of the second intermediate dielectric layer (TV 2) and the second insulating layer (SIN 2);

step S9, as shown in fig. 3 (h), forming a second first recess 13 with reference to step S5;

step S10, as shown in fig. 2, forming a top dielectric layer (TV 3) on the upper surface of the second insulating layer (SIN 2);

step S11, as shown in fig. 2, forming a second via hole 20 in the top dielectric layer (TV 3), and depositing a second metal 22 in the second via hole 20;

step S12, as shown in fig. 2, a second metal interconnection layer (MT) is formed on the upper surface of the top dielectric layer (TV 3), and a second landing point 21 is formed on the lower surface of the second metal interconnection layer (MT), so that the second landing point 21 is correspondingly connected to the upper surface of the second metal 22.

It should be noted that the structure of the two stacked layers and the top dielectric layer (TV 3) formed in the above steps is only an example, and does not limit the self-aligned stacked via processing method. According to design requirements, the number of stacked layers can be flexibly set to form different structures. For example, the second intermediate dielectric layer (TV 2) and the second insulating layer (SIN 2) in fig. 2 and 3 are removed, and the second metal interconnection layer (MT) is formed directly on the upper surface of the first intermediate dielectric layer (TV 1) to form a single-layer stacked structure; for example, one or more stacked layers are sequentially stacked on the upper surface of the second insulating layer (SIN 2) to form a stacked structure with three or more layers. Regardless of how many stacked layers are formed, the first through holes are positioned in the manner of forming the first through holes, and the second through holes and the first through holes are positioned in the manner of forming the second through holes by the same steps as those in the above-described embodiment.

In the self-aligning stacking through hole processing method, in the process of forming the dielectric layers and the insulating layers which are sequentially stacked, through holes in all layers are synchronously formed, and metal on the top of the through hole in the lower layer is removed, so that the through hole in the upper layer can be positioned by utilizing the depression formed after the metal is removed, the through hole in the upper layer can be accurately positioned above the through hole in the lower layer, the metal in the through holes is mutually communicated, a metal layer does not need to be formed between the dielectric layers, the process is simpler, and metal materials are saved.

In some embodiments, the substrate and/or dielectric layer (e.g., TV1, TV2, TV 3) may be made of Undoped Silicon Glass (USG) with high gap-filling capability. Preferably, the dielectric constant of the USG is 4.2.

In some embodiments, the thickness of each dielectric layer (e.g., TV1, TV2, TV 3) may or may not be uniform, and the thickness of each dielectric layer may be set according to the design requirements of the semiconductor device.

In some embodiments, when more than one stacked layer is formed, in the stacked layers adjacent in front and behind, the aperture of the first through-hole of the succeeding stacked layer is set to be different from the aperture of the first through-hole of the preceding stacked layer.

For example, in forming the upper and lower two stacked structures shown in fig. 4, the aperture of the first through-hole of the upper stacked structure is larger than the aperture of the first through-hole of the lower stacked structure. Preferably, the aperture of the upper first through hole is 1.1 to 1.5 times the aperture of the lower first through hole.

Similarly, the aperture of the first through hole of the upper stacked structure may be smaller than the aperture of the first through hole of the lower stacked structure.

In the scheme, the key process parameters (CD) of the through holes which are overlapped later in the process can be set more conveniently by setting the first through holes with different apertures, so that the through holes can be positioned and communicated conveniently.

Preferably, after the first via is formed in the upper stacked structure by using an etching (Etch) process, the bottom edge of the first via is made to stay at the position of the upper surface of the insulating layer of the lower stacked structure by setting etching process parameters.

In some embodiments, a chemical mechanical polishing of the insulating layer is used to remove a portion of the first metal 12 on top of the first metal 12, so that the top surface of the first metal 12 is lowered to a predetermined location below the insulating layer. Specifically, as shown in fig. 3 and 4, the first insulating layer (SIN 1) and/or the second insulating layer (SIN 2) are polished by using a chemical mechanical polishing process, and a portion of the first metal 12 at the top end of the first via hole 10 is removed by adjusting the polishing pressure, so that the top surface of the first metal 12 is lower than the upper surface (first target surface) of the insulating layer, thereby forming the first recess 13. The first via hole 10 stacked above is provided with a location by the first recess 13, and when the first metal 12 is deposited into the first via hole 10 of the upper layer, a portion of the first metal 12 is entered into the first via hole 10 of the lower layer, thereby forming a more stable electrical connection.

Preferably, the chemical mechanical polishing process includes a main polishing step and an over-polishing step. Specifically, in the main polishing step, a polishing slurry adapted to the first metal 12 is used to polish the insulating layer (e.g., SIN1, SIN 2), and the main polishing step is completed by an end-point detection method. After the main polishing step is completed, the main polishing step is performed, i.e., the etching reaction is continued on the first metal 12, so that the top surface of the first metal 12 is lower than the predetermined position below the insulating layer (e.g., SIN1, SIN 2).

Preferably, the chemical etching effect in the chemical mechanical polishing process is more obvious by controlling the process conditions, such as setting the pressure between the wafer box polishing pads and adjusting the concentration of the grinding liquid.

In some embodiments, when the cmp process removes the first metal 12, the top surface of the first metal is located at a predetermined position between the upper and lower surfaces of the insulating layer. Specifically, as shown in fig. 3 and 4, the top surface of the first metal 12 in the lower stacked layer is located between the upper and lower surfaces of the first insulating layer (SIN 1), and/or the top surface of the first metal 12 in the upper stacked layer is located between the upper and lower surfaces of the second insulating layer (SIN 2).

In some embodiments, at least one of the first metal 12 and the second metal 22 is tungsten. By using the metal tungsten as an electric communication material, the top of the tungsten metal is conveniently removed by a chemical mechanical polishing process while the electric connection effect is ensured.

In some embodiments, the first insulating layer (SIN 1) and/or the second insulating layer (SIN 2) is an insulating dielectric layer composed of silicon nitride. In some embodiments, the first via 10 is formed using a dry etching process, and the etching operation is stopped at the upper surface of the first metal interconnection layer (TM 1) and/or the upper surface of the insulating layer (e.g., SIN1, SIN 2) by controlling a selection ratio in the etching process.

In some embodiments, the second via 20 may be formed by using a dry etching process, and the etching operation may be stopped on the upper surface of the insulating layer (such as SIN2 in fig. 2) connected to the top dielectric layer (TV 3) by controlling the selection ratio in the etching process.

Preferably, the parameters of the etching process include: the laser wavelength is 355-400 nm, the laser pulse width is less than 12ps, the laser frequency is 1800-2000 kHz, the power is 2.5-4W, the scanning speed is 1400-1800 mm/s, and the aperture of the etched first through hole 10 is 1-2 mu m.

Based on the same invention concept, the present specification further provides a wafer, where the wafer includes a substrate, metal interconnection layers located on two sides, and at least one stacked layer and a top dielectric layer located between the metal interconnection layers, the top dielectric layer is located on an upper surface of the uppermost stacked layer, and a plurality of through holes are provided in the stacked layer and the top dielectric layer, and are used for interconnecting the metal interconnection layers on the two sides. That is, the wafer has a stacked structure sequentially including a first metal interconnection layer (a lowermost metal interconnection layer of the wafer, such as TM1 in fig. 2), at least one stacked layer (stacked layers formed in pairs of TV1 and SIN1 in fig. 2, and TV2 and SIN 2), a top dielectric layer (TV 3 in fig. 2), and a second metal interconnection layer (an uppermost metal interconnection layer of the wafer, such as MT in fig. 2), from an upper surface of the substrate, wherein the stacked layer has a structure formed by sequentially forming an intermediate dielectric layer and an insulating layer formed on an upper surface of the intermediate dielectric layer; and a plurality of stacked vias (such as the first vias 12 in fig. 2) for interconnecting between the first metal interconnection layer and the second metal interconnection layer, wherein the stacked vias are formed by using the self-aligned stacked via processing method according to any one of the above solutions.

The beneficial effects of the above wafer can be the effects of the self-aligned stacked via processing method in the foregoing embodiments, which are not described herein again.

Based on the same inventive concept, the present specification further provides a semiconductor isolator, as shown in fig. 2 and 3, comprising:

the semiconductor isolator comprises a substrate, a first metal interconnection layer (such as TM 1), at least one stacked layer (such as a stacked layer formed by TV1 and SIN1, TV2 and SIN 2), a top dielectric layer (shown in a figure TV 3) and a second metal interconnection layer (such as MT) which are sequentially stacked on the upper surface of the substrate, wherein the first metal interconnection layer and the second metal interconnection layer are metal interconnection layers of the isolator and are used for being communicated with external devices, the stacked layer between the two metal interconnection layers and the top dielectric layer positioned on the stacked layer form a dielectric layer structure in the semiconductor isolator, and in addition, a plurality of stacked through holes (such as a first through hole 10 in the stacked layer and a second through hole 20 in the top dielectric layer) which are communicated with each other and stacked with each other are further arranged in the stacked layer and the top dielectric layer, and the stacked through holes are formed by adopting a self-aligned stacked through hole processing method in any one of the above schemes.

According to the semiconductor isolator, the plurality of stacked layers and the top-layer dielectric layer form the isolated middle layer, the isolation effect is guaranteed, and meanwhile the through holes in the layers penetrate through the stacked structures, so that metal in the through holes can be stably and electrically connected with the metal interconnection layers on the two sides, and the two sides of the semiconductor isolator are electrically connected.

In some embodiments, the intermediate dielectric layer includes a silicon oxide layer, and in particular, the first intermediate dielectric layer (TV 1) and/or the second intermediate dielectric layer (TV 2) as shown in fig. 2 and 3 includes a silicon oxide layer. It should be noted that the top dielectric layer (TV 3) shown in fig. 2 and 3 may also include a silicon oxide layer.

Preferably, the material of the dielectric layers (e.g., TV1, TV2, TV 3) can be selected from Undoped Silicate Glass (USG) with high gap filling capability. More preferably, the dielectric constant of the USG is 4.2.

The insulating layer includes a silicon-depleted layer. Specifically, the first insulating layer (SIN 1) and/or the second insulating layer (SIN 2) shown in fig. 2 and 3 include a silicon nitride layer.

In some embodiments, the silicon oxide layer has a thickness of 3 to 8 μm.

In some embodiments, the silicon nitride layer has a thickness of 1 to 3 μm.

Based on the same inventive concept, the present specification further provides a method for manufacturing a semiconductor isolator, wherein a semiconductor body of the isolator is manufactured by using a self-aligned stacked via processing method according to any one of the above-mentioned schemes, which is not described herein again, and the semiconductor body includes a substrate, a first metal interconnection layer, at least one stacked layer, a top dielectric layer, a second metal interconnection layer, and a plurality of stacked vias interconnected between the first metal interconnection layer and the second metal interconnection layer, which are sequentially stacked from an upper surface of the substrate;

In one embodiment, the middle dielectric layer and the top dielectric layer include silicon oxide layers, and the insulating layer includes a silicon nitride layer, and in particular, as shown in fig. 2 and 3, the silicon oxide layer is prepared to have a thickness of 3 to 8 μm using a Chemical Vapor Deposition (CVD) process. After the silicon oxide layer is deposited, a chemical mechanical polishing process is used for removing the silicon oxide layer with the top layer of 1-2 microns. The chemical vapor deposition process is continuously used to prepare a silicon nitride layer with a thickness of 1-3 μm, and an etching (Etch) process, such as a dry etching process, is used to sequentially Etch the silicon nitride layer and the silicon oxide layer to form the first through hole 10.

It should be noted that the etching end point can be located on the upper surface of the middle dielectric layer by controlling the selection ratio of the etching process; or when the silicon oxide layer is formed on the upper surface of the metal interconnection layer, the etching end point is positioned on the upper surface of the metal interconnection layer by controlling the selection ratio of the etching process.

Subsequently, metal tungsten is deposited in the first via hole 10, the upper surface of the insulating layer and the upper surface of the metal tungsten are polished using a chemical mechanical polishing process, and chemical etching is mainly performed by adjusting polishing pressure or by adjusting other process parameters, so that the upper surface of the metal tungsten is polished to a position lower than the upper surface of the insulating layer.

According to the design requirement of the semiconductor isolator, the process of depositing and forming the silicon oxide layer and the silicon nitride layer is repeated, a new silicon oxide layer structure and a new silicon nitride layer structure are stacked above the existing structure, the first through hole is etched in the stacked structure on the upper layer, and the falling point of the first through hole is controlled to be positioned right above the first through hole on the lower layer, so that the through hole is formed and used for interconnecting the metal interconnection layers on the two sides of the semiconductor isolator.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the method embodiments described later, since they correspond to the system, the description is simple, and for the relevant points, reference may be made to the partial description of the system embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of processing a self-aligned stacked via, comprising:

2. The self-aligned stacked via processing method according to claim 1, wherein when there is more than one of the stacked layers, in the stacked layers adjacent in the front and rear, an aperture of the first via of the succeeding one of the stacked layers is set to be different from an aperture of the first via of the preceding one of the stacked layers;

and/or the aperture of the second through hole is set to be different from the aperture of the first through hole adjacent to the second through hole.

3. The method according to claim 2, wherein the diameter of the first through hole of the next stacked layer is 1.1 to 1.5 times the diameter of the first through hole of the previous stacked layer.

4. The method of claim 1, wherein after depositing the first metal into the first via, when the top surface of the first metal is not located at a predetermined position under the first target surface, the insulating layer is subjected to a chemical mechanical polishing process to remove a portion of the first metal at a top end position of the first via, so that the top surface of the first metal is located at a predetermined position under the first target surface.

5. The method of claim 4, wherein the CMP process comprises a main polishing step of polishing the insulating layer with a polishing slurry compatible with the first metal and completing the main polishing step by an end-point detection method, and an over-polishing step of continuing a corrosion reaction on the first metal after the main polishing step is completed so that a top surface of the first metal is lower than a predetermined position below the first target surface.

6. The method of claim 1, wherein the top surface of the first metal is located at a predetermined position between the top and bottom surfaces of the insulating layer.

7. The self-aligned stacked via processing method of claim 1, wherein the first metal and/or the second metal comprises tungsten;

8. The self-aligned stack via processing method of claim 1, further comprising: and forming the first through hole and/or the second through hole by using a dry etching process, and stopping etching operation on the upper surface of the first metal interconnection layer and/or the upper surface of the insulating layer by controlling the selection ratio in the etching process.

9. The method of claim 8, wherein in the etching process, the laser wavelength is 355-400 nm, the laser pulse width is less than 12ps, the laser frequency is 1800-2000 kHz, the power is 2.5-4W, the scanning speed is 1400-1800 mm/s, and the aperture of the first through hole is 1-2 μm.

10. A wafer, comprising:

and a plurality of stacked vias for interconnecting between the first metal interconnection layer and the second metal interconnection layer, the stacked vias being formed by using the self-aligned stacked via processing method according to any one of claims 1 to 9.

11. A semiconductor isolator, comprising:

a substrate;

and a plurality of stacked vias interconnected between the first metal interconnection layer and the second metal interconnection layer, the stacked vias being formed by the self-aligned stacked via processing method according to any one of claims 1 to 9.

12. The semiconductor isolator of claim 11, wherein the intermediate dielectric layer and/or the top dielectric layer comprises a silicon oxide layer having a dielectric constant of 4.2;

and/or the insulating layer comprises a silicon nitride layer.

13. The semiconductor separator according to claim 12, wherein the thickness of the silicon oxide layer is 3 to 8 μm;

and/or the thickness of the silicon nitride layer is 1-3 mu m.

14. A method for manufacturing a semiconductor isolator, comprising:

preparing a semiconductor body of an isolator by using the self-aligned stacked via processing method as claimed in any one of claims 1 to 9, the semiconductor body comprising a substrate, a first metal interconnection layer, at least one stacked layer, a top dielectric layer and a second metal interconnection layer which are sequentially stacked from the upper surface of the substrate, and a plurality of stacked vias interconnected between the first metal interconnection layer and the second metal interconnection layer;