CN115295034A - Interval oscillator, method for controlling same, and memory provided with same - Google Patents

Interval oscillator, method for controlling same, and memory provided with same Download PDF

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Publication number
CN115295034A
CN115295034A CN202210949585.6A CN202210949585A CN115295034A CN 115295034 A CN115295034 A CN 115295034A CN 202210949585 A CN202210949585 A CN 202210949585A CN 115295034 A CN115295034 A CN 115295034A
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signal
timing
oscillator
clock
clock signal
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赖荣钦
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Dongxin Semiconductor Co ltd
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Dongxin Semiconductor Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
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Abstract

The invention provides an interval oscillator, a control method thereof and a memory, which can obtain a predetermined time interval and eliminate time difference caused by delay. The interval oscillator includes: a clock generator generating a clock signal of a specific frequency; a timer for counting the clock signal and outputting a timing signal; a start signal generation unit that generates a start signal for starting an operation of the space oscillator by triggering a timing signal for which level conversion does not occur to be inverted by a signal edge corresponding to a first timing of the clock signal; and a stop signal generation unit that generates a stop signal for stopping the operation of the space oscillator by using a timing signal in which a level transition occurs at a signal edge corresponding to a second timing of the clock signal, the second timing being a timing at which a predetermined count number of clock cycles has elapsed after the first timing, and a time interval between the start signal and the stop signal being equal to a predetermined time interval.

Description

Interval oscillator, method for controlling same, and memory provided with same
Technical Field
The present invention relates to a block oscillator, and more particularly, to a block oscillator capable of eliminating a delay time difference to obtain an accurate time interval. The invention also relates to a control method of the interval oscillator and a memory with the interval oscillator.
Background
As a Random Access Memory (RAM), there are classified into an SRAM (static random access memory) and a DRAM (dynamic random access memory). DRAM uses capacitors to store more or less charge to store data, requires a timed refresh circuit to overcome the problem of capacitor leakage, and is commonly used in main memories with large capacity, such as computers, smart phones, server memories, and the like. The DRAM is further classified into SDRAM, DDR SDRAM, RDRAM, etc.
Among them, SDRAM (Synchronous DRAM) is a clock Synchronous memory that operates based on a clock signal from a processor. The command signal for defining the action and the address signal for specifying the memory cell are sent in parallel and synchronized with the rising edge of the clock signal. DDR SDRAM (double data rate SDRAM; hereinafter abbreviated as DDR) is a memory having a double data transfer rate, and data can be transferred at both rising and falling edges of a clock signal, that is, the data transfer rate is twice the frequency of the clock signal, and the transfer performance is better than that of the conventional SDRAM due to the increase in speed. DDR is widely used in various intelligent products such as tablet computers, set-top boxes, automotive electronics, digital televisions, and the like due to its higher data rate, lower energy consumption, and higher density.
On the other hand, LPDDR (Low Power DDR: low Power DDR) is used for mobile electronic products because of its advantages such as Low Power consumption and small size. Moreover, the energy consumption is obviously reduced, and the service life of the battery is effectively prolonged.
The initialization process of the above SDRAM, DDR, etc. includes a normal Mode Register MRS (Mode Register Set) or an Extended Mode Register EMRS (Extended Mode Registers Set) for setting an operation Mode thereof. Data in the MRS mode register controls CAS (Column Address strobe) Delay, burst length, burst sequence, test mode, DLL (Delay-locked Loop) reset, and the like, and supports various applications such as SDRAM and DDR. The default value of the mode register is not defined, so the value of the mode register must be set to a specified timing specification after power-up.
On the other hand, a Bi-directional Data Strobe (Bi-directional Data Strobe) signal, which is used to control the read/write timing of the Data signal DQ, accurately distinguishes each transmission cycle within one clock cycle, and is convenient for a receiving party to accurately receive Data. However, in DDR operation, the internal true synchronous clock is the clock signal CK instead of DQS, and data is transferred and stored internally, which also needs to be desynchronized with the clock signal CK (the internal clock is slower than the external clock), so that all DQ signals are required to be synchronous, and a certain relation is kept with the clock signal CK, so that the delay between DQS and CK signals needs to be controlled.
For this reason, a DQS interval oscillator is provided in DDR and the like to generate a desired time interval. The DQS interval oscillator is started when a start signal from a microprocessor or the like is received, and stops operating when a timer inside the DQS interval oscillator reaches a predetermined count, thereby generating a desired time interval.
However, the DQS interval oscillator takes a certain amount of time from the receipt of a command signal to start or stop until the start and stop actions are actually made. That is, a delay inherent to a component or a circuit in the DQS interval oscillator, a delay in signal transmission, or the like causes a constant time difference between a time interval generated by the DQS interval oscillator and an actually desired time interval, and thus the timing generated by the DQS interval oscillator cannot accurately reach a desired value, that is, a predetermined time interval cannot be accurately reflected.
Disclosure of Invention
The present invention has been made to solve the above problems, and an object of the present invention is to provide a gap oscillator that can obtain an accurate time gap by eliminating the time difference caused by the delay.
A first aspect of the present invention is directed to a block oscillator for acquiring a predetermined time interval, including:
a clock generator generating a clock signal of a specific frequency;
a timer that counts the clock signal generated by the clock generator and outputs a timing signal that causes a level transition when a count value of the clock signal reaches a predetermined count value corresponding to the predetermined time interval set in advance in the timer;
an enable signal generating unit that generates an enable signal for starting the operation of the space oscillator by triggering the inversion of the timing signal, in which the level transition does not occur, using a signal edge corresponding to a first timing of the clock signal; and
a stop signal generating unit that generates a stop signal for stopping the intermittent oscillator by using the timing signal whose level has been shifted triggered by a signal edge corresponding to a second timing of the clock signal, the second timing being a timing at which the predetermined count value of clock cycles has elapsed after the first timing,
the time interval between the start signal and the stop signal is equal to the prescribed time interval.
In a second aspect of the present invention, in the space oscillator according to the first aspect of the present invention, the timing signal is at a low level when the count value of the clock signal has not reached the predetermined count value, and the timing signal changes from the low level to the high level when the count value of the clock signal has reached the predetermined count value.
In a third aspect of the present invention, in the intermittent oscillator according to the second aspect of the present invention, the clock signal is maintained at a high level for one or more clock cycles, and then is changed to a low level, and a signal for stopping the operation is output to the clock generator.
In a fourth aspect of the present invention, in the interval oscillator according to any one of the first to third aspects of the present invention, the first timing is a first rising edge of the clock signal.
A fifth aspect of the present invention is the space oscillator according to any one of the first to third aspects of the present invention, wherein the space oscillator is provided in a DDR (double data rate synchronous dynamic random access memory) and generates the predetermined time interval for a DQS (data strobe) signal.
A sixth aspect of the present invention is directed to a control method of a space oscillator for acquiring a prescribed time interval, comprising the steps of:
generating a clock signal of a specific frequency by using a clock generator;
counting the clock signal generated by the clock generator by a timer and outputting a timing signal that causes a level transition when a count value of the clock signal reaches a predetermined count value corresponding to the predetermined time interval set in advance in the timer;
generating a start signal for starting the operation of the interval oscillator by using a signal edge corresponding to a first timing of the clock signal to trigger the inversion of the timing signal in which the level transition does not occur; and
generating a stop signal for stopping the intermittent oscillator by using the timing signal whose level has been shifted triggered by a signal edge corresponding to a second timing of the clock signal, the second timing being a timing at which the predetermined count value is a clock cycle after the first timing,
such that the time interval between the start signal and the stop signal is equal to the prescribed time interval.
In a seventh aspect of the present invention, in the method for controlling a space oscillator according to the sixth aspect of the present invention, the timing signal is at a low level when the count value of the clock signal has not reached the predetermined count value, and the timing signal changes from the low level to the high level when the count value of the clock signal has reached the predetermined count value.
An eighth aspect of the present invention is the method for controlling a space oscillator according to the seventh aspect of the present invention, wherein the clock generator is turned to a low level after the high level of the clock signal is maintained for one or more clock cycles, and outputs a signal for stopping the operation of the clock generator.
In a ninth aspect of the present invention, in the method for controlling a spaced oscillator according to any one of the sixth to eighth aspects of the present invention, the first timing is a first rising edge of the clock signal.
A tenth aspect of the present invention is directed to a memory including at least the spaced oscillator according to any one of the first to fifth aspects of the present invention.
Effects of the invention
According to the interval oscillator of the present invention, the start signal generating section generates the start signal for starting the interval oscillator at the timing corresponding to the signal edge of the clock signal based on the clock signal, and the stop signal generating section generates the stop signal for stopping the interval oscillator at the timing corresponding to the signal edge of the clock signal based on the clock signal, so that the time interval between the start signal and the stop signal is equal to the predetermined time interval. Therefore, the time difference between the generated time interval and the actually desired time interval due to the inherent delay of the elements or circuits in the interval oscillator, the delay of the signal transmission, and the like can be eliminated, so that the timing recorded by the interval oscillator can accurately reflect the timing set in the timer.
Drawings
Fig. 1 is a block diagram showing the basic structure of a DQS interval oscillator.
Figure 2 is a timing diagram illustrating a DQS interval oscillator.
Fig. 3 is a block diagram showing the basic structure of the DQS interval oscillator according to embodiment 1 of the present invention.
Fig. 4 is a timing chart showing the DQS interval oscillator according to embodiment 1 of the present invention.
Fig. 5 is a flowchart showing a method of controlling the DQS interval oscillator according to embodiment 1 of the present invention.
Detailed Description
The present invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The dimensions and relative sizes of layers and regions may be exaggerated in the figures for clarity.
Spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features.
Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms are to be understood as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The interval oscillator according to the present invention is exemplified by a DQS interval oscillator, which is applied to DDR to generate a predetermined time interval for a DQS signal. The invention can of course also be applied to other types of interval oscillators as long as they are intended to generate the desired time intervals.
Therefore, the basic structure of the DQS interval oscillator and its signal timing will be explained first. Figure 1 is a block diagram of the basic structure of a DQS interval oscillator 100. Figure 2 is a timing diagram of the DQS interval oscillator 100.
As shown in the upper part of fig. 1, the DQS interval oscillator 100 includes a clock generator 10, a counter 20, and a timer 30. The clock generator 10 generates a clock signal of a specific frequency for the timer 30. Here, the detailed structure of the clock generator 10 is shown in the lower part of fig. 1, and receives a START signal START _ OSC of interval oscillator inputted from the outside, for example, a microprocessor (not shown), for instructing the DQS interval oscillator 100 and the timer 30 to START operating. Clock generator 10 also receives inputs for a system clock signal CLK and a signal DQS _ SETb _ p, which will be described later with respect to DQS _ SETb _ p. The clock generator 10 outputs the down-converted clock signal DCNT _ CK according to the input system clock signal CLK. In the present invention, the frequency of the clock signal DCNT _ CK is 1/16 of the frequency of the system clock signal CLK, which is only an example and can be set appropriately according to actual requirements. The logic circuit configuration shown in the lower part of fig. 1 is also an example of the clock generator 10, and the clock generator 10 may have any configuration as long as it can generate the clock signal DCNT _ CK of a predetermined frequency from the input interval oscillator START signal START _ OSC, the system clock signal CLK, and the signal DQS _ SETb _ p.
The clock signal DCNT _ CK output from the clock generator 10 is input to the counter 20. The counter 20 counts the input clock signal DCNT _ CK. In the present invention, the counter 20 outputs a clock signal count value DCNT <7:0> corresponding to the first 8-bit data 0 to 7 to the timer 30, taking the first 8-bit data as an example.
The timer 30 compares the received clock signal count value DCNT <7:0> with a preset setting signal DSET <7:0> corresponding to the first 8-bit data 0 to 7, and outputs a timing signal DQS _ SET according to the comparison result. The middle of fig. 1 shows a detailed structure of the timer 30. For example, for bit 1, the count value DCNT <0> is compared with its corresponding SET value DSET <0>, for bit 2, the count value DCNT <1> is compared with its corresponding SET value DSET <1>, … …, and for bit 8, the count value DCNT <7> is compared with its corresponding SET value DSET <7>, and the timing signal DQS _ SET is output via the illustrated exemplary logic circuit, and the signal DQS _ SETb _ p is output in accordance with the timing signal DQS _ SET. Details of the timing signals DQS _ SET and DQS _ SETb _ p will be described with reference to the timing diagram of fig. 2.
Here, although the counter 20 and the timer 30 are schematically described as separate elements, the counter 20 is not essential, and may be realized by a counting function provided in the timer 30 itself.
According to the timing chart of fig. 2, the system clock signal CLK is a high-frequency clock signal, and the clock generator 10 of the interval oscillator 100 down-converts the system clock signal CLK to output the clock signal DCNT _ CK. For simplicity of explanation, fig. 2 shows only the count values DCNT <0> and DCNT <1> of the 1 st and 2 nd bits, and the illustration of DCNT <2> to DCNT <7> is omitted. In fig. 2, the timer 30 outputs a timing signal DQS _ SET that becomes high when a preset value DSET <7:0> of the count in the timer 30 is 3, that is, when the count value of the counter 20 reaches 3 that is preset. After the timing signal DQS _ SET goes high for a predetermined period of time, the timer 30 outputs a signal DQS _ SETb _ p indicating that one operation of the timer 30 is completed, thereby terminating the operation of the clock generator 10 and stopping the generation of the clock signal (as shown in fig. 1).
In fig. 2, the interval oscillator START signal START _ OSC inputted from the outside or an unillustrated microcontroller is a low level pulse. When the interval oscillator START signal START _ OSC is received, the interval oscillator 100 is powered on to START operating. But the start point of the actually measured time interval is earlier than the start point of the desired time interval due to a time delay caused by circuit elements and the like in the clock generator 10. When the count value of the counter 20 reaches 3, the timer 30 outputs the timing signal DQS _ SET at a high level, but the end point of the time interval actually measured is later than the end point of the desired time interval due to a time delay caused by circuit elements and the like within the timer 30. Therefore, the time difference caused by the above-described delay in the interval oscillator may cause the time interval actually obtained to fail to reach the desired value, and thus the accurate time interval may not be obtained.
< embodiment 1>
In order to solve the above problem, the present inventors have further provided a start signal generation unit for controlling a start signal for starting timing of the interval oscillator and a stop signal generation unit for stopping timing in addition to the configuration of the interval oscillator 100 of fig. 1, and have obtained a desired time interval by using the start signal and the stop signal.
Fig. 3 is a block diagram showing the basic structure of DQS interval oscillator 100' according to embodiment 1 of the present invention.
The basic configuration of the DQS interval oscillator 100 'of the present embodiment includes a clock generator 10', a counter 20', a timer 30', a start signal generating unit 40, and a stop signal generating unit 50. The basic structures and functions of the clock generator 10', the counter 20', and the timer 30 'shown in fig. 3 are the same as those of the clock generator 10, the counter 20, and the timer 30' shown in fig. 1, and a description thereof will not be repeated.
The DQS interval oscillator 100' of the present embodiment is different from the DQS interval oscillator 100 of fig. 1, and further includes a start signal generation unit 40 and a stop signal generation unit 50. As shown in particular in the lower part of figure 3.
The activation signal generation section 40 includes an inverter 401, a D flip-flop 402, and a pulse generator 403. The timing signal DQS _ SET generated by the timer 30 'is input to the D terminal of the D flip-flop 402 via the inverter 401, the clock signal DCNT _ CK generated by the clock generator 10' is input to the CK terminal of the D flip-flop 402, and a signal output from the Q terminal of the D flip-flop 402 is output as the START signal START after passing through the pulse generator 403.
The stop signal generating section 50 includes a D flip-flop 502 and a pulse generator 503. The timing signal DQS _ SET generated by the timer 30 'is input to the D terminal of the D flip-flop 502, the clock signal DCNT _ CK generated by the clock generator 10' is input to the CK terminal of the D flip-flop 502, and a signal output from the Q terminal of the D flip-flop 502 is output as the STOP signal STOP via the pulse generator 503.
Next, the timing of the START signal START and the STOP signal STOP will be described with reference to fig. 4. The diagrams of CLK, DCNT _ CK, DCNT <0>, DCNT <1>, DCNT <7:0>, DSET <7:0>, START _ OSC, DQS _ SET in FIG. 4 and the effect of the time difference due to the delay are the same as in FIG. 2 and therefore will not be repeated.
In the present embodiment, the START signal START is a signal for starting the timing of the DQS interval oscillator 100', which is generated based on the timing signal DQS _ SET outputted from the timer 30' and the clock signal DCNT _ CK outputted from the clock generator 10', that is, a signal for determining the START timing of the time interval to be generated. As shown in fig. 3, the timing signal DQS _ SET is input to the D terminal of the D flip-flop 402 via an inverter 401. The timing signal DQS _ SET is a signal generated by the timer 30' counting the clock signal DCNT _ CK. According to the present embodiment, when the count value of the clock signal DCNT _ CK is less than the predetermined value (3 in the present embodiment), the clock signal DQS _ SET is at the low level. When the count value of the clock signal DCNT _ CK reaches the predetermined value 3, the timing signal DQS _ SET is level-shifted from low level to high level.
On the other hand, since the clock signal DCNT _ CK is input to the CK terminal of the D flip-flop 402 as a synchronous clock signal, as shown in fig. 4, during a period in which the clock signal DQS _ SET is at a low level, that is, before the count value of the clock signal DCNT _ CK reaches a predetermined value, the first rising edge of the clock signal DCNT _ CK (corresponding to the timing between "0" and "1" of DCNT <0>, DCNT <7:0 >) triggers inversion of the low-level clock signal DQS _ SET by a synchronous action of the clock signal DCNT _ CK, and a rising edge (i.e., a high level) of the pulse signal of the START signal START is generated. The START signal START STARTs the timing of DQS interval oscillator 100'.
In order to obtain a desired time interval, the present embodiment further generates a STOP signal STOP to STOP the timing of the DQS interval oscillator 100' when a predetermined time interval is reached.
In the present embodiment, the STOP signal STOP is a signal for stopping the timing of the DQS interval oscillator 100', which is generated based on the timing signal DQS _ SET outputted from the timer 30' and the clock signal DCNT _ CK outputted from the clock generator 10', that is, a signal for determining the end timing of the time interval to be generated. As shown in fig. 3, the timing signal DQS _ SET is directly input to the D terminal of the D flip-flop 502.
On the other hand, since the clock signal DCNT _ CK is input as a synchronous clock signal to the CK terminal of the D flip-flop 502, as shown in fig. 4, after a predetermined time interval (i.e., 3 clock signal cycles) has elapsed since the rising edge of the START signal START, the count value of the clock signal DCNT _ CK exceeds 3, and thus the clock signal DQS _ SET becomes high, and at this time, the rising edge of the clock signal DCNT _ CK (corresponding to one falling edge of DCNT <0> and "3" of DCNT <7:0 >) triggers the high-level clock signal DQS _ SET by the synchronous action of the clock signal DCNT _ CK, and the rising edge of the pulse signal of the STOP signal STOP (i.e., high level) is generated. The STOP signal STOP STOPs the timing of DQS interval oscillator 100'.
The time interval between the rising edge of the START signal START and the rising edge of the STOP signal STOP thus obtained is equal to the desired time interval. The DQS interval oscillator 100' is able to accurately generate the desired time interval because the effects of time delays in the clock generator 10' and the timer 30' are eliminated, i.e., the actual measured time interval is the desired time interval.
In this embodiment, the START signal START is used to START the timing of the DQS interval oscillator 100', and the STOP signal STOP is used to STOP the timing of the DQS interval oscillator 100'. Before the count value of the clock signal DCNT _ CK by the counter 20' reaches a desired value, the timing signal DQS _ SET, which is at a low level at this time, is triggered to invert with synchronization of the clock signal DCNT _ CK to generate a pulse of the START signal START, and after the count value of the clock signal DCNT _ CK reaches the desired value, the timing signal DQS _ SET, which is at a high level at this time, is triggered with synchronization of the clock signal DCNT _ CK to generate a pulse of the STOP signal STOP, so that the time interval between the START signal START and the STOP signal STOP is exactly equal to a desired time interval. After the high-level clock signal DQS _ SET is maintained for a predetermined time, the output signal DQS _ SETb _ p stops the operation of the clock generator 10'. In fig. 4, the period of time for which the timing signal DQS _ SET is maintained at the high level is equivalent to one cycle of the clock signal DCNT _ CK, but may be a plurality of cycles, or may have other time lengths, and may be SET according to actual conditions.
In the present embodiment, the clock signal DQS _ SET changes from low level to high level when the count value of the clock signal DCNT _ CK reaches a predetermined value, but may change from high level to low level and be SET according to the needs of the system circuit.
In this embodiment, during the period when the clock signal DQS _ SET is at a low level, the first rising edge of the clock signal DCNT _ CK (corresponding to the timing between "0" and "1" of DCNT <7:0 >) triggers the inversion of the clock signal DQS _ SET, thereby generating a pulse of the START signal START at the first rising edge of the clock signal DCNT _ CK.
Then, during a period in which the clock signal DQS _ SET is at the high level, the clock signal DQS _ SET is triggered at a rising edge of the clock signal DCNT _ CK at which a predetermined count value (here, 3) has elapsed (corresponding to a timing between "3" of DCNT <7:0> and "4" not shown in fig. 4), and a pulse of the STOP signal STOP is generated at the rising edge of the clock signal DCNT _ CK.
Therefore, the timing signal DQS _ SET, the START signal START, and the STOP signal STOP are synchronized by the clock signal DCNT _ CK, so that a delay time difference caused by circuit elements can be avoided, and the DQS interval oscillator can provide a desired time interval.
Fig. 5 is a flowchart of a method for controlling DQS interval oscillator 100' according to embodiment 1 of the present invention.
In step S1, the clock generator 100' generates a down-converted clock signal DCNT _ CK according to the system clock signal CLK.
In step S2, the counter 20' counts the clock signal DCNT _ CK and obtains a count value.
In step S3, the timer 30' compares the count value with a predetermined count value (3 cycles of the clock signal DCNT _ CK in the present embodiment) corresponding to a desired time interval, and determines whether or not the count value has reached the predetermined count value. If the count value is not reached, that is, if the count value is smaller than the predetermined count value (yes in step S3), the low-level timing signal DQS _ SET is output (step S4), and the process returns to step S2 to continue counting the clock signals.
Then, at step S5, on the first rising edge of the clock signal DCNT _ CK (referred to as "first timing" here as shown in fig. 4), the START signal generating section 40 in fig. 3 triggers the inversion of the low-level timing signal DQS _ SET, thereby generating a pulse of the START signal START at step S6.
When the count value of the clock signal DCNT _ CK reaches the predetermined count value in step S3, that is, when the count value is equal to or greater than the predetermined count value (no in step S3), the low-level clock signal DQS _ SET goes high (step S7).
Then, at step S8, the high-level clock signal DQS _ SET is triggered at the rising edge of the clock signal DCNT _ CK corresponding to the second timing 3 clock cycles, which is a predetermined time interval from the first timing, and a pulse of the STOP signal STOP is generated at step S9.
Thus, the time interval between the rising edge of the pulse of the START signal START and the rising edge of the pulse of the STOP signal STOP is the desired time interval (3 clock cycles) in steps S6 and S9, and therefore, the time interval thus generated eliminates the influence of the time difference due to the delay, and the desired time interval can be accurately generated (step S10).
When the high-level clock signal DQS _ SET continues for a predetermined time, the present embodiment SETs the predetermined time to one cycle of the clock signal DCNT _ CK as shown in fig. 4, and in step S11, generates the signal DQS _ SETb _ p to stop the clock generator 10' from generating the clock signal.
The method of controlling the DQS interval oscillator 100 'according to embodiment 1 for obtaining a predetermined time interval includes the steps of generating a clock signal DCNT _ CK of a specific frequency by a clock generator 10', counting the clock signal DCNT _ CK by a timer, outputting a timing signal DQS _ SET of a low level when a count value does not reach a predetermined count value corresponding to the predetermined time interval, outputting a timing signal DQS _ SET of a high level when the count value reaches the predetermined count value, generating a START signal START for starting the timing of the DQS interval oscillator 100 'by triggering the inversion of the timing signal DQS _ SET of the low level by a rising edge corresponding to a first timing of the clock signal DCNT _ CK, and generating a STOP signal START for stopping the timing of the DQS interval oscillator 100' by triggering the timing signal DQS _ SET of the high level by a rising edge corresponding to a second timing of the clock signal DCNT _ CK which is the predetermined time interval from the first timing so that the time interval is the predetermined time interval.
Therefore, the time difference between the generated time interval and the actually desired time interval due to the inherent delay of the elements or circuits in the interval oscillator, the delay of the signal transmission, and the like can be eliminated, so that the timing recorded by the interval oscillator can accurately reflect the timing set in the timer.
The present invention has been described in detail, but the above embodiments are merely examples of all embodiments, and the present invention is not limited thereto. The present invention may freely combine the respective embodiments, may modify any of the components of the respective embodiments, or may omit any of the components of the respective embodiments within the scope of the present invention.
Industrial applicability of the invention
The interval oscillator and the control method thereof can be applied to the SRAM comprising SDR SRAM, DDR SRAM, QDR SRAM and ZBT SRAM; DRAM including SDRAM, DDR DRAM, RDRAM; ROM, and the like.

Claims (10)

1. A gap oscillator for obtaining a specified time gap, comprising:
a clock generator generating a clock signal of a specific frequency;
a timer that counts the clock signal generated by the clock generator and outputs a timing signal that causes a level transition when a count value of the clock signal reaches a predetermined count value corresponding to the predetermined time interval set in advance in the timer;
an enable signal generating unit that generates an enable signal for starting the operation of the space oscillator by triggering the inversion of the timing signal, in which the level transition does not occur, using a signal edge corresponding to a first timing of the clock signal; and
a stop signal generating unit that generates a stop signal for stopping the intermittent oscillator by using the timing signal whose level has been shifted triggered by a signal edge corresponding to a second timing of the clock signal, the second timing being a timing at which the predetermined count value of clock cycles has elapsed after the first timing,
the time interval between the start signal and the stop signal is equal to the prescribed time interval.
2. The spaced oscillator of claim 1,
the clock signal is at a low level when the count value of the clock signal does not reach the predetermined count value, and the clock signal changes from the low level to the high level when the count value of the clock signal reaches the predetermined count value.
3. The spaced oscillator of claim 2,
and a control unit which changes to a low level after the high level of the timing signal is maintained for one or more clock cycles, and outputs a signal for stopping the operation of the clock generator.
4. The interval oscillator of any one of claims 1 to 3,
the first timing is a first rising edge of the clock signal.
5. The interval oscillator of any one of claims 1 to 3,
the interval oscillator is provided in a DDR (double data rate synchronous dynamic random access memory) and generates the predetermined time interval for a DQS (data strobe) signal.
6. A method for controlling a gap oscillator for obtaining a prescribed time interval, comprising the steps of:
generating a clock signal of a specific frequency by using a clock generator;
counting the clock signal generated by the clock generator by using a timer and outputting a timing signal that causes level transition when a count value of the clock signal reaches a predetermined count value corresponding to the predetermined time interval set in advance in the timer;
generating a start signal for starting the operation of the interval oscillator by inverting the timing signal whose level conversion has not occurred by using a signal edge corresponding to a first timing of the clock signal; and
generating a stop signal for stopping the intermittent oscillator by using the timing signal whose level has been shifted triggered by a signal edge corresponding to a second timing of the clock signal, the second timing being a timing at which the predetermined count value is a clock cycle after the first timing,
such that the time interval between the start signal and the stop signal is equal to the prescribed time interval.
7. The method of controlling a spaced oscillator according to claim 6,
the clock signal is at a low level when the count value of the clock signal does not reach the predetermined count value, and the clock signal changes from the low level to the high level when the count value of the clock signal reaches the predetermined count value.
8. The method of controlling a spaced oscillator according to claim 7,
and a control unit which changes to a low level after the high level of the timing signal is maintained for one or more clock cycles, and outputs a signal for stopping the operation of the clock generator.
9. The method of controlling a spaced oscillator according to any one of claims 6 to 8,
the first timing is a first rising edge of the clock signal.
10. A memory, characterized in that,
comprising at least a spaced oscillator as claimed in any one of claims 1 to 5.
CN202210949585.6A 2022-08-09 2022-08-09 Interval oscillator, method for controlling same, and memory provided with same Pending CN115295034A (en)

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