CN115293079A

CN115293079A - Generation method and device, verification method and device, electronic device and storage medium

Info

Publication number: CN115293079A
Application number: CN202210985336.2A
Authority: CN
Inventors: 耿鑫钰; 潘于; 高红莉; 刘静
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-08-17
Filing date: 2022-08-17
Publication date: 2022-11-04

Abstract

A black box file generation method and device, a verification method and device, an electronic device and a computer readable storage medium are provided. The black box file is used for verifying the object path in the integrated circuit design, and the generation method of the black box file comprises the following steps: acquiring hierarchical structure information of an integrated circuit design, wherein the hierarchical structure information comprises structural information and module information of the integrated circuit design; determining a plurality of first circuit modules in the integrated circuit design that are associated with the object path using the hierarchy information; and generating the black box file according to module information of a second circuit module in the integrated circuit design, wherein the second circuit module is a module except for the plurality of first circuit modules in the integrated circuit design. The method for generating the black box file can improve the complicated steps of simplifying the generation of the black box file and improve the generation efficiency of the black box file.

Description

Generation method and device, verification method and device, electronic device and storage medium

Technical Field

The embodiment of the disclosure relates to a black box file generation method and device, a black box file verification method and device, electronic equipment and a storage medium.

Background

Verification is the work of simulating and testing the aspects of chip function design, chip process and the like before the production of chips, and becomes an important component part of the chip research and development design industry along with the continuous increase of the scale of the chips.

Disclosure of Invention

At least one embodiment of the present disclosure provides a method for generating a black box file, where the black box file is used to verify an object path in an integrated circuit design, and the method includes: acquiring hierarchical structure information of an integrated circuit design, wherein the hierarchical structure information comprises structural information and module information of the integrated circuit design; determining a plurality of first circuit modules in the integrated circuit design that are associated with the object path using the hierarchy information; and generating a black box file according to module information of a second circuit module in the integrated circuit design, wherein the second circuit module is a module except the plurality of first circuit modules in the integrated circuit design.

For example, in the generation method provided by an embodiment of the present disclosure, the plurality of first circuit modules include a source module, a destination module, and at least one intermediate module that the object path passes through, where the source module is a circuit module where a start point of the object path is located, and the destination module is a circuit module where an end point of the object path is located.

For example, in a generating method provided by an embodiment of the present disclosure, the number of object paths is greater than or equal to 2, and the determining, using the hierarchical structure information, a plurality of first circuit modules related to the object paths in the integrated circuit design includes: determining a source module and a destination module of each object path; using the hierarchical structure information to obtain at least one intermediate module passed by each object path; and acquiring a union of a source module, a destination module and at least one intermediate module comprising the object path to obtain a plurality of first circuit modules.

For example, in a generating method provided by an embodiment of the present disclosure, using the hierarchical structure information to obtain at least one intermediate module that each object path passes through includes: acquiring an intermediate module description file of the integrated circuit design; and acquiring at least one intermediate module passed by each object path according to the intermediate module description file and by combining the hierarchical structure information.

For example, in the generation method provided by an embodiment of the present disclosure, the intermediate module description file includes at least one module to be added and a sub-layer level of each module to be added; according to the intermediate module description file, combining with the hierarchical structure information, acquiring at least one intermediate module passed by each object path, including: and extracting sub-modules positioned in the sub-hierarchy in each module to be added from the hierarchical structure information according to the sub-hierarchy of each module to be added, wherein at least one middle module passed by each object path comprises the module to be added and the sub-modules.

For example, in a generation method provided by an embodiment of the present disclosure, determining a source module and a destination module of each object path includes: acquiring a path information file of an integrated circuit design; and extracting the source module and the destination module of the object path from the path information file.

For example, in a generating method provided in an embodiment of the present disclosure, acquiring hierarchy structure information of an integrated circuit design includes: acquiring a chip logic design file of an integrated circuit design; and obtaining hierarchical structure information of the integrated circuit design based on the chip logic design file.

At least one embodiment of the present disclosure provides a verification method for verifying an object path in an integrated circuit design, including: acquiring a black box file according to a generation method provided by any embodiment of the disclosure; acquiring a path information file of an object path; and verifying the object path based on the path information file and the black box file to generate a verification result.

At least one embodiment of the present disclosure provides a generating apparatus of a black box file, where the black box file is used to verify an object path in an integrated circuit design, and the generating apparatus includes: a structure information acquisition unit configured to acquire hierarchical structure information of the integrated circuit design, the hierarchical structure information including structure information of the integrated circuit design and module information; a circuit module determination unit configured to determine a plurality of first circuit modules in the integrated circuit design that are associated with the object path using the hierarchical structure information; and a black box generating unit configured to generate a black box file according to module information of a second circuit module other than the plurality of first circuit modules among the plurality of circuit modules of the integrated circuit design.

For example, in a generating apparatus provided in an embodiment of the present disclosure, the number of object paths is equal to or greater than 2, and the circuit module determining unit includes: a module determination subunit configured to determine a source module and a destination module of each object path; a module acquisition subunit configured to acquire, using the hierarchical structure information, at least one intermediate module through which each object path passes; and the calculation subunit is configured to calculate a union set of the source modules, the destination modules and the at least one intermediate module of all the object paths to obtain a plurality of first circuit modules.

For example, in the generating apparatus provided in an embodiment of the present disclosure, the module acquiring subunit includes: a description file obtaining subunit configured to obtain an intermediate module description file of the integrated circuit design; and the intermediate module acquisition subunit is configured to acquire at least one intermediate module passed by each object path according to the intermediate module description file and by combining the hierarchical structure information.

For example, in the generating apparatus provided in an embodiment of the present disclosure, the intermediate module description file includes at least one module to be added and a sub-hierarchy of each module to be added; the intermediate module acquisition subunit includes: and the extraction subunit is configured to extract sub-modules positioned in the sub-hierarchy in each module to be added from the hierarchical structure information according to the sub-hierarchy of each module to be added, and at least one intermediate module through which each object path passes comprises the module to be added and the sub-modules.

For example, in the generating apparatus provided in an embodiment of the present disclosure, the module determining subunit includes: a path information file obtaining subunit configured to obtain a path information file of the integrated circuit design; and a path module determination subunit configured to extract the source module and the destination module of the object path from the path information file.

For example, in a generating apparatus provided in an embodiment of the present disclosure, a structure information acquiring unit includes: a design file acquisition subunit configured to acquire a chip logic design file of an integrated circuit design; and a hierarchical structure information acquisition subunit configured to acquire hierarchical structure information of the integrated circuit design based on the chip logic design file.

At least one embodiment of the present disclosure provides a verification apparatus for verifying an object path in an integrated circuit design, including: the black box acquisition unit is configured to acquire a black box file according to the generation method provided by any embodiment of the disclosure; a path information acquisition unit configured to acquire a path information file of the object path; and a verification unit configured to verify the object path based on the path information file and the black box file to generate a verification result.

At least one embodiment of the present disclosure provides an electronic device comprising a processor; a memory including one or more computer program instructions; one or more computer program instructions are stored in the memory and when executed by the processor implement the generation method or the verification method provided by any embodiment of the present disclosure.

At least one embodiment of the present disclosure provides a computer-readable storage medium, which stores non-transitory computer-readable instructions, and when the computer-readable instructions are executed by a processor, the generating method or the verifying method provided by any embodiment of the present disclosure is implemented.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1A illustrates a flowchart of a method for generating a black box file according to at least one embodiment of the present disclosure;

FIG. 1B is a diagram illustrating a file format of a hierarchy file provided by at least one embodiment of the present disclosure;

FIG. 1C is a schematic diagram illustrating an object path provided by at least one embodiment of the present disclosure;

fig. 2A illustrates a flowchart of a method of step S20 in fig. 1 according to at least one embodiment of the present disclosure;

fig. 2B is a schematic diagram illustrating a file format of a path information file according to at least one embodiment of the disclosure;

fig. 2C is a schematic diagram illustrating a file format of an intermediate module description file according to at least one embodiment of the present disclosure;

fig. 3 is a flowchart illustrating another black box file generation method according to at least one embodiment of the present disclosure;

FIG. 4 illustrates a flow chart of a verification method for verifying object paths in an integrated circuit design according to at least one embodiment of the present disclosure;

FIG. 5 illustrates a flow diagram of another verification method for verifying object paths in an integrated circuit design in accordance with at least one embodiment of the present disclosure;

fig. 6 is a schematic block diagram illustrating a device for generating a black box file according to at least one embodiment of the present disclosure;

FIG. 7 is a schematic block diagram illustrating an apparatus for verifying object paths in an integrated circuit design according to at least one embodiment of the present disclosure;

fig. 8 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

fig. 9 illustrates a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

fig. 10 illustrates a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In System-on-a-Chip (SoC) design verification, the verification concern may include whether data interaction between the top layer of the SoC design and each module is correct, and whether connection of each module is correct. The traditional verification scheme usually uses a written verification case to verify the SOC, but for large-scale SoC design, the number of interconnection signals is huge, and a great number of verification cases need to be constructed to cover each signal path, so that huge challenges are brought to verification work. The verification of the SoC design can be simplified by utilizing the verification tool, so that the verification of the SoC design is simpler. For example, by writing both ends of the interconnect signal in a table or a script as a check basis, the SoC design can be checked using a verification tool. In the application of large-scale SoC design verification, the verification tool has its limitation, and because the SoC design is increasingly large in scale, the process of loading the SoC design and analyzing the path by the verification tool is time-consuming, and occupies a large amount of memory, even the analysis fails due to insufficient memory. Therefore, when designing an SoC design using a verification tool, circuit modules that do not affect the analysis of paths in the SoC design can be output into one file, which is referred to as a black box file. When the verification tool analyzes the path, the circuit module in the black box file can not be considered, so that the analysis burden of the verification tool can be reduced, and the running time and the occupied memory can be saved.

In general, when the black box file is used for verification, the black box file is effective on the premise that a verification tool must load the black box file before reading the design, so the black box file is currently used as an optimization means for subsequent inspection, and once the design is changed or the path to be detected is changed, the black box file may need to be regenerated. If the black box file is obtained by analyzing the SoC design by using the verification tool, the verification tool often fails due to insufficient memory when the black box is analyzed because the SoC design is huge and the path is complex. If the black box file is written manually, if some modules affecting the path are set as the black box by mistake due to the lack of understanding of the SoC design by the user, the final inspection result will be affected, and since the number of circuit modules of the SoC design is very large, writing the black box file manually is a very tedious matter.

In the current super-large-scale SoC, the physical realization of the layout needs to be divided into a plurality of circuit modules to be respectively carried out, and then the physical design of the whole SoC is completed through the top-level design. As the chip scale continues to increase, the area increases, the wiring between circuit blocks correspondingly increases, and the line delay inevitably causes timing problems. To solve this problem, a buffer (e.g., a flip flop) is inserted on a wiring between two circuit blocks to converge timing.

At least one embodiment of the disclosure provides a black box file generation method and device, a black box file verification method and device, electronic equipment and a computer-readable storage medium. The black box file is used for verifying an object path in the integrated circuit design, and the generation method of the black box file comprises the following steps: acquiring hierarchical structure information of an integrated circuit design, wherein the hierarchical structure information comprises structural information and module information of the integrated circuit design; determining a plurality of first circuit modules in the integrated circuit design that are associated with the object path using the hierarchical structure information; and generating a black box file according to module information of a second circuit module in the integrated circuit design, wherein the second circuit module is a module except the plurality of first circuit modules in the integrated circuit design. The method for generating the black box file can simplify the complicated steps of generating the black box file, improve the efficiency of generating the black box file, relieve the problem of memory overflow and improve the efficiency of design verification of an integrated circuit.

Fig. 1A illustrates a flowchart of a method for generating a black box file according to at least one embodiment of the present disclosure.

As shown in fig. 1A, the generation method may include steps S10 to S30.

Step S10: and acquiring the hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information comprises the structure information and the module information of the integrated circuit design.

Step S20: a plurality of first circuit blocks in the integrated circuit design associated with the object path is determined using the hierarchy information.

Step S30: and generating a black box file according to the module information of the second circuit module in the integrated circuit design. Here, the second circuit module is a module other than the plurality of first circuit modules in the integrated circuit design, for example, at least a part of or all of the modules other than the plurality of first circuit modules, and the like.

The resulting black box file in embodiments of the present disclosure is used to verify object paths in an integrated circuit design.

With respect to step S10, for example, the structure information of the integrated circuit design may include a hierarchical structure of the integrated circuit design, a circuit module included in each hierarchy, and the like.

For example, the hierarchy structure information of the integrated circuit may include module information, such as a name of each circuit module, an instance name of each hierarchy, and the like, in addition to the structure information of the integrated circuit.

For example, step S10 may include: the method comprises the steps of obtaining a chip logic design file of the integrated circuit design, and obtaining hierarchical structure information of the integrated circuit design according to the chip logic design file.

The chip logic design file may be, for example, a Register Transfer Level (RTL) file. For example, analysis of the RTL file with a verification tool that includes a connection check tool for connection checking paths yields hierarchy information for the integrated circuit design.

For example, the connection check tool reads the RTL file, and after the check tool finishes reading the RTL file, executes a command (e.g., start _ gui command) for starting the gui that the connection check tool can recognize, and enters the gui of the connection check tool, where the gui displays the hierarchical structure information of the ic design.

In some embodiments of the present disclosure, the connection check tool outputs hierarchy information for the entire integrated circuit design into one hierarchy file in response to an interaction, for example, in a graphical interaction interface. For example, the hierarchy file is named hierarchy.

The embodiment can automatically generate the hierarchical structure file according to the operation of the user, is simple to operate and easy to realize, and saves the time for generating the black box file.

Fig. 1B illustrates a schematic diagram of a file format of a hierarchy file provided in at least one embodiment of the present disclosure.

As shown in fig. 1B, the hierarchy file indicates, for example, for a hierarchy log file, that the top-level module CHIP is instantiated into module a (i.e., module a), module B (i.e., module B), and module C (i.e., module C); the module A comprises a sub-level, and the sub-level comprises two sub-modules, namely a module _ A1 and a module _ A2; the module B comprises a first sub-hierarchy comprising sub-module _ B1 and sub-module _ B2, the sub-module _ B1 of the first sub-hierarchy further comprising a second sub-hierarchy comprising sub-modules module _ B11 and module _ B12; the sub-module _ B2 of the first sub-hierarchy still further comprises a second sub-hierarchy comprising sub-module _ B21.

For step S20, the plurality of first circuit modules include a source module, a destination module and at least one intermediate module, where the source module is a circuit module where a start point of the object path is located, the destination module is a circuit module where an end point of the object path is located, and the intermediate module is a module where the object path passes between the start point and the end point.

Fig. 1C is a schematic diagram illustrating an object path according to at least one embodiment of the present disclosure.

As shown in fig. 1C, the start point of the object path is port a, and the end point is port b. The port a belongs to the circuit module a and the port B belongs to the circuit module B, so that the source module of the object path is the circuit module a and the destination module is the circuit module B.

As shown in fig. 1C, the object path passes through the module C, the sub-module D in the module C, and the sub-module E from the starting point a to reach the ending point b, and therefore, the module C, the sub-module D, and the sub-module E are a plurality of intermediate modules through which the object path passes.

The object path does not pass through sub-module F in module C, and therefore, at least one intermediate module that the object path passes through does not include sub-module F.

In some embodiments of the present disclosure, for step S20, a plurality of first circuit modules in the integrated circuit design that are related to the object path are determined, for example, from a hierarchy.

In some embodiments of the present disclosure, the object path may be one or more. In the case where the object path is plural, that is, the number of object paths is 2 or more, step S20 may include the steps described below with reference to fig. 2A.

Fig. 2A illustrates an exemplary method flowchart of step S20 in fig. 1 provided by at least one embodiment of the present disclosure.

As shown in fig. 2A, in at least one example, the step S20 may include steps S21 to S23.

Step S21: a source module and a destination module for each object path are determined.

Step S22: and acquiring at least one intermediate module passed by each object path by using the hierarchical structure information.

Step S23: a union set of a source module, a destination module and at least one intermediate module including an object path is obtained to obtain a plurality of first circuit modules.

The method can obtain a plurality of first circuit modules related to all object paths, so that the second circuit modules unrelated to all object paths generate the black box file, all object paths can be verified, and the verification efficiency is improved.

For step S21, for example, a path information file of the integrated circuit design is acquired, and a source module and a destination module of the object path are extracted from the path information file.

For example, the path information file is an add.tcl file, and the script file describes some basic information of the object path, which may include, for example, a start point, an end point, a source module, a destination module, gating information, clock information, path delay information, and the like of the object path.

In some embodiments of the present disclosure, the path information file may have a fixed format, and the user may fill the script file with the path information manually or through a tool (e.g., a program) according to the fixed format.

In other embodiments of the present disclosure, the path information file may be automatically generated. For example, the object path includes at least one buffer, the buffer information of the at least one buffer in the object path is extracted from a buffer description file for the integrated circuit design, and the path description information of the object path is extracted from a chip logic design file of the integrated circuit design according to the buffer information; and generating a path information file of the object path according to the path description information. The automatic generation of the path information file further improves the generation efficiency of the black box file, the path information file does not need to be written manually, and the time for developing the path information file is greatly saved.

For example, the buffer description file may include, for example, the number of stages of buffers to be inserted on a signal connection between two circuit modules, signal information at both ends of the connection, clock information used for the buffers, and the like. The path description information of the object path may include, for example, a start point and an end point of the object path, a circuit module in which the start point is located, a circuit module in which the end point is located, and the like.

Fig. 2B is a schematic diagram illustrating a file format of a path information file according to at least one embodiment of the present disclosure.

As shown in fig. 2B, for example, the name of a path information file may be add.tcl, in which an object path from a start point a to an end point B (hereinafter, referred to as "a-B path"), an object path from a start point c to an end point d (hereinafter, referred to as "c-d path"), and an object path from a start point e to an end point f (hereinafter, referred to as "e-f path") are included.

As shown in fig. 2B, the source modules of the a-B path and the c-d path are circuit modules a, and the destination modules are circuit modules B; the source module of the e-F path is circuit module D and the destination module is circuit module F.

As shown in fig. 2B, path delay information of the object path may also be included in the path information file. For example, path _ delay represents path delay information of the object path. For example, the a-b path and the c-d path are delayed by 1 clock cycle.

For step S21, the source module and the destination module of each object path may be determined in other manners. Such as a source module and a destination module that receive user input.

For step S22, for example, an intermediate module description file of the integrated circuit design may be obtained; and acquiring at least one intermediate module passed by each object path according to the intermediate module description file and by combining the hierarchical structure information.

In some embodiments of the present disclosure, the intermediate module description file includes at least one module to be added and a sub-level for each module to be added.

Fig. 2C is a schematic diagram illustrating a file format of an intermediate module description file according to at least one embodiment of the present disclosure.

As shown in fig. 2C, for example, the middle module description file is add. The middle module description file may include two columns. The first column, hierarchy, represents the Hierarchy of modules to be added. The second column is "Level", which represents the sub-Level of the module to be added through which the object path passes.

For example, the element located at the "Hierarchy" column and at the first row is chip.m, which indicates that the module to be added includes a circuit module CHIP and a circuit module M. The circuit module CHIP may be, for example, a top module, and the circuit module M is a sub-module of the top module. The value of "Level" corresponding to chip.m is 1, and indicates that the object path passes through sub-modules of the first sub-hierarchy of the circuit module M, for example, the sub-modules of the first sub-hierarchy include a sub-module M1 and a sub-module M2.

Similarly, the element in the second row in the "Hierarchy" column is chip.n, which means that the modules to be added include circuit module CHIP and circuit module N. The value of "Level" corresponding to chip.n is 2, and indicates that the object path passes through sub-modules at a sub-Level of the first layer and sub-modules at a sub-Level of the second layer in the circuit block N. For example, the object path passes through sub-module N1 and sub-module N2 included in the first sub-level of circuit module N, module N11 in the second sub-level included in sub-module N1, and the like.

Also for example, the element located in the "Hierarchy" column and located in the third row is chip.l, which means that the module to be added includes a circuit module CHIP and a circuit module L. The value of "Level" corresponding to chip.n is all, indicating that the object path passes through all sub-Level sub-modules included in the circuit block L.

In some embodiments of the present disclosure, an intermediate module description file add, csv, such as that shown in fig. 2C, may be user-written.

In some embodiments of the present disclosure, a "Hierarchy" column in the middle module description file add.csv, such as shown in fig. 2C, may be automatically generated by a verification tool or other tool, and a "Level" column may be filled in by a user.

For example, in the object path shown in fig. 1C, the object path passes through not only the circuit module C but also the sub-module D instantiated by the circuit module C and the sub-module E instantiated by D. If sub-modules D and E are manually added to a file (e.g., a table) for recording information of an intermediate module, it is very cumbersome to add sub-modules D and E, so a Level information "Level" is set, and it is only necessary to fill the hierarchical structure of circuit module C into the "Hierarchy" column and fill 2 into the "Level" column, which is equivalent to including circuit module C and modules D, E, and F including the two levels below circuit module C in an intermediate module through which an object path passes, thereby reducing the cumbersome degree of obtaining the intermediate module. If only the circuit module C is needed to be added, and the sub-module is obtained without adding the circuit module C for instantiation, 0 is filled in the 'Level' column. If the design of the circuit block C is not clear, it is only known that the object path will pass through the circuit block C and some sub-blocks below the circuit block C, and a "Level" column may be filled with all, which is equivalent to including all the hierarchical blocks below C in the intermediate block through which the object path passes.

For step S22, for example, according to the hierarchy of each module to be added, a sub-module located in the hierarchy in each module to be added is extracted from the hierarchical structure information, and at least one intermediate module through which each object path passes includes the module to be added and the sub-module.

For example, the middle module description file is an add.csv file in fig. 2C, the module to be added including chip.m, chip.n, and chip.l is obtained by reading the add.csv file, and a sub-module of a sub-level where an object path passes through a first layer in the circuit module M can also be obtained by reading the add.csv file; the object path passes through sub-modules positioned at a sub-level of a first layer and sub-modules positioned at a sub-level of a second layer in the circuit module N; the object path passes through all sub-level sub-modules comprised by the circuit module L. According to the information obtained by reading the add.csv file, for example, the sub-module of the sub-level of the first layer in the circuit module M is extracted from the hierarchy.log file described above as M1, the first sub-level of the circuit module N includes a sub-module N1 and a sub-module N2, and the sub-module N1 includes a sub-module N11 in the second sub-level, and the like. Thus, the at least one intermediate module traversed by the object path may comprise: the circuit module M and the sub-module M are M1, the circuit module N, a sub-module N1, a sub-module N2, a sub-module N11 and the like.

For step S23, a union refers to a set composed by merging elements in multiple sets together. For example, the elements in the set obtained by combining the source module, the destination module and the at least one intermediate module in the plurality of object paths are a plurality of first circuit modules. There are no duplicate circuit blocks in the combined set. For example, only one of the repeated circuit modules in the source module, the destination module and the at least one intermediate module in the plurality of object paths is reserved, so that a union including the source module, the destination module and the at least one intermediate module of all object paths is obtained.

For example, the plurality of object paths include a first object path and a second object path, the plurality of first circuit modules of the first object path may include, for example, a circuit module P1, a circuit module P2, and a circuit module P3, and the plurality of first circuit modules of the second object path may also include a circuit module Q1, a circuit module P2, and a circuit module Q2, where the circuit module P2 is a circuit module that is duplicated with respect to the first object path and the second object path, and thus only one circuit module P2 is reserved, and thus the plurality of first circuit modules obtained after the union processing includes the circuit module P1, the circuit module P2, and the circuit module P3, the circuit module Q1, and the circuit module Q2.

For step S30, for example, a required second circuit module is obtained by using a command (e.g., -set _ black-out { }) of the black box setting manner provided by the verification tool, so that a black box file is generated according to the module information of the second circuit module. The effect of the command-set _ blackbox-exception { } is to generate as a black box file from circuit blocks in the integrated circuit design except in curly brackets behind-exception. For example, a user may enter a number of first circuit modules into curly brackets behind an-exception, thereby automatically generating a black box file by the verification tool.

For example, -set _ blackbex-exception { CHIP, A1, A2, B1, B2, B11 \8230 }, the verification tool sets other circuit modules in the integrated circuit design except for { CHIP, A1, A2, B1, B2, B11 \8230 }, as black box files.

Fig. 3 illustrates a flowchart of another method for generating a black box file according to at least one embodiment of the present disclosure.

As shown in fig. 3, the generation method includes steps S301 to S309.

Step S301: a chip logic design file, such as an RTL file, of the integrated circuit is read.

Step S302: and starting a connection checking tool interactive interface. For example, a start _ gui command, which the connection check tool can recognize, is executed to enter the graphical interactive interface of the connection check tool.

Step S303: for example, the hierarchical structure of the integrated circuit design is displayed in the graphical interactive interface, a right-click of a mouse is performed on, for example, a "Hierarchy" window in the graphical interactive interface, and the entire hierarchical structure of the integrated circuit is output to a hierarchical structure file through an option of an "output hierarchical structure" in a pop-up dialog box. This file is saved as hierarchy.

Step S304: a path information file is obtained, for example, the add.tcl file described above.

Step S305: an intermediate module description file, such as the add.

Step S306: for example, the name of the source module and the name of the destination module in the path information file (e.g., saved as add.tcl file) are extracted, and the corresponding circuit module is looked up in the hierarchy file (hierarchy.log).

Step S307: extracting module information (e.g. information of "Hierarchy" column in fig. 2C) and corresponding sub-Level information ("Level" column) in an intermediate module description file (e.g. add.csv file), and searching for an intermediate module meeting requirements in a hierarchical structure file (hierarchy.log).

Step S308: and removing repeated circuit modules to obtain a union set of a source module, a destination module and at least one intermediate module which comprise the object path to obtain a plurality of first circuit modules. For example, step S23 described above with respect to fig. 2A is performed.

Step S309: for example, a black box file is generated using-set _ blackbox-instance { } provided by the validation tool.

At least one embodiment of the present disclosure also provides a verification method for verifying an object path in an integrated circuit design. The verification method may include acquiring a black box file according to the generation method of any of the above embodiments; acquiring a path information file of an object path; and verifying the object path based on the path information file and the black box file to generate a verification result. The verification method can simplify the complicated steps of the black box file, relieve the problem that the verification tool fails to automatically generate the black box file, greatly reduce the time required by verification and improve the verification efficiency.

Fig. 4 illustrates a flow chart of a verification method for verifying an object path in an integrated circuit design according to at least one embodiment of the disclosure.

As shown in fig. 4, the authentication method may include steps S401 to S403.

Step S401: and acquiring the black box file according to the generation method of the black box file.

Step S402: and acquiring a path information file of the object path.

Step S403: and verifying the object path based on the path information file and the black box file to generate a verification result.

In the above-described authentication method, for step S401, for example, a black box file may be generated according to the generation method of any of the above-described embodiments.

In the above-described authentication method, for step S402, the path information file is, for example, the add.tcl file described above. The path information file may be written by the user himself. For example, the path information file is read according to an access path input by a user.

In other embodiments of the present disclosure, for example, the path information file may be automatically generated. For example, the object path includes at least one buffer, and buffer information of the at least one buffer in the object path is extracted from a buffer description file for the integrated circuit design; extracting path description information of the object path from a chip logic design file (e.g., an RTL file) of the integrated circuit design according to the buffer information; and generating a path information file including path information of the object path according to the path description information.

With respect to step S403, the path information file and the black box file are read, for example, by a verification tool, and the object path is verified according to the path information file and the black box file to generate a verification result.

Fig. 5 is a flowchart illustrating another verification method for verifying an object path in an integrated circuit design according to at least one embodiment of the present disclosure.

As shown in fig. 5, the authentication method may include steps S501 to S507.

Step S501: a chip logic design file (e.g., RTL file) of an integrated circuit design is obtained.

Step S502: a path information file, such as the add.tcl file described above, is obtained.

Step S503: the black box file is obtained according to the method for generating the black box file provided by any embodiment of the disclosure. The analysis efficiency of the verification tool can be improved by setting the module irrelevant to the path to be detected in the integrated circuit design as a black box.

Step S504: get the verification script (e.g., run. Tcl file) that the verification tool runs. For example, the verification tool may be a connection check tool, for example, a run.tcl file containing therein a basic setting command of the connection check tool, a command to read a black box file, a command to read a design file, a command to read a description path file, and a command to start a path check.

Step S505: run run.tcl file.

Step S506: a verification result is generated, which may be, for example, a result file vcf.

Step S507: and debugging the path with failed verification through a debugging command or an interactive interface. For example, the reason for the failure of verification is analyzed, the integrated circuit design is modified or the path information file add.tcl is modified.

Fig. 6 illustrates a schematic block diagram of a generation apparatus 600 for a black box file according to at least one embodiment of the present disclosure.

For example, as shown in fig. 6, the black box file generating apparatus 600 includes a configuration information acquiring unit 610, a circuit module determining unit 620, and a black box generating unit 630. The black box file is used to verify object paths in the integrated circuit design.

The structure information obtaining unit 610 is configured to obtain hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information includes structure information and module information of the integrated circuit design. The hierarchy structure information may also include an instance name for each hierarchy.

The configuration information acquisition unit 610 may perform step S10 described in fig. 1A, for example.

The circuit module determining unit 620 is configured to determine a plurality of first circuit modules of the integrated circuit design that are associated with the object path using the hierarchical structure information.

The circuit module determination unit 620 may perform, for example, step S20 described in fig. 1A.

The black box generating unit 630 is configured to generate the black box file according to module information of a second circuit module other than the plurality of first circuit modules among the plurality of circuit modules of the integrated circuit design.

The black box generating unit 630 may perform, for example, step S30 described in fig. 1A.

For example, in a generating apparatus provided in an embodiment of the present disclosure, a module acquiring subunit includes: a description file acquiring subunit configured to acquire an intermediate module description file of the integrated circuit design; and the intermediate module acquisition subunit is configured to acquire at least one intermediate module passed by each object path according to the intermediate module description file and by combining the hierarchical structure information.

For example, in the generating apparatus provided in an embodiment of the present disclosure, the intermediate module description file includes at least one module to be added and a sub-hierarchy of each module to be added; the intermediate module acquisition subunit includes: and the extracting subunit is configured to extract the sub-modules positioned in the sub-hierarchy in each module to be added from the hierarchical structure information according to the sub-hierarchy of each module to be added, and at least one intermediate module through which each object path passes comprises the module to be added and the sub-modules.

For example, in a generating apparatus provided in an embodiment of the present disclosure, the module determining subunit includes: a path information file obtaining subunit configured to obtain a path information file of the integrated circuit design; and a path module determination subunit configured to extract a source module and a destination module of the object path from the path information file.

For example, in a generating apparatus provided in an embodiment of the present disclosure, the configuration information acquiring unit includes: a design file acquisition subunit configured to acquire a chip logic design file of an integrated circuit design; and a hierarchical structure information acquisition subunit configured to acquire hierarchical structure information of the integrated circuit design based on the chip logic design file.

For example, the configuration information acquisition unit 610, the circuit module determination unit 620, and the black box generation unit 630 may be hardware, software, firmware, and any feasible combination thereof. For example, the configuration information acquiring unit 610, the circuit module determining unit 620, and the black box generating unit 630 may be dedicated or general circuits, chips, devices, or the like, or may be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the generating apparatus 600 corresponds to each step of the foregoing verification method, and for a specific function of the generating apparatus 600, reference may be made to the related description about the generating method, which is not described herein again. The components and structure of the generating apparatus 600 shown in fig. 6 are merely exemplary and not limiting, and the generating apparatus 600 may further include other components and structures as needed.

Fig. 7 illustrates a schematic block diagram of a verification apparatus 700 for verifying an object path in an integrated circuit design according to at least one embodiment of the present disclosure.

For example, as shown in fig. 7, the authentication apparatus 700 may include a black box acquisition unit 710, a path information acquisition unit 720, and an authentication unit 730.

The black box acquiring unit 710 is configured to acquire a black box file according to a generating method provided by any embodiment of the present disclosure.

The black box acquiring unit 710 may perform step S401 described in fig. 4, for example.

The path information obtaining unit 720 is configured to obtain a path information file of the object path.

The path information acquisition unit 720 may perform step S402 described in fig. 4, for example.

The verification unit 730 is configured to verify the object path based on the path information file and the black box file to generate a verification result.

The verification unit 730 may, for example, perform step S403 described in fig. 4.

For example, the black box acquiring unit 710, the path information acquiring unit 720, and the verifying unit 730 may be hardware, software, firmware, and any feasible combination thereof. For example, the black box acquiring unit 710, the path information acquiring unit 720 and the verifying unit 730 may be a dedicated or general circuit, a chip or a device, or a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in at least one embodiment of the present disclosure, each unit of the verification apparatus 700 corresponds to each step of the aforementioned verification method, and for specific functions of the verification apparatus 700, reference may be made to relevant descriptions about the verification method, which are not described herein again. The components and configuration of the authentication device 700 shown in fig. 7 are exemplary only, and not limiting, and the authentication device 700 may include other components and configurations as desired.

At least one embodiment of the present disclosure also provides an electronic device comprising a processor and a memory, the memory including one or more computer program instructions. One or more computer program instructions are stored in the memory and executed by the processor to implement the black box file generation method or the verification method described above. The electronic equipment can improve the complicated steps of simplifying the generation of the black box file, improve the generation efficiency of the black box file and improve the verification efficiency.

Fig. 8 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 8, the electronic device 800 includes a processor 810 and a memory 820. The memory 820 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules). The processor 810 is configured to execute non-transitory computer readable instructions, which when executed by the processor 810 may perform one or more steps of the bus device design method described above. The memory 820 and the processor 810 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, processor 810 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 810 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 800 to perform desired functions.

For example, memory 820 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, erasable Programmable Read Only Memory (EPROM), portable compact disk read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 810 to implement various functions of electronic device 800. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the design method of the bus device for specific functions and technical effects of the electronic device 800, and details are not described here.

Fig. 9 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic apparatus 900 is, for example, suitable for implementing a method for designing a bus device according to an embodiment of the present disclosure. The electronic device 900 may be a terminal device or the like. It should be noted that the electronic device 900 shown in fig. 9 is only one example and does not bring any limitations to the function and the scope of the use of the embodiments of the present disclosure.

As shown in fig. 9, electronic device 900 may include a processing means (e.g., central processing unit, graphics processor, etc.) 910 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM) 920 or a program loaded from storage 980 into a Random Access Memory (RAM) 930. In the RAM930, various programs and data necessary for the operation of the electronic apparatus 900 are also stored. The processing device 910, the ROM 920, and the RAM930 are connected to each other through a bus 940. An input/output (I/O) interface 950 is also connected to bus 940.

Generally, the following devices may be connected to the I/O interface 950: input devices 960 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 970 including, for example, a Liquid Crystal Display (LCD), speaker, vibrator, or the like; storage 980 including, for example, magnetic tape, hard disk, etc.; and a communication device 990. The communication means 990 may allow the electronic device 900 to communicate with other electronic devices wirelessly or by wire to exchange data. While fig. 9 illustrates an electronic device 900 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 900 may alternatively be implemented or provided with more or less means.

For example, according to an embodiment of the present disclosure, the generation method and the verification method of the black box file described above may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the above-described bus apparatus design method. In such embodiments, the computer program may be downloaded and installed from a network through the communication device 990, or installed from the storage device 980, or installed from the ROM 920. When the computer program is executed by the processing device 910, the functions defined in the generation method and the verification method of the black box file provided by the embodiment of the present disclosure can be implemented.

At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, may implement the black box file generation method and the verification method described above. The computer readable storage medium can improve the complicated steps of simplifying the generation of the black box file, improve the generation efficiency of the black box file and improve the verification efficiency.

Fig. 10 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 10, the storage medium 1000 is used to store non-transitory computer readable instructions 1010. For example, the non-transitory computer readable instructions 1010, when executed by a computer, may perform one or more steps of the black box file generation method and the authentication method described above.

For example, the storage medium 1000 may be applied to the electronic device 800 described above. For example, the storage medium 1000 may be the memory 820 in the electronic device 800 shown in fig. 8. For example, the related description about the storage medium 1000 may refer to the corresponding description of the memory 820 in the electronic device 800 shown in fig. 8, and is not repeated here.

The following points need to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A generation method of a black box file, wherein the black box file is used for verifying an object path in an integrated circuit design, the generation method comprising:

acquiring hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information comprises structure information and module information of the integrated circuit design;

determining a plurality of first circuit modules in the integrated circuit design that are associated with the object path using the hierarchy information; and

and generating the black box file according to module information of a second circuit module in the integrated circuit design, wherein the second circuit module is a module in the integrated circuit design except the plurality of first circuit modules.

2. The generation method of claim 1, wherein the plurality of first circuit modules includes a source module, a destination module of the object path, and at least one intermediate module through which the object path passes,

the source module is a circuit module where a starting point of the object path is located, and the destination module is a circuit module where an end point of the object path is located.

3. The generation method according to claim 2, wherein the number of object paths is 2 or more,

using the hierarchy information, determining the plurality of first circuit modules in the integrated circuit design that are associated with the object path, comprising:

determining a source module and a destination module of each object path;

using the hierarchical structure information to obtain at least one intermediate module passed by each object path; and

and acquiring a union set of a source module, a destination module and at least one intermediate module comprising the object path to obtain the plurality of first circuit modules.

4. The generation method of claim 3, wherein using the hierarchy information to obtain the at least one intermediate module traversed by the each object path comprises:

acquiring an intermediate module description file of the integrated circuit design; and

and acquiring the at least one intermediate module passed by each object path according to the intermediate module description file and by combining the hierarchical structure information.

5. The generation method according to claim 4, wherein the intermediate module description file includes at least one module to be added and a sub-level of each module to be added;

according to the intermediate module description file, in combination with the hierarchical structure information, acquiring at least one intermediate module passed by each object path, including:

extracting sub-modules positioned in the sub-hierarchy in each module to be added from the hierarchical structure information according to the sub-hierarchy of each module to be added,

wherein the at least one intermediate module passed by each object path includes the module to be added and the sub-module.

6. The generation method of claim 3, wherein determining the source module and the destination module of the each object path comprises:

acquiring a path information file of the integrated circuit design; and

and extracting the source module and the destination module of the object path from the path information file.

7. The generation method of any of claims 1 to 6, wherein obtaining the hierarchy information of the integrated circuit design comprises:

acquiring a chip logic design file of the integrated circuit design; and

obtaining the hierarchical structure information of the integrated circuit design based on the chip logic design file.

8. A verification method for verifying object paths in an integrated circuit design, comprising:

acquiring the black box file according to the generation method of any one of claims 1 to 7;

acquiring a path information file of the object path; and

and verifying the object path based on the path information file and the black box file to generate a verification result.

9. An apparatus for generating a black box file for verifying object paths in an integrated circuit design, the apparatus comprising:

a structure information obtaining unit configured to obtain hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information includes structure information and module information of the integrated circuit design;

a circuit module determining unit configured to determine a plurality of first circuit modules in the integrated circuit design related to the object path using the hierarchical structure information; and

a black box generating unit configured to generate the black box file according to module information of a second circuit module other than the plurality of first circuit modules among a plurality of circuit modules of the integrated circuit design.

10. A verification apparatus for verifying object paths in an integrated circuit design, comprising:

a black box acquisition unit configured to acquire the black box file according to the generation method according to any one of claims 1 to 7;

a path information acquisition unit configured to acquire a path information file of the object path; and

and the verification unit is configured to verify the object path based on the path information file and the black box file to generate a verification result.

11. An electronic device, comprising:

a processor;

a memory comprising one or more computer program instructions;

wherein the one or more computer program instructions are stored in the memory and when executed by the processor implement the generation method of any one of claims 1-7 or the verification method of claim 8.

12. A computer readable storage medium storing non-transitory computer readable instructions, wherein the computer readable instructions, when executed by a processor, implement the generation method of any one of claims 1-7 or the verification method of claim 8.