CN115292949A - Method and device for evaluating whether redundant array meets replacement requirements - Google Patents
Method and device for evaluating whether redundant array meets replacement requirements Download PDFInfo
- Publication number
- CN115292949A CN115292949A CN202210980764.6A CN202210980764A CN115292949A CN 115292949 A CN115292949 A CN 115292949A CN 202210980764 A CN202210980764 A CN 202210980764A CN 115292949 A CN115292949 A CN 115292949A
- Authority
- CN
- China
- Prior art keywords
- wafer
- chip
- redundant arrays
- address information
- database
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The application discloses a method and a device for evaluating whether a redundant array meets the replacement requirement, which can be applied to the technical field of chip production design, wherein the method comprises the following steps: acquiring address information of a specific failure unit of a chip; establishing a wafer failure address database based on the address information; performing mathematical modeling by using the database to obtain the number of redundant arrays required by repairing each chip in the wafer; and obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer. According to the method and the device, based on the address information of the failure unit which actually appears in the produced chip, the redundant array is evaluated and analyzed by using mathematical modeling, and the relation between the accurate redundant array number and the wafer yield can be obtained, so that the redundant array number can be set by combining the requirement on the product yield, and the problem that how many redundant arrays are reserved to meet the requirement on replacement of the failure unit of the main array is solved.
Description
Technical Field
The present application relates to the field of chip production design technologies, and in particular, to a method and an apparatus for evaluating whether a redundant array meets a replacement requirement.
Background
The redundant array is a spare storage unit in the storage chip and is used for compensating and improving the yield by replacing the failure main array with the redundant array after the production of the wafer is finished, so that the final yield of the product under the permission of a normal process can meet the requirement of mass production; for memory chips, the number of memory cells is usually in the order of mega, and even more capacity has giga memory cells. If a single failed memory cell is generated in one giga of memory cells due to production process errors, on the basis, the whole chip is regarded as a failed chip, which is unreasonable from the cost aspect, so that adding a redundant array is an effective production cost reduction mechanism in a large-capacity memory chip.
However, the redundant array occupies a part of the chip area, too much redundant array may result in a smaller number of chip particles that can be manufactured by a wafer with the same area, and too little redundant array may result in that the redundant array cannot completely replace the failed main array, so that only the whole chip can be regarded as a failed chip. Therefore, how to evaluate how many redundant arrays need to be reserved to meet the requirement of replacing the failure unit of the main array becomes a technical problem to be solved in the field.
Disclosure of Invention
Based on the above problems, the present application provides a method and an apparatus for evaluating whether a redundant array meets a replacement requirement, so as to evaluate how many redundant arrays need to be reserved to meet the requirement of replacing a failure unit of a main array.
The embodiment of the application discloses the following technical scheme:
in a first aspect, an embodiment of the present application provides a method for evaluating whether a redundant array meets a replacement requirement, where the method includes:
acquiring address information of a specific failure unit of a chip;
establishing a wafer failure address database based on the address information;
performing mathematical modeling by using the database to obtain the number of redundant arrays required for repairing each chip in the wafer;
and obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer.
Optionally, the obtaining address information of the specific failure unit of the chip includes:
when a failed chip is screened, the address information of a specific failed unit of the chip is acquired by using a failed address memory module.
Optionally, the establishing a wafer failure address database based on the address information includes:
generating a data file based on the address information;
establishing a wafer failure address database according to the data file;
optionally, the obtaining the number of redundant arrays required for repairing each chip in the wafer by using the database to perform mathematical modeling includes:
acquiring a physical address mapping formula according to a chip design scheme and a layout arrangement rule by using the database;
and performing mathematical modeling according to the physical address mapping formula and the replacement rule aiming at the failure unit to obtain the quantity of redundant arrays required by repairing each chip in the wafer.
Optionally, obtaining a relationship between the number of redundant arrays and a wafer yield according to the number of redundant arrays required for repairing each chip in the wafer includes:
and generating a relation graph of the number of the redundant arrays and the yield of the wafer according to the number of the redundant arrays required by repairing each chip in the wafer by using a data statistical tool.
In a second aspect, an embodiment of the present application provides an apparatus for evaluating whether a redundant array meets a replacement requirement, where the apparatus includes:
the address information acquisition module is used for acquiring the address information of the specific failure unit of the chip;
the database establishing module is used for establishing a wafer failure address database based on the address information;
the modeling module is used for carrying out mathematical modeling by utilizing the database to obtain the quantity of redundant arrays required by repairing each chip in the wafer;
and the relation acquisition module is used for acquiring the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer.
Optionally, the address information obtaining module is specifically configured to obtain address information of a specific failing unit of a chip by using the failing address memory module when screening the failing chip.
Optionally, the database establishing module includes:
a data file generating unit configured to generate a data file based on the address information;
the database establishing unit is used for establishing a wafer failure address database according to the data file;
optionally, the modeling module includes:
the mapping formula obtaining unit is used for obtaining a physical address mapping formula according to a chip design scheme and a layout arrangement rule by using the database;
and the modeling unit is used for performing mathematical modeling according to the physical address mapping formula and the replacement rule aiming at the failure unit to obtain the quantity of the redundant arrays required by repairing each chip in the wafer.
Optionally, the relationship obtaining module is specifically configured to generate a relationship diagram between the number of redundant arrays and a wafer yield according to the number of redundant arrays required for repairing each chip in the wafer by using a data statistics tool.
Compared with the prior art, the method has the following beneficial effects:
the method comprises the steps of obtaining address information of a specific failure unit of a chip; establishing a wafer failure address database based on the address information; performing mathematical modeling by using the database to obtain the number of redundant arrays required for repairing each chip in the wafer; and obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer. According to the method and the device, based on the address information of the failure unit actually appearing in the produced chip, the redundant array is evaluated and analyzed by using mathematical modeling, and the relation between the number of the redundant arrays and the wafer yield can be accurately obtained, so that the number of the redundant arrays can be set by combining the requirements on the product yield, and the problem that the requirement of replacing the main array failure unit can be met by reserving more redundant arrays is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a schematic flowchart of a method for evaluating whether a redundant array meets a replacement requirement according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating a relationship between the number of redundant arrays and yield according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an apparatus for evaluating whether a redundant array meets a replacement requirement according to an embodiment of the present disclosure.
Detailed Description
As described above, too many and too few redundant arrays can increase production costs for the chip manufacturer.
The inventor researches and invents a method and a device for evaluating whether a redundant array meets the replacement requirement so as to evaluate how many redundant arrays need to be reserved to meet the requirement of replacing a failure unit of a main array.
In order to make those skilled in the art better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Method embodiment
Referring to fig. 1, a schematic flow chart of a method for evaluating whether a redundant array meets a replacement requirement according to an embodiment of the present application includes the following steps:
s101, address information of a specific failure unit of the chip is obtained.
Specifically, while the failed chips are screened in a CP (Chip-binding wafer Test) or FT (Final-Test package) manner, the Address information of the specific failed unit of the Chip is collected by using an Address failure Memory module AFM (Address Fail Memory) of an Automatic Test Equipment ATE (Automatic Test Equipment), that is, when the failed chips are screened, the Address information of the specific failed unit of the Chip is obtained by using the Address failure Memory module.
It should be noted that, in step S101, one wafer or one batch of wafers to be tested under the same process may be prepared, and since one wafer can generally manufacture a plurality of chips, in step S101, the address information of the specific fail unit of each chip included in one wafer to be tested may be obtained. Each chip is taken as an independent observation individual, so that the problem that a simulation model is easy to distort when the process defects are relatively concentrated and the same area possibly contains multiple failure types and is evaluated by other methods is effectively solved.
And S102, establishing a wafer failure address database based on the address information.
Specifically, a data file may be generated based on the address information of the specific failing unit of the chip acquired in step S101, and a wafer failing address database may be established by using the generated data file.
And S103, performing mathematical modeling by using the database to obtain the number of redundant arrays required for repairing each chip in the wafer.
Specifically, because the failure of the memory cell caused by the production process is the actual physical arrangement, and in the actual circuit design, the replacement mechanism of the redundant array is often limited to a certain extent, and any position which cannot be replaced randomly is replaced, a later modeling step is required to be added for evaluating and analyzing the coverage rate of the redundant array, so that how many redundant arrays are required to repair each chip in the wafer can be known. Therefore, in step S103, a physical address mapping formula may be obtained according to the chip design scheme and the layout arrangement rule by using the database; and performing mathematical modeling according to the physical address mapping formula and the replacement rule aiming at the failure unit to obtain the quantity of redundant arrays required by repairing each chip in the wafer.
And S104, obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer.
Specifically, a relation graph between the number of redundant arrays and the yield of the wafer may be generated by using a data statistics tool according to the number of redundant arrays required for repairing each chip in the wafer, and the generated relation graph may be as shown in fig. 2, which is a schematic diagram of the relation between the number of redundant arrays and the yield provided in the embodiment of the present application.
It should be noted that, in the embodiments provided in the present application, it is not limited to what kind of data statistics tool is specifically used, and a conventional data statistics tool may be used to generate a graph capable of representing the relationship between the number of redundant arrays and the wafer yield according to the number of redundant arrays required for repairing each chip in the wafer.
According to the method for evaluating whether the redundant array meets the replacement requirement, the address information of the specific failure unit of the chip is obtained; establishing a wafer failure address database based on the address information; performing mathematical modeling by using the database to obtain the number of redundant arrays required for repairing each chip in the wafer; and obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer. According to the method and the device, based on the address information of the failure unit which actually appears in the produced chip, the redundant array is evaluated and analyzed by using mathematical modeling, and the relation between the accurate redundant array number and the wafer yield can be obtained, so that the redundant array number can be set by combining the requirement on the product yield, and the problem that how many redundant arrays are reserved to meet the requirement on replacement of the failure unit of the main array is solved.
Device embodiment
Referring to fig. 3, the schematic view of a device for evaluating whether a redundant array meets a replacement requirement according to an embodiment of the present application includes an address information obtaining module 301, a database establishing module 302, a modeling module 303, and a relationship obtaining module 304.
The address information acquiring module 301 is configured to acquire address information of a specific failure unit of a chip;
a database establishing module 302, configured to establish a wafer failure address database based on the address information;
the modeling module 303 is configured to perform mathematical modeling by using the database to obtain the number of redundant arrays required for repairing each chip in the wafer;
the relationship obtaining module 304 is configured to obtain a relationship between the number of redundant arrays and a wafer yield according to the number of redundant arrays required for repairing each chip in the wafer.
Optionally, the address information obtaining module 301 is specifically configured to, when a failed chip is screened, obtain address information of a specific failed unit of the chip by using a failed address storage module.
Optionally, the database building module 302 includes:
a data file generating unit configured to generate a data file based on the address information;
the database establishing unit is used for establishing a wafer failure address database according to the data file;
optionally, the modeling module 303 includes:
the mapping formula obtaining unit is used for obtaining a physical address mapping formula according to a chip design scheme and a layout arrangement rule by using the database;
and the modeling unit is used for performing mathematical modeling according to the physical address mapping formula and the replacement rule aiming at the failure unit to obtain the quantity of the redundant arrays required by repairing each chip in the wafer.
Optionally, the relationship obtaining module 304 is specifically configured to generate a relationship diagram between the number of redundant arrays and the yield of the wafer according to the number of redundant arrays required for repairing each chip in the wafer by using a data statistics tool.
The device for evaluating whether the redundant array meets the replacement requirement comprehensively utilizes an address information acquisition module, a database establishment module, a modeling module and a relation acquisition module; acquiring address information of a specific failure unit of a chip; establishing a wafer failure address database based on the address information; performing mathematical modeling by using the database to obtain the number of redundant arrays required by repairing each chip in the wafer; and obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer. According to the method and the device, based on the address information of the failure unit which actually appears in the produced chip, the redundant array is evaluated and analyzed by using mathematical modeling, and the relation between the accurate redundant array number and the wafer yield can be obtained, so that the redundant array number can be set by combining the requirement on the product yield, and the problem that how many redundant arrays are reserved to meet the requirement on replacement of the failure unit of the main array is solved.
It should be noted that, in this specification, each embodiment is described in a progressive manner, and the same and similar parts between the embodiments are referred to each other, and each embodiment focuses on differences from other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts suggested as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only one specific embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of evaluating whether a redundant array satisfies a replacement requirement, the method comprising:
acquiring address information of a specific failure unit of a chip;
establishing a wafer failure address database based on the address information;
performing mathematical modeling by using the database to obtain the number of redundant arrays required for repairing each chip in the wafer;
and obtaining the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer.
2. The method according to claim 1, wherein the obtaining address information of the specific failed unit of the chip comprises:
when a failed chip is screened, the address information of a specific failed unit of the chip is acquired by using a failed address memory module.
3. The method of claim 1, wherein building a wafer failed address database based on the address information comprises:
generating a data file based on the address information;
and establishing a wafer failure address database according to the data file.
4. The method of claim 1, wherein the performing mathematical modeling using the database to obtain the number of redundant arrays needed to repair each die in the wafer comprises:
acquiring a physical address mapping formula according to a chip design scheme and a layout arrangement rule by using the database;
and performing mathematical modeling according to the physical address mapping formula and the replacement rule aiming at the failure unit to obtain the quantity of redundant arrays required by repairing each chip in the wafer.
5. The method of claim 1, wherein obtaining the relationship between the number of redundant arrays and the wafer yield according to the number of redundant arrays required for repairing each chip in the wafer comprises:
and generating a relation graph of the number of the redundant arrays and the yield of the wafer according to the number of the redundant arrays required by repairing each chip in the wafer by using a data statistical tool.
6. An apparatus for evaluating whether a redundant array satisfies a replacement requirement, the apparatus comprising:
the address information acquisition module is used for acquiring the address information of the specific failure unit of the chip;
the database establishing module is used for establishing a wafer failure address database based on the address information;
the modeling module is used for carrying out mathematical modeling by utilizing the database to obtain the quantity of redundant arrays required by repairing each chip in the wafer;
and the relation acquisition module is used for acquiring the relation between the number of the redundant arrays and the wafer yield according to the number of the redundant arrays required by repairing each chip in the wafer.
7. The apparatus of claim 6, wherein the address information obtaining module is specifically configured to obtain address information of a specific failing unit of a chip by using the failing address memory module when a failing chip is screened.
8. The apparatus of claim 6, wherein the database building module comprises:
a data file generating unit configured to generate a data file based on the address information;
and the database establishing unit is used for establishing a wafer failure address database according to the data file.
9. The apparatus of claim 6, wherein the modeling module comprises:
the mapping formula obtaining unit is used for obtaining a physical address mapping formula according to a chip design scheme and a layout arrangement rule by using the database;
and the modeling unit is used for performing mathematical modeling according to the physical address mapping formula and the replacement rule aiming at the failure unit to obtain the quantity of the redundant arrays required by repairing each chip in the wafer.
10. The apparatus of claim 6, wherein the relationship obtaining module is specifically configured to generate a relationship graph of the number of redundant arrays and a wafer yield according to the number of redundant arrays required for repairing each chip in the wafer by using a data statistics tool.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210980764.6A CN115292949A (en) | 2022-08-16 | 2022-08-16 | Method and device for evaluating whether redundant array meets replacement requirements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210980764.6A CN115292949A (en) | 2022-08-16 | 2022-08-16 | Method and device for evaluating whether redundant array meets replacement requirements |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115292949A true CN115292949A (en) | 2022-11-04 |
Family
ID=83830521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210980764.6A Pending CN115292949A (en) | 2022-08-16 | 2022-08-16 | Method and device for evaluating whether redundant array meets replacement requirements |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115292949A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116168750A (en) * | 2023-04-26 | 2023-05-26 | 长鑫存储技术有限公司 | Memory array repair method |
-
2022
- 2022-08-16 CN CN202210980764.6A patent/CN115292949A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116168750A (en) * | 2023-04-26 | 2023-05-26 | 长鑫存储技术有限公司 | Memory array repair method |
| CN116168750B (en) * | 2023-04-26 | 2023-09-15 | 长鑫存储技术有限公司 | Memory array repair method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7054705B2 (en) | Method of manufacturing semiconductor devices | |
| US7194366B2 (en) | System and method for estimating reliability of components for testing and quality optimization | |
| US8509014B2 (en) | Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs | |
| TWI457942B (en) | Semiconductor wafer and its relief design method | |
| US6446017B1 (en) | Method and system for tracking manufacturing data for integrated circuit parts | |
| US7386418B2 (en) | Yield analysis method | |
| CN106407490A (en) | System and method for discovering unknown problematic patterns in chip design layout | |
| CN115292949A (en) | Method and device for evaluating whether redundant array meets replacement requirements | |
| KR20100038391A (en) | Method and apparatus for monitoring vias in a semiconductor fab | |
| US9455050B2 (en) | Failure diagnosis circuit | |
| US20070114396A1 (en) | Critical area calculation method and yield calculation method | |
| JP3111931B2 (en) | Inspection result analyzer, analysis method, and recording medium recording analysis program | |
| US6499118B1 (en) | Redundancy analysis method and apparatus for ATE | |
| CN106782666A (en) | A kind of three-dimensional stacked memory | |
| JP5342199B2 (en) | Failure rate prediction method, failure rate prediction program, semiconductor manufacturing device management method, and semiconductor device manufacturing method | |
| US20070266358A1 (en) | Yield calculation method | |
| KR101003076B1 (en) | Semiconductor device test apparatus and method | |
| US10789398B2 (en) | Method and apparatus for SOC with optimal RSMA | |
| KR20010006977A (en) | Method and system for analyzing a production failure in a semiconductor device | |
| US8160830B2 (en) | Method of yield management for semiconductor manufacture and apparatus thereof | |
| US20120109561A1 (en) | Wafer test apparatus, wafer test method, and program | |
| KR101074456B1 (en) | Memory test method and system by early termination conditions | |
| TW557528B (en) | Automatic grading system of wafer product and method thereof | |
| TW562947B (en) | Analysis method for memory repair | |
| KR20080096233A (en) | Method of failure analysis on defective semiconductor device and failure analysis system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |