CN115292220A - GPP hardware abstraction layer design method and system based on shared memory mechanism - Google Patents
GPP hardware abstraction layer design method and system based on shared memory mechanism Download PDFInfo
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Abstract
The invention provides a design method of a GPP hardware abstraction layer based on a shared memory mechanism, which comprises the following steps: providing an input-output port for a GPP waveform component; constructing a port priority mapping table, carrying out priority arbitration on data of the GPP waveform assembly, and handing the data to an address mapping module for processing according to the priority of the data in the port priority mapping table; constructing a logical address mapping table and a physical address mapping table, mapping a data destination logical address into an actual physical address, and then delivering the actual physical address to a routing control module; sending data in the MOCB port to a physical bus according to the physical address analyzed by the address mapping module; meanwhile, reading data from the physical address, and pushing the data to the MOCB port; and detecting the abnormality, and sending the abnormality detection result to an upper layer terminal through the drive adapting interface. Each port of the invention is allocated with different priorities and transmit-receive FIFO to shunt data, thereby ensuring the real-time performance of communication and ensuring the reliability of data transmission.
Description
Technical Field
The invention relates to the technical field of electronic equipment, in particular to a method and a system for designing a GPP hardware abstraction layer based on a shared memory mechanism, and also provides a corresponding terminal and a corresponding medium.
Background
Software Communication Architecture (Software Communication Architecture) SCA typically includes heterogeneous processor resources such as GPP, DSP, GPP, etc., and different types of waveform algorithms are deployed respectively. The traditional waveform is deeply coupled with a Hardware platform, the transplantation cost is extremely high, in order to improve the portability of the waveform, software and Hardware are decoupled, the SCA proposes that CORBA (Common Object Request Broker Architecture) communication is used among GPPs, and MHAL (Modem Hardware Abstraction Layer) communication is used among the GPP, the DSP and the GPP. At present, a plurality of mature CORBA products exist in the market and can be directly used, but the research on MHAL in the industry is less, some published researches on MHAL are only on the standard interpretation level to a great extent, the problems of real-time performance, reliability and the like concerned by waveform developers are not explained, and the problems cannot fall to the ground in engineering practice.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a design method of a GPP hardware abstraction layer (namely MOCB, MHAL on Chip Bus) based on a shared memory mechanism, and simultaneously provides a corresponding terminal and medium, aiming at providing requirements which can meet real-time performance, reliability, smooth transplantation and engineering for waveform developers.
According to an aspect of the present invention, a method for designing a GPP hardware abstraction layer based on a shared memory mechanism is characterized by comprising:
providing input-output ports for the GPP waveform components, including a MOCB data port for communication and a MOCB event port for event management;
constructing a port priority mapping table, carrying out priority arbitration on the data of the GPP waveform assembly, and handing the data to an address mapping module for processing according to the priority of the data in the port priority mapping table;
constructing a logical address mapping table and a physical address mapping table, mapping a data destination logical address into an actual physical address, and then delivering the actual physical address to a routing control module;
packaging different physical buses and IO interfaces to construct a driving adaptive interface;
calling a driving adaptation interface, and sending data in the MOCB port to a physical bus according to a physical address analyzed by an address mapping module; meanwhile, reading data from the physical address, and pushing the data to the MOCB port;
and each module carries out abnormity detection and sends the abnormity detection result to an upper layer terminal through the drive adapting interface.
The MOCB port is composed of a data module and an event module;
the data module comprises an MOCB data port, a transmission FIFO buffer area, a receiving FIFO buffer area and a flow control module; wherein:
the MOCB data port is used for data communication between the GPP waveform assembly and assemblies on other processors and supports a synchronous mode and an asynchronous mode; supporting priority configuration, wherein each port corresponds to a priority; supporting the space size allocation of a transmission FIFO buffer area and the space size allocation of a receiving FIFO buffer area; flow control is supported; supporting flow statistics; a reliable transmission mechanism is supported, and reliable transmission of data is ensured through data verification, acknowledgement and overtime retransmission methods;
the flow control module is used for controlling the flow of the receiving buffer area and the sending buffer area, and when the residual space of the sending buffer area is lower than a certain threshold value, a flow control signal is triggered to stop receiving new data; when the residual space of the receiving buffer area is lower than a certain threshold value, triggering a flow control signal and stopping sending new data;
the event module comprises an MOCB event port and an event distribution register management module; wherein the content of the first and second substances,
the MOCB event port provides event management capability for a GPP waveform component;
and the event distribution register management module is used for maintaining a mapping table of event IDs, sub-events, semaphores and logical addresses.
The GPP waveform component transmits data, including: the GPP waveform assembly sends data to a FIFO cache of a MOCB port; and the MOCB port FIFO buffer sends data to a physical bus.
The GPP waveform component sends data to an MOCB port FIFO cache, and the specific steps are as follows:
step 1: the waveform component calls a MOCB sending interface to send data to a MOCB data port;
step 2: the MOCB data port checks whether the transmission FIFO buffer memory is enough, if the space is not enough, the Errorcode is sent to the waveform component, otherwise, the step 3 is carried out;
and 3, step 3: the MOCB data port stores data to an FIFO buffer memory;
and 4, step 4: the MOCB data port flow control module sets the FIFO cache to be in a data to-be-sent state;
and 5: and (5) repeating the step 1 to the step 4.
In the process that the GPP waveform assembly sends data to the FIFO cache of the MOCB port, the conversion process of the MOCB state machine comprises the following steps:
and (3) an idle state: when the FIFO buffer space is not full, the MOCB does nothing, and when the GPP waveform component sends data to the MOCB port, the state is converted into a data receiving state;
receiving a data state: the MOCB port stores data sent by the GPP waveform assembly into an FIFO cache, and if storage fails, the data are converted into an exception handling state; if the storage is successful, judging whether the FIFO cache is full, if so, converting the FIFO cache into a saturated state, otherwise, converting the FIFO cache into a space state;
and (3) saturation state: the MOCB port FIFO cache is full, in the state, the MOCB port does not receive data sent by the GPP waveform assembly any more, and after the data in the FIFO cache are sent to a physical bus, the FIFO cache is converted into an idle state;
exception handling state: in the state, the MOCB performs exception handling operation including exception analysis and exception reporting, and after exception handling is finished, the MOCB is switched to an idle state.
The MOCB port FIFO cache sends data to a physical bus, and the specific steps are as follows:
step 1: waiting for sending a data request, if the GPP waveform assembly sends data to the FIFO cache of the MOCB data port, the flow control module marks the FIFO cache as a state with data to be sent;
step 2: the priority arbitration module carries out priority arbitration on data in FIFO caches of different ports and preferentially processes the data with high priority;
and 3, step 3: the address mapping module maps LD of data to be sent into a physical address;
and 4, step 4: the routing control module calls a driving interface and sends data to a physical bus;
and 5: sending an event to the target component to inform the target component that data arrives;
step 6: checking whether the FIFO buffer has at least one packet of complete data to be sent, and if not, returning to the step 1; otherwise, entering step 7;
and 7: checking whether low-priority data which is waited for the maximum duration but is not sent exists, if so, sending the low-priority data, and returning to the step 3; otherwise, returning to the step 2.
The MOCB port FIFO cache sends data to a physical bus, and the conversion process of the MOCB state machine is as follows:
and (3) an idle state: the MOCB port FIFO cache does not have data, the MOCB does not do any things, and when the data are stored in the FIFO cache, the MOCB port FIFO cache is converted into a data to-be-sent state;
data to be sent state: the state represents that data to be sent to a physical bus in the FIFO buffer, and the MOCB is converted into a data sending state;
the MOCB address analysis module of the sending data state maps the logic address of the data to be sent into a physical address, the routing control module calls a driving interface to send the data to a physical bus, and if the data is abnormal, the data is converted into an abnormal processing state; if the data is successfully transmitted, checking whether the FIFO buffer memory still has data to be transmitted, if the data still has the data to be transmitted, converting the data into a data to be transmitted state, and if the FIFO buffer memory is empty, entering an idle state;
exception handling state: and the MOCB performs exception handling operations including exception analysis and exception reporting, and after the exception handling is finished, checks whether the FIFO cache has data to be sent or not, converts the FIFO cache into a data to be sent state if the FIFO cache has data to be sent, and enters an idle state if the FIFO cache is empty.
The GPP waveform component reads data, including: the informing, by the MOCB port, the GPP waveform component to read the MOCB port and informing, by the GPP waveform component, the GPP waveform component to read data specifically includes:
step 1: the MOCB port waits for receiving an interrupt signal;
step 2: after receiving the interrupt signal, mapping the interrupt number into an event ID;
and 3, step 3: the event distribution register management module analyzes the event ID to obtain a corresponding logical address;
and 4, step 4: the address mapping module maps the logical address into a physical address;
and 5: the routing control module calls a driving interface to obtain a sub-event from the physical bus according to the physical address, if the sub-event is successfully read, the step 6 is executed, otherwise, the step 7 is executed;
step 6: the MOCB port informs the GPP waveform assembly that data is up;
and 7: and the exception handling module is used for carrying out exception handling and reporting exception information.
The reading of data by the GPP waveform component through the MOCB port specifically includes:
step 1: the GPP waveform component receives a data arrival event notice sent by the MOCB port;
step 2: the GPP waveform component checks whether the receiving FIFO buffer space is enough, if the space is not enough, the step 3 is carried out, otherwise, the step 4 is carried out;
and step 3: waiting for the data in the FIFO buffer to be processed, and returning to the step 2 after the data are processed;
and 4, step 4: the GPP waveform component calls the MOCB port to read a data interface;
and 5: the address mapping module converts the logic address into a physical address;
step 6: the routing control module calls a driving interface to read data from a physical bus according to the physical address, if the data are read unsuccessfully, the step 7 is carried out, otherwise, the step 8 is carried out;
and 7: the exception handling module is used for carrying out exception handling and reporting exception information;
and 8: the MOCB port returns data read from the physical bus to the GPP waveform component.
On the other hand, the invention also provides a system for designing a GPP hardware abstraction layer based on a shared memory mechanism, which is characterized by comprising:
the system comprises a MOCB port module, a data interface module and a data interface module, wherein the MOCB port module is used for providing input and output ports for a GPP waveform assembly and comprises a MOCB data port for communication and a MOCB event port for event management;
the priority arbitration module is used for constructing a port priority mapping table and handing data to the address mapping module for processing according to the priority of the data in the port priority mapping table;
the address mapping module is used for constructing and maintaining a logical address and physical address mapping table, mapping the data destination logical address into an actual physical address, and then delivering the actual physical address to the routing control module for processing;
the routing control module is used for calling the driving adaptation interface, and sending data in the MOCB port to a physical bus according to the physical address analyzed by the address mapping module; meanwhile, reading data from the physical address, and pushing the data to the MOCB port;
the driving adaptive interface module is used for encapsulating different physical buses and IO interfaces to construct a driving adaptive interface;
the abnormity detection module is used for carrying out abnormity detection on each module and sending the abnormity detection result to an upper layer terminal through the drive adaptation interface;
according to a third aspect of the present invention, there is provided a terminal comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor being operable to execute the program to perform the method of any of the above, or to operate the system of any of the above.
According to a fourth aspect of the invention, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, is operable to perform the method of, or to run the system of, any of the above.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial effects:
1. ensuring the real-time performance of communication: each port is allocated with different priorities and a transceiving FIFO (first in first out), so that data are shunted and high-priority data are transmitted preferentially;
2. ensuring the reliability of data transmission: for data needing reliable transmission, a port ensures the reliable transmission of the data by methods such as data verification, acknowledgement, overtime retransmission and the like; meanwhile, the anomaly detection module monitors the communication condition of the whole hardware abstraction layer in real time, and analyzes and reports the occurring anomalies;
3. standardized hardware drive interface: a unified standard interface is abstracted from a data receiving and transmitting drive interface, an external drive interface and a radio frequency control interface of bottom hardware, so that the portability of a hardware abstraction layer is improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic diagram of a GPP hardware abstraction layer design system based on a shared memory mechanism according to an embodiment of the present invention.
Fig. 2 is a flow chart of the GPP waveform component sending data to the MOCB port FIFO buffer in a preferred embodiment of the present invention.
Fig. 3 is a state machine transition process diagram of the process of sending data from a GPP waveform component to a MOCB port FIFO buffer in a preferred embodiment of the present invention.
FIG. 4 is a flow chart of the MOCB port FIFO buffer sending data to the physical bus according to a preferred embodiment of the present invention.
FIG. 5 is a state machine transition process diagram of the process of the MOCB port FIFO buffer sending data to the physical bus according to the preferred embodiment of the present invention.
FIG. 6 is a flow chart of the operation of the MOCB notification waveform component to read data in a preferred embodiment of the present invention.
FIG. 7 is a flowchart of the operation of the waveform component to read data through the MOCB port in a preferred embodiment of the present invention.
Detailed Description
The following examples illustrate the invention in detail: the embodiment is implemented on the premise of the technical scheme of the invention, and gives a detailed implementation mode and a specific operation process. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
An embodiment of the present invention provides a method for designing a GPP hardware abstraction layer based on a shared memory mechanism, which can be configured for different physical buses (such as SRIO-DIO, PCIe, EMIF, etc.)
As shown in fig. 1, the method for designing a GPP hardware abstraction layer based on a shared memory mechanism according to this embodiment may include the following steps:
s100 provides input and output ports for GPP waveform components, including a MOCB data port for communication and a MOCB event port for event management;
s101, a port priority mapping table is established, priority arbitration is carried out on data of the GPP waveform assembly, and the data are handed to an address mapping module for processing according to the priority of the data in the port priority mapping table;
s102, a logical address mapping table and a physical address mapping table are constructed, a data destination logical address is mapped into an actual physical address, and then the actual physical address is sent to a routing control module;
s103, packaging different physical buses and IO interfaces to construct a driving adaptive interface;
s104, calling a driving adaptation interface, and sending data in the MOCB port to a physical bus according to a physical address analyzed by the address mapping module; meanwhile, reading data from the physical address, and pushing the data to the MOCB port;
s105, each module carries out abnormity detection and sends the abnormity detection result to an upper layer terminal through the drive adapting interface.
In a preferred embodiment of S100, the MOCB ports are divided into MOCB data ports and MOCB event ports.
The MOCB data port is used for data communication between the GPP waveform assembly and assemblies on other processors, and supports a synchronous mode and an asynchronous mode; supporting priority configuration, wherein each port corresponds to a priority; the size configuration of the transmission FIFO space and the size configuration of the receiving FIFO space are supported, so that a user can reasonably configure the size of the receiving FIFO and the transmitting FIFO according to service requirements, and the space is saved; flow control is supported; flow statistics is supported and is optional; the method supports a reliable transmission mechanism, ensures the reliable transmission of the data through methods such as data verification, acknowledgement, overtime retransmission and the like, but increases the overhead, is suitable for the data without real-time requirement, and is an option.
The MOCB event port provides event management capabilities for waveform components, and maintains a mapping table of event IDs, sub-events, semaphores, and logical addresses via an event distribution register management module.
It should be noted that, the steps in the method provided by the present invention may be implemented by using corresponding modules, devices, units, and the like in the system, and those skilled in the art may implement the composition of the system by referring to the technical solution of the method, that is, the embodiment in the method may be understood as a preferred example for constructing the system, and will not be described herein again.
The technical solutions of the design method and the design system provided by the above embodiments of the present invention are further described below with reference to a specific application example and the accompanying drawings.
The process of sending data by the GPP waveform assembly is divided into two steps, the first step is that the GPP waveform assembly sends the data to the MOCB port FIFO cache, and the second step is that the MOCB port FIFO cache sends the data to a physical bus.
The flow of the GPP waveform component sending data to the MOCB port FIFO buffer is shown in fig. 2, and the specific steps are described as follows:
step 1: the waveform component calls a MOCB sending interface to send data to a MOCB data port;
step 2: the MOCB data port checks whether the transmission FIFO buffer is enough, if the space is not enough, the Errorcode is transmitted to the waveform component, otherwise, the step 3 is carried out;
and 3, step 3: the MOCB data port stores data to an FIFO buffer memory;
and 4, step 4: the MOCB data port flow control module sets the FIFO buffer to be in a state of data to be sent;
and 5: and (5) repeating the step 1 to the step 4.
In the process that the GPP waveform component sends data to the MOCB port FIFO buffer, the conversion process of the MOCB state machine is as shown in fig. 3, and is specifically described as follows:
an idle state: the state that FIFO buffer memory space is not full, in this state, MOCB does nothing, when GPP waveform assembly sends data to MOCB port, will change into and receive the data state;
receiving a data state: in the state, the MOCB port stores the data sent by the GPP waveform assembly into an FIFO cache, and if the storage fails, the data is converted into an exception handling state; if the storage is successful, judging whether the FIFO cache is full, if so, converting the FIFO cache into a saturated state, otherwise, converting the FIFO cache into a space state;
and (3) saturation state: the MOCB port FIFO cache is full, in the state, the MOCB port does not receive data sent by the GPP waveform assembly any more, and after the data in the FIFO cache are sent to a physical bus, the FIFO cache is converted into an idle state;
exception handling state: in the state, the MOCB performs exception handling operation including exception analysis and exception reporting, and after exception handling is finished, the MOCB is switched to an idle state.
Fig. 4 shows a flowchart of sending data to a physical bus by a MOCB data port FIFO buffer, and the specific steps are described as follows:
step 1: waiting for sending a data request, and if the waveform component sends data to an MOCB data port FIFO cache, marking the FIFO cache as a state that the data are to be sent by the flow control module;
step 2: the priority arbitration module carries out priority arbitration on data in FIFO caches of different ports and preferentially processes the data with high priority;
and step 3: the address mapping module maps LD of data to be sent into a physical address;
and 4, step 4: the routing control module calls a driving interface and sends data to a physical bus;
and 5: sending an event to the target component to inform the target component that data arrives;
step 6: checking whether the FIFO buffer has at least one packet of complete data to be sent, and if not, returning to the step 1; otherwise, entering step 7;
and 7: checking whether low-priority data which is waited for the maximum duration but is not sent exists, if so, sending the low-priority data, and returning to the step 3; otherwise, returning to the step 2;
in the process that the MOCB port sends the data in the FIFO buffer to the physical bus, the conversion process of the MOCB state machine is as shown in fig. 5, which is specifically described as follows:
and (3) an idle state: in the state, the MOCB port FIFO cache does not have data, the MOCB does not do anything, and the MOCB port FIFO cache is converted into a data to-be-sent state after the data is stored in the FIFO cache;
data to be sent state: the state represents that data to be sent to a physical bus in the FIFO buffer, and the MOCB is converted into a data sending state;
the data sending state: in the state, the MOCB address analysis module maps the logic address of the data to be sent into a physical address, then calls a driving interface through the routing control module to send the data to a physical bus, and if the data is abnormal, the data is converted into an abnormal processing state; if the data is successfully transmitted, checking whether the FIFO cache has data to be transmitted, if the data is still to be transmitted, converting the data into a data to be transmitted state, and if the FIFO cache is empty, entering an idle state;
exception handling state: in the state, the MOCB performs exception handling operations including exception analysis and exception reporting, and after the exception handling is finished, checks whether the FIFO buffer has data to be sent, if the FIFO buffer has data to be sent, the MOCB is converted into a data to be sent state, and if the FIFO buffer is empty, the MOCB enters an idle state.
The process of the waveform component reading data is also divided into two steps, the first step is that the MOCB informs the waveform component to read the data, and the second step is that the waveform component reads the data through a MOCB port.
The flow of the MOCB notification waveform component for reading data is shown in fig. 6, and the specific steps are described as follows:
step 1: the MOCB waits for receiving an interrupt signal;
step 2: after receiving the interrupt signal, mapping the interrupt number into an event ID;
and 3, step 3: the event distribution register management module analyzes the event ID to obtain a corresponding logical address;
and 4, step 4: the address mapping module maps the logic address into a physical address;
and 5: the route control module calls a drive interface from a physical bus subevent according to the physical address, if the reading is successful, the step 6 is carried out, otherwise, the step 7 is carried out;
step 6: the MOCB informs the waveform component that data is reached;
and 7: and the exception handling module is used for carrying out exception handling and reporting the exception information.
The flow of the waveform component reading data through the MOCB port is shown in fig. 7, and the specific steps are described as follows:
step 1: the GPP waveform component receives a data arrival event notice sent by the MOCB;
step 2: the GPP waveform assembly checks whether the receiving FIFO buffer space is enough, if the space is not enough, the step 3 is carried out, otherwise, the step 4 is carried out;
and 3, step 3: waiting for the data in the FIFO buffer to be processed, and returning to the step 2 after the data are processed;
and 4, step 4: a GPP waveform component calls a MOCB port to read a data interface;
and 5: the address mapping module converts the logic address into a physical address;
step 6: the route control module calls a driving interface to read data from the physical bus according to the physical address, if the reading fails, the step 7 is carried out, otherwise, the step 8 is carried out;
and 7: the exception handling module is used for carrying out exception handling and reporting exception information;
and 8: the MOCB returns the data read from the physical bus to the waveform component.
It should be noted that: the flowcharts in the figures illustrate the method functions and operations according to preferred embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions. It is well known to those skilled in the art that implementation by hardware, implementation by software, and implementation by a combination of software and hardware are equivalent.
The above embodiments of the present invention are not exhaustive of the techniques known in the art.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.
Claims (13)
1. A method for designing a GPP hardware abstraction layer based on a shared memory mechanism is characterized by comprising the following steps:
providing input and output ports for a GPP waveform component, including a MOCB data port for communication and a MOCB event port for event management;
constructing a port priority mapping table, carrying out priority arbitration on the data of the GPP waveform assembly, and handing the data to an address mapping module for processing according to the priority of the data in the port priority mapping table;
constructing a logical address mapping table and a physical address mapping table, mapping a data destination logical address into an actual physical address, and then delivering the actual physical address to a routing control module;
packaging different physical buses and IO interfaces to construct a driving adaptive interface;
calling a driving adaptation interface, and sending data in the MOCB port to a physical bus according to a physical address analyzed by an address mapping module; meanwhile, reading data from the physical address, and pushing the data to the MOCB port;
and each module carries out abnormity detection and sends the abnormity detection result to an upper layer terminal through the drive adapting interface.
2. The method of claim 1, wherein the MOCB port is composed of a data module and an event module;
the data module comprises an MOCB data port, a transmission FIFO buffer area, a receiving FIFO buffer area and a flow control module; wherein:
the MOCB data port is used for carrying out data communication between the GPP waveform assembly and assemblies on other processors and supporting a synchronous mode and an asynchronous mode; supporting priority configuration, wherein each port corresponds to a priority; supporting the space size allocation of a transmission FIFO buffer area and the space size allocation of a receiving FIFO buffer area; flow control is supported; supporting flow statistics; a reliable transmission mechanism is supported, and reliable transmission of data is ensured through data verification, acknowledgement and overtime retransmission methods;
the flow control module is used for controlling the flow of the receiving buffer area and the sending buffer area, and when the residual space of the sending buffer area is lower than a certain threshold value, a flow control signal is triggered to stop receiving new data; when the residual space of the receiving buffer area is lower than a certain threshold value, triggering a flow control signal and stopping sending new data;
the event module comprises an MOCB event port and an event distribution register management module; wherein the content of the first and second substances,
the MOCB event port provides event management capability for a GPP waveform assembly;
and the event distribution register management module is used for maintaining a mapping table of event IDs, sub-events, semaphores and logical addresses.
3. The method according to claim 1 or 2, wherein the GPP waveform component sends data, and the method comprises: the GPP waveform assembly sends data to a FIFO cache of a MOCB port; and the MOCB port FIFO buffer sends data to a physical bus.
4. The GPP hardware abstraction layer design method based on a shared memory mechanism according to claim 3, wherein the GPP waveform component sends data to a MOCB port FIFO cache, and the specific steps are as follows:
step 1: the waveform component calls a MOCB sending interface to send data to a MOCB data port;
and 2, step: the MOCB data port checks whether the transmission FIFO buffer memory is enough, if the space is not enough, the Errorcode is sent to the waveform component, otherwise, the step 3 is carried out;
and step 3: the MOCB data port stores data to an FIFO buffer memory;
and 4, step 4: the MOCB data port flow control module sets the FIFO cache to be in a state of data to be sent;
and 5: and (5) repeating the step 1 to the step 4.
5. The method as claimed in claim 4, wherein in the process of sending the data to the FIFO buffer of the MOCB port by the GPP waveform component, the conversion process of the MOCB state machine includes:
an idle state: when the FIFO buffer space is not full, the MOCB does nothing, and when the GPP waveform component sends data to the MOCB port, the state is converted into a data receiving state;
receiving a data state: the MOCB port stores data sent by the GPP waveform assembly into an FIFO cache, and if storage fails, the data are converted into an abnormal processing state; if the storage is successful, judging whether the FIFO cache is full, if so, converting the FIFO cache into a saturated state, otherwise, converting the FIFO cache into a space state;
and (3) saturation state: the MOCB port FIFO cache is full, in the state, the MOCB port does not receive data sent by the GPP waveform assembly any more, and after the data in the FIFO cache are sent to a physical bus, the FIFO cache is converted into an idle state;
exception handling state: in the state, the MOCB performs exception handling operation including exception analysis and exception reporting, and after exception handling is finished, the MOCB is switched to an idle state.
6. The method according to claim 4, wherein the MOCB port FIFO buffer sends data to a physical bus, and the specific steps are as follows:
step 1: waiting for sending a data request, if the GPP waveform assembly sends data to the FIFO cache of the MOCB data port, the flow control module marks the FIFO cache as a state with data to be sent;
and 2, step: the priority arbitration module carries out priority arbitration on data in FIFO caches of different ports and preferentially processes the data with high priority;
and step 3: the address mapping module maps LD of data to be sent into a physical address;
and 4, step 4: the routing control module calls a driving interface and sends data to a physical bus;
and 5: sending an event to the target component to inform the target component that data arrives;
step 6: checking whether the FIFO buffer has at least one packet of complete data to be sent, and returning to the step 1 if the FIFO buffer does not have at least one packet of complete data to be sent; otherwise, entering step 7;
and 7: checking whether low-priority data which is waited for the maximum duration but is not sent exists, if so, sending the low-priority data, and returning to the step 3; otherwise, returning to the step 2.
7. The method of claim 6, wherein the MOCB port FIFO buffer sends data to a physical bus, and the MOCB state machine transition process is as follows:
and (3) an idle state: the MOCB port FIFO cache does not have data, the MOCB does not do any things, and when the data are stored in the FIFO cache, the MOCB port FIFO cache is converted into a data to-be-sent state;
data to be sent state: the state represents data to be sent to a physical bus in the FIFO cache, and the MOCB is converted into a data sending state;
the MOCB address analysis module maps a logic address of data to be sent into a physical address, the route control module calls a driving interface to send the data to a physical bus, and if the data are abnormal, the MOCB address analysis module is converted into an abnormal processing state; if the data is successfully transmitted, checking whether the FIFO cache has data to be transmitted, if the data is still to be transmitted, converting the data into a data to be transmitted state, and if the FIFO cache is empty, entering an idle state;
exception handling state: and the MOCB performs exception handling operations including exception analysis and exception reporting, and after the exception handling is finished, checks whether the FIFO cache has data to be sent or not, converts the FIFO cache into a data to be sent state if the FIFO cache has data to be sent, and enters an idle state if the FIFO cache is empty.
8. The method according to claim 1 or 2, wherein the reading of the data by the GPP waveform component comprises: and the MOCB port informs the GPP waveform assembly to read data, and the GPP waveform assembly reads data through the MOCB port.
9. The method according to claim 8, wherein the MOCB port notifies the GPP waveform component to read data, and the method specifically includes:
step 1: the MOCB port waits for receiving an interrupt signal;
step 2: after receiving the interrupt signal, mapping the interrupt number into an event ID;
and 3, step 3: the event distribution register management module analyzes the event ID to obtain a corresponding logical address;
and 4, step 4: the address mapping module maps the logical address into a physical address;
and 5: the routing control module calls a drive interface from a physical bus subevent according to a physical address, if the reading is successful, the step 6 is carried out, otherwise, the step 7 is carried out;
step 6: the MOCB port informs the GPP waveform assembly that data is reached;
and 7: and the exception handling module is used for carrying out exception handling and reporting exception information.
10. The method of claim 8, wherein the reading of data by the GPP waveform component through the MOCB port specifically includes:
step 1: the GPP waveform component receives a data arrival event notice sent by the MOCB port;
step 2: the GPP waveform assembly checks whether the buffer space of the receiving FIFO is enough, if the space is not enough, the step 3 is carried out, otherwise, the step 4 is carried out;
and step 3: waiting for the data in the FIFO buffer to be processed, and returning to the step 2 after the data are processed;
and 4, step 4: the GPP waveform component calls the MOCB port to read a data interface;
and 5: the address mapping module converts the logic address into a physical address;
step 6: the routing control module calls a driving interface to read data from a physical bus according to the physical address, if the data are read unsuccessfully, the step 7 is executed, otherwise, the step 8 is executed;
and 7: the exception handling module is used for carrying out exception handling and reporting exception information;
and step 8: the MOCB port returns data read from the physical bus to the GPP waveform component.
11. A system for designing a GPP hardware abstraction layer based on a shared memory mechanism is characterized by comprising:
the system comprises a MOCB port module, a data interface module and a data interface module, wherein the MOCB port module is used for providing input and output ports for a GPP waveform assembly and comprises a MOCB data port for communication and a MOCB event port for event management;
the priority arbitration module is used for constructing a port priority mapping table and handing data to the address mapping module for processing according to the priority of the data in the port priority mapping table;
the address mapping module is used for constructing and maintaining a logical address and physical address mapping table, mapping the data destination logical address into an actual physical address, and then delivering the actual physical address to the routing control module for processing;
the routing control module is used for calling the driving adaptation interface, and sending data in the MOCB port to a physical bus according to the physical address analyzed by the address mapping module; meanwhile, reading data from the physical address, and pushing the data to the MOCB port;
the driving adaptation interface module is used for encapsulating different physical buses and IO interfaces to construct a driving adaptation interface;
and the abnormity detection module is used for carrying out abnormity detection on each module and sending the abnormity detection result to an upper layer terminal through the drive adaptation interface.
12. A terminal comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor is operable to perform the method of any one of claims 1 to 10 or to operate the system of claim 11 when executing the program.
13. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 10 or to carry out the system of claim 11.
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