CN115275782A - Laser radar multi-junction VCSEL array chip based on P substrate growth and preparation method thereof - Google Patents

Laser radar multi-junction VCSEL array chip based on P substrate growth and preparation method thereof Download PDF

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Publication number
CN115275782A
CN115275782A CN202211029868.5A CN202211029868A CN115275782A CN 115275782 A CN115275782 A CN 115275782A CN 202211029868 A CN202211029868 A CN 202211029868A CN 115275782 A CN115275782 A CN 115275782A
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substrate
bragg reflector
type bragg
type
laser radar
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杨旭
郭丁凯
蔡建新
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Wuhan Qianmu Laser Co ltd
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Wuhan Qianmu Laser Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18322—Position of the structure
    • H01S5/18325—Between active layer and substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18322—Position of the structure
    • H01S5/1833—Position of the structure with more than one structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2004—Confining in the direction perpendicular to the layer structure
    • H01S5/2018—Optical confinement, e.g. absorbing-, reflecting- or waveguide-layers
    • H01S5/2027—Reflecting region or layer, parallel to the active layer, e.g. to modify propagation of the mode in the laser or to influence transverse modes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/42—Arrays of surface emitting lasers
    • H01S5/423—Arrays of surface emitting lasers having a vertical cavity

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Semiconductor Lasers (AREA)

Abstract

The invention relates to a preparation method of a laser radar multi-junction VCSEL array chip based on P substrate growth, which comprises the following steps: s1, selecting a P-type substrate, and growing a plurality of pairs of P-type Bragg reflectors on the P-type substrate; s2, after the growth is finished, a plurality of groups of quantum wells are grown on the P-type Bragg reflector to serve as light emitting areas, and the light emitting areas comprise one or more groups of tunnel junctions and oxide layers; s3, growing a plurality of pairs of N-type Bragg reflectors on the light emitting region; and S4, growing a contact layer with a highly doped surface on the N-type Bragg reflector after the growth is finished. The laser radar multi-junction VCSEL array chip based on P substrate growth is further included. According to the invention, the P-type Bragg reflector is grown on the P substrate, so that the heat source is closer to the heat sink substrate with good heat conductivity, the heat generated in the operation of the VCSEL device is rapidly dissipated, the junction temperature is reduced, and the drift of the gain curve of the active region along with the temperature is reduced, thereby ensuring that the substrate temperature has higher gain from normal temperature to high temperature.

Description

Laser radar multi-junction VCSEL array chip based on P substrate growth and preparation method thereof
Technical Field
The invention relates to the technical field of lasers, in particular to a laser radar multi-junction VCSEL array chip based on P substrate growth and a preparation method thereof.
Background
A VCSEL (Vertical Cavity Emitting Laser), which is an acronym for Vertical Cavity Surface Emitting Laser, is a semiconductor-based Laser diode, and is different from a conventional top and side Emitting LED and an edge Emitting Laser, and the VCSEL can vertically emit a more efficient light beam from its Surface. Since 1977 related concepts were proposed by e.g. Shiga-Jian (Kenichi Iga) of Tokyo industry university in Japan, they have been developed for over forty years. Since it has the outstanding advantages of low threshold, small far field divergence angle, high modulation rate, easy realization of single longitudinal mode work, easy two-dimensional integration and the like, through development for many years, the VCSEL has been widely applied in the fields of broadband ethernet, high-speed data communication, optical interconnection, three-dimensional sensing, optical integrated elements and the like.
In recent years, due to the rise of applications of laser radars and the explosion of the market, VCSELs have also received attention as one of their important light-emitting devices. Its two-dimensional addressable functionality and cost have advantages over other schemes, however VCSELs have deficiencies in power density compared to edge-emitting laser light sources. In order to increase the power density of the VCSEL, a multi-PN junction VCSEL chip is mainly used to increase the optical power output. However, due to the multiple sets of active regions and the multiple sets of tunnel junctions in the structure, the amount of heat generated during operation is significantly higher than in conventional single junction VCSELs.
A schematic diagram 1 of a VCSEL array structure for a lidar is shown, in which a cross-sectional view of two adjacent light emitting holes is shown. The structure is formed by epitaxial material growth on N-substrate, and adopts AlGaAs material system in 850/905/940nm wave band, which comprises about 35 pairs of N-doped DBR (Bragg reflector), multiple active regions, tunnel junction, and about 20 pairs of P-doped DBR. The heat source is the heat generated by the electron-hole recombination in the active region, the joule heat generated when the current passes through the P-type Bragg reflector, and the joule heat generated when the current passes through the N-type Bragg reflector. The mobility of the holes (150 cm 2/V/s) is far smaller than that of the electrons (2500 cm 2/V/s), and the resistance of the P-semiconductor (taking the holes as the majority carriers) is far larger than that of the N-semiconductor (taking the electrons as the majority carriers), so that the heat generated in the P-type Bragg reflector is far larger than that of the N-type Bragg reflector. Meanwhile, the substrate surface of the multi-junction VCSEL chip is generally required to be used by being attached to an aluminum nitride heat sink, the high thermal conductivity (320W/m.K) of the multi-junction VCSEL chip is favorable for heat dissipation, and air is used as a poor heat conductor and is only 0.03W/m.K in thermal conductivity, so that the multi-junction VCSEL chip is not favorable for heat dissipation. Under the existing structure, a heat source generated by the P-type Bragg reflector can enter the heat sink to dissipate heat after passing through the oxide layer/the active region/the N-type Bragg reflector, so that the junction temperature of the active region is further increased, the light output power is reduced, and the service life is shortened.
Disclosure of Invention
The invention aims to provide a laser radar multi-junction VCSEL array chip based on P substrate growth and a preparation method thereof, which can at least solve part of defects in the prior art.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions: a laser radar multi-junction VCSEL array chip based on P substrate growth and a preparation method thereof comprise the following steps:
s1, selecting a P-type substrate, and growing a plurality of pairs of P-type Bragg reflectors on the P-type substrate;
s2, after the growth is finished, a plurality of groups of quantum wells are grown on the P-type Bragg reflector to serve as light emitting areas, and the light emitting areas comprise one or more groups of tunnel junctions and oxidation layers;
s3, growing a plurality of pairs of N-type Bragg reflectors on the light emitting areas;
and S4, growing a contact layer with a highly doped surface on the N-type Bragg reflector after the growth is finished.
Furthermore, the doping concentration of the P-type substrate is 1-2E 18/cm 3 In between.
Furthermore, the number of the P-type Bragg reflectors is 30-40.
Further, the P-type Bragg reflector assembly is 5-20% AlGaAs or 82-92% AlGaAs.
Furthermore, the N-type Bragg reflector has 18-26 pairs.
Further, the composition of the N-type Bragg reflector is 5-20% AlGaAs/82-92% by weight.
Further, the contact layer is highly doped at 1E19cm 3 The above.
Further, defining a layer on the surface of the N-type Bragg reflector by photoetching, etching downwards by RIE-ICP, and sequentially etching the N-type Bragg reflector, the quantum well and part of the P-type Bragg reflector.
Further, the contact layer is an N-contact layer, and silicon nitride holes are formed in the N-contact layer and electroplated.
Further, after the electroplating is finished, etching of a front cutting path of the chip is carried out, the back substrate is thinned to be 100 microns thick, evaporation and electroplating of back metal are carried out, and high-temperature alloy is carried out.
Compared with the prior art, the invention has the beneficial effects that: a laser radar multi-junction VCSEL array chip based on P substrate growth is characterized in that a P-type Bragg reflector and a main heat source in a VCSEL device are arranged in an active region, the P-type Bragg reflector is grown on the P substrate, so that the heat source is closer to a heat sink base plate (320W/m.K) with good heat conductivity, heat generated in the VCSEL device during working is rapidly dissipated, and the junction temperature is reduced. The method is beneficial to reducing the drift of the gain curve of the active region along with the temperature, thereby ensuring that the substrate temperature has higher gain from normal temperature to high temperature, and the power of the growth of the substrate is 15% higher than that of the growth of the traditional N-substrate.
Drawings
FIG. 1 is a schematic diagram of a conventional laser radar multi-junction VCSEL array chip;
fig. 2 is a schematic diagram of a laser radar multi-junction VCSEL array chip based on P-substrate growth according to an embodiment of the present invention;
fig. 3 is a power comparison graph of a conventional N-substrate and a P-substrate provided in this example.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 2 and fig. 3, an embodiment of the present invention provides a laser radar multi-junction VCSEL array chip, including a heat sink substrate 1, where a P-type substrate 2, a P-type bragg reflector 3, a light emitting region 4, and an N-type bragg reflector 5 are sequentially disposed on the heat sink substrate 1, and the light emitting region 4 is used for generating laser light; the N-type Bragg reflector 5 is sunken downwards to form a groove, the groove sequentially penetrates through the N-type Bragg reflector 5, the light emitting area 4 and the groove bottom of the groove to extend into the P-type Bragg reflector 3, and N contact metal 6 is arranged on the surface of the N-type Bragg reflector 5 and in the groove. In fig. 1 and 2, a represents electron-resistance heat, b represents heat generation of electron-hole pairs, c represents hole-resistance heat, and an arrow at the notch 12 represents emitted laser light. In this embodiment, the groove extends all the way to the P-type bragg mirror 3, and then the N-contact metal 6 is prepared in the groove. The P-type Bragg reflector 3 and the active region are main heat sources in the VCSEL device, and the P-type Bragg reflector 3 is grown on the P substrate, so that the heat sources are closer to the heat sink base plate 1 (320W/m.K) with good heat conductivity, heat generated in the operation of the VCSEL device is rapidly dissipated, and the junction temperature is reduced. The method is beneficial to reducing the drift of the gain curve of the active region along with the temperature, thereby ensuring that the substrate temperature has higher gain from normal temperature to high temperature, and the power of the chip is 15% higher than that of a chip grown by the traditional N-substrate, such as the chip shown in figure 1.
As an optimized solution of the embodiment of the present invention, please refer to fig. 2 and fig. 3, the light emitting region 4 has a quantum well 7, an oxide layer 8 and a tunnel junction 9 therein, and the quantum well 7, the oxide layer 8 and the tunnel junction 9 are sequentially disposed along the direction from the P-type substrate 2 to the N-type bragg reflector 5. Quantum well 7, oxide layer 8 and tunnel junction 9 all have a plurality ofly, follow P type substrate 2 to N type Bragg reflector 5's direction, one quantum well 7, one oxide layer 8 and one a set of unit is constituteed to tunnel junction 9, and multiunit is followed P type substrate 2 to N type Bragg reflector 5's direction sets gradually. In this embodiment, as in fig. 2 and 3, only the quantum well 7, the oxide layer 8, and the tunnel junction 9 in the lowermost cell are shown. The working principle of the light emitting region 4 is: electrons and holes flow into the semiconductor material through the metal covered by the P-type substrate 2 and the N-type substrate respectively, electron-hole pair recombination is carried out in the quantum well 7 through the P-type Bragg reflector 3 and the N-type Bragg reflector 5 respectively, and energy released by the recombination appears in the form of laser. The region between the P-type bragg reflector 3 and the N-type bragg reflector 5 forms an optical resonant cavity of the laser, and the oxide layer 8 can ensure high photoelectric conversion efficiency by controlling electrons and photons transversely.
Referring to fig. 2 and 3 as an optimized solution of the embodiment of the present invention, a P-type metal 10 is disposed between the heat sink substrate 1 and the P-type substrate 2. In the present embodiment, the heat conduction efficiency can be improved by the P-type metal 10. The P-type metal 10 is prior art and may be, for example, a Ti/Pt/Au system.
As an optimized solution of the embodiment of the present invention, please refer to fig. 2 and fig. 3, the light emitting region 4 has at least one light emitting hole 11 therein. The N contact metal 6 may be a Ge/Au system having a notch 12 for emitting laser light generated from the light emitting hole 11. In the present embodiment, the laser light generated in the light emitting hole 11 is emitted from the notch 12. Preferably, an electrically insulating region 13 is further included, said light emitting aperture 11 being located in said electrically insulating region 13, the light emitting aperture 11 being obtained by the electrically insulating region 13. The electrically insulating region 13 is an ion implanted region.
As an optimized scheme of the embodiment of the invention, the number of the P-type Bragg reflectors 3 is 30-40. The N-type Bragg reflector 5 has 18-26 pairs. The thickness of the P-type substrate 2 is 100 μm.
Referring to fig. 2 and 3, the above chip has a corresponding manufacturing method, which specifically includes the following steps: s1, selecting a P-type substrate 2, and growing a plurality of pairs of P-type Bragg reflectors 3 on the P-type substrate 2; s2, after the growth is finished, a plurality of groups of quantum wells 7 are grown on the P-type Bragg reflector 3 to serve as light emitting areas 4, and the light emitting areas 4 comprise one or more groups of tunnel junctions 9 and oxidation layers 8; s3, growing a plurality of pairs of N-type Bragg reflectors 5 on the light emitting region 4; and S4, growing a contact layer with a highly doped surface on the N-type Bragg reflector 5 after the growth is finished. In the embodiment, the P-type bragg reflector 3 and the active region are main heat sources in the VCSEL device, and the P-type bragg reflector 3 is grown on the P substrate, so that the heat sources are closer to the heat sink substrate 1 (320W/m.k) with good heat conductivity, heat generated in the operation of the VCSEL device is rapidly dissipated, and the junction temperature is reduced. The method is beneficial to reducing the drift of the gain curve of the active region along with the temperature, thereby ensuring that the substrate temperature has higher gain from normal temperature to high temperature, and the power of the growth of the substrate is 15% higher than that of the growth of the traditional N-substrate. Specifically, when a chip is prepared, the P-type bragg reflector 3 is grown and prepared on the P-type substrate 2, so that the P-type bragg reflector 3 with the largest heat quantity can quickly transfer the heat quantity to the P-metal and dissipate the heat through the heat sink substrate 1, and compared with the conventional air heat dissipation, the heat dissipation efficiency can be greatly improved, and the junction temperature is reduced. Given a substrate temperature of 50 ℃, a junction temperature of the conventional VCSEL in figure 1 can reach about 85-95 ℃ at a junction temperature at 5ns,0.1% duty cycle of the drive circuit, and a typical operating current. In the structure of the embodiment, the junction temperature is only 70-75 ℃ under the same working temperature. The optimized lifetime can be up to about 3.2 times the lifetime before optimization, as calculated according to the equations for the arrhenius lifetime assessment.
As an optimized scheme of the embodiment of the invention, please refer to FIGS. 2 and 3, the doping concentration of the P-type substrate 2 is 1-2E 18/cm 3 In between. The number of the P-type Bragg reflectors 3 is 30-40. The P-type Bragg reflector 3 has a composition of 5-20% of AlGaAs or 82-92% of AlGaAs. The number of the N-type Bragg reflectors 5 is 18-26. The composition of the N-type Bragg reflector 5 is 5-20% of AlGaAs/82-92% of AlGaAs. The contact layer is highly doped at 1E19cm 3 The above. In the present embodiment, the material parameters are adopted to obtain the best heat dissipation effect.
Referring to fig. 2 and 3 as an optimized scheme of the embodiment of the present invention, the step of growing the contact layer is to define the layer by photolithography, perform the ring-shaped N contact metal 6 on the surface of the epitaxial layer, and plate silicon nitride for protection.
As an optimized scheme of the embodiment of the present invention, please refer to fig. 2 and fig. 3, a layer is defined on the surface of the N-type bragg reflector 5 by photolithography, and is etched downward by RIE-ICP, and the N-type bragg reflector 5, the quantum well 7, and a portion of the P-type bragg reflector 3 are sequentially etched. The N contact metal 6 enters into this etching depth.
As an optimization scheme of the embodiment of the present invention, referring to fig. 2 and fig. 3, the preparation of the multiple oxide layers 8 specifically includes: an oxidation process is carried out in a water oxygen furnace to form one or more oxide layers 8 which are coated with silicon nitride for protection. Ion implantation then assists in defining the current confinement region, opening a silicon nitride opening in the N-contact layer, and electroplating. And then etching a cutting channel on the front surface of the chip, thinning the substrate on the back surface of the chip to the thickness of 100 microns, performing evaporation and electroplating on metal on the back surface, performing high-temperature alloy, and finally cutting, testing and sorting the chip.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. A preparation method of a laser radar multi-junction VCSEL array chip based on P substrate growth is characterized by comprising the following steps:
s1, selecting a P-type substrate, and growing a plurality of pairs of P-type Bragg reflectors on the P-type substrate;
s2, after the growth is finished, a plurality of groups of quantum wells are grown on the P-type Bragg reflector to serve as light emitting areas, and the light emitting areas comprise one or more groups of tunnel junctions and oxidation layers;
s3, growing a plurality of pairs of N-type Bragg reflectors on the light emitting areas;
and S4, growing a contact layer with a highly doped surface on the N-type Bragg reflector after the growth is finished.
2. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, characterized in that: the doping concentration of the P-type substrate is 1-2E 18/cm 3 In the meantime.
3. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, characterized in that: the number of the P-type Bragg reflectors is 30-40.
4. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, wherein the method comprises the following steps: the P-type Bragg reflector assembly is 5-20% AlGaAs or 82-92% AlGaAs.
5. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, wherein the method comprises the following steps: the N-type Bragg reflector has 18-26 pairs.
6. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, characterized in that: the composition of the N-type Bragg reflector is 5-20% of AlGaAs/82-92% of AlGaAs.
7. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, characterized in that: the contact layer is highly doped at 1E19cm 3 The above.
8. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, characterized in that: and defining a layer on the surface of the N-type Bragg reflector by photoetching, etching downwards by RIE-ICP, and sequentially etching the N-type Bragg reflector, the quantum well and part of the P-type Bragg reflector.
9. The method for preparing the laser radar multi-junction VCSEL array chip based on the P substrate growth, according to claim 1, characterized in that: the contact layer is an N-contact layer, and silicon nitride openings are formed in the N-contact layer and are electroplated.
10. The laser radar multi-junction VCSEL array chip based on P substrate growth is characterized in that: the laser comprises a heat sink substrate, wherein a P-type substrate, a P-type Bragg reflector, a light emitting area and an N-type Bragg reflector are sequentially arranged on the heat sink substrate, and the light emitting area is used for generating laser; and the N-type Bragg reflector is downwards sunken to form a groove, the groove sequentially penetrates through the N-type Bragg reflector and the light emitting region, the groove bottom of the groove extends into the P-type Bragg reflector, and N contact metals are arranged on the surface of the N-type Bragg reflector and in the groove.
CN202211029868.5A 2022-08-25 2022-08-25 Laser radar multi-junction VCSEL array chip based on P substrate growth and preparation method thereof Pending CN115275782A (en)

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