CN115274695A - Array substrate and manufacturing method thereof - Google Patents
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- CN115274695A CN115274695A CN202210806790.7A CN202210806790A CN115274695A CN 115274695 A CN115274695 A CN 115274695A CN 202210806790 A CN202210806790 A CN 202210806790A CN 115274695 A CN115274695 A CN 115274695A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The array substrate and the manufacturing method of the array substrate provided by the embodiment of the application comprise a substrate, an active layer and a source drain layer; wherein the active layer is formed using a crystalline oxide semiconductor material. In addition, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and the conductive regions contain doped particles, so that a crystalline oxide semiconductor thin film transistor device with a specific structure is formed, the mobility of the array substrate can be greatly improved, the driving characteristic can be improved, and the stability of the array substrate can be improved. Therefore, by adopting the array substrate provided by the embodiment of the application, the stability of the device can be ensured on the basis of improving the mobility of the device.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a manufacturing method of the array substrate.
Background
Currently, semiconductor materials have been widely used in the field of semiconductor displays. The oxide semiconductor has high mobility and low leak current characteristics compared to an amorphous silicon material. At present, all oxide semiconductor materials commonly used are amorphous.
Among them, amorphous oxide semiconductors having better uniformity than low-temperature polysilicon have relatively low mobility, but cannot satisfy the driving requirements of high-quality display panels. Specifically, in order to further improve the quality of the display panel, it is necessary to improve the driving current capability of the driving circuit and to reduce the size of the driving circuit, and the conventional amorphous oxide semiconductor material has a problem of reduced device stability due to insufficient mobility.
Therefore, how to provide an array substrate with sufficient mobility without degrading the device stability is a difficult problem for the existing panel manufacturers to overcome.
Disclosure of Invention
An object of the embodiments of the present application is to provide an array substrate and a method for manufacturing the array substrate, which can solve the technical problem that the stability of a device is reduced due to insufficient mobility of a conventional amorphous oxide semiconductor material used in an existing array substrate.
An embodiment of the present application provides an array substrate, including:
a substrate comprising a first side and a second side disposed opposite one another;
the active layer is arranged on the first surface, the material of the active layer is a crystalline oxide semiconductor, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and doped particles are arranged in the conductive regions;
and the source drain layer is arranged on one surface of the active layer, which is far away from the substrate, and is connected with the conductive region.
In the array substrate of the present application, the crystalline oxide semiconductor has a grain size of 10 nm to 1000 nm.
In the array substrate, the doping particles include one or more of hydrogen, helium, boron, aluminum, nitrogen, fluorine, phosphorus, argon, and sulfur.
The application array substrate in, array substrate still includes insulating buffer layer and interlayer insulation layer, insulating buffer layer is located the substrate with between the active layer, interlayer insulation layer sets up the active layer is kept away from in the one side of substrate, just be equipped with the through-hole on the interlayer insulation layer, source drain layer warp the through-hole with the active layer is connected.
In the array substrate, the array substrate further comprises a first gate layer and a first gate insulating layer, the first gate insulating layer is located on one surface, away from the substrate, of the active layer, and the first gate layer is located on one surface, away from the substrate, of the first gate insulating layer.
In the array substrate, the first gate layer includes a first gate sublayer, a second gate sublayer and a third gate sublayer, which are sequentially stacked, and the material of the first gate sublayer is the same as that of the third gate sublayer.
In the array substrate described in the present application, the array substrate further includes a second gate layer and a second gate insulating layer, the second gate layer and the second gate insulating layer are located between the substrate and the active layer, the second gate layer is located on the first surface, and the second gate insulating layer is located the second gate layer is far away from the substrate on one surface.
The embodiment of the present application further provides a manufacturing method of an array substrate, where the manufacturing method includes:
providing a substrate;
forming an active layer on the substrate, wherein the active layer is made of a crystalline oxide semiconductor, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and doped particles are arranged in the conductive regions;
and forming a source drain layer on the active layer, wherein the source drain layer is connected with the conductive region.
In the method for manufacturing an array substrate, the step of forming an active layer on the substrate includes:
forming an amorphous oxide semiconductor layer over the substrate;
performing heat treatment on the amorphous oxide semiconductor layer to form a crystalline oxide semiconductor layer;
performing an etching process on the crystalline oxide semiconductor layer to form an active layer;
and injecting doping particles into two ends of the active layer to form a channel region and conductive regions positioned on two sides of the channel region.
In the method for manufacturing an array substrate, the step of forming an active layer on the substrate includes:
directly depositing a crystalline oxide semiconductor layer on the substrate;
performing an etching process on the crystalline oxide semiconductor layer to form an active layer;
and injecting doping particles into two ends of the active layer to form a channel region and conductive regions positioned on two sides of the channel region.
The array substrate and the manufacturing method of the array substrate provided by the embodiment of the application comprise a substrate, an active layer and a source drain layer; wherein the active layer is formed using a crystalline oxide semiconductor material. In addition, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and the conductive regions contain doped particles, so that a crystalline oxide semiconductor thin film transistor device with a specific structure is formed, the mobility of the array substrate can be greatly improved, the driving characteristic can be improved, and the stability of the array substrate can be improved. Therefore, by adopting the array substrate provided by the embodiment of the application, the stability of the device can be ensured on the basis of improving the mobility of the device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a first implementation manner of an array substrate provided in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a second implementation manner of an array substrate provided in an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a third embodiment of an array substrate according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a fourth implementation manner of an array substrate provided in this application example.
Fig. 5 is a schematic structural diagram of a fifth implementation manner of an array substrate provided in an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a sixth implementation manner of an array substrate provided in an embodiment of the present application.
Fig. 7 is a schematic flowchart of a manufacturing method of a display panel according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram of a display panel corresponding to step 201 of a method for manufacturing a display panel according to an embodiment of the present disclosure.
Fig. 9 is a sub-flow diagram illustrating a manufacturing method of a display panel according to an embodiment of the present disclosure.
Fig. 10 is a schematic structural diagram of a display panel corresponding to step 2021 of a method for manufacturing a display panel according to an embodiment of the present application.
Fig. 11 is a schematic view of a display panel structure corresponding to step 2023 of a method for manufacturing a display panel according to an embodiment of the present application.
Fig. 12 is a schematic view of a display panel structure corresponding to step 2024 of a method for manufacturing a display panel according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of a display panel corresponding to step 203 of the method for manufacturing a display panel according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first implementation manner of an array substrate according to an embodiment of the present disclosure. As shown in fig. 1, an array substrate 10 provided in the embodiment of the present application includes a substrate 101, an active layer 102, and a source/drain layer 103. The substrate 101 includes a first side 101a and a second side 101b disposed opposite to each other. The active layer 102 is disposed on the first face 101 a. The source and drain layers 103 are disposed on a side of the active layer 102 remote from the substrate 101.
The active layer 102 includes a channel region 102a and conductive regions 102b on two sides of the channel region 102 a. The conductive region 102b is provided with doped particles therein. The material of the active layer 102 is a crystalline oxide semiconductor. The source drain layer 103 is connected to the conductive region 102b.
In the prior art, the material of the active layer is generally an amorphous high mobility semiconductor material. Specifically, the material of the active layer is typically indium gallium tin oxide. Although the active layer made of the material can improve the mobility of the array substrate to some extent, the stability of the array substrate is reduced.
In the embodiment of the present application, the material of the active layer 102 is a crystalline oxide semiconductor. The active layer 102 is made of a crystalline oxide semiconductor, and the stability of the device can be ensured on the basis of improving the mobility of the array substrate 10.
Wherein a crystal grain size of the crystalline oxide semiconductor is 10 nm to 1000 nm. Specifically, the crystal grain size of the crystalline oxide semiconductor is 10 nm, 50 nm, 110 nm, 200 nm, 350 nm, 500 nm, 700 nm, 900 nm, or 1000 nm. The specific size of the crystal grains of the crystalline oxide semiconductor is determined by the specific requirements of the array substrate 10.
Among them, it should be noted that by defining the grain size of the crystalline oxide semiconductor constituting the active layer 102, the stability of the device can be improved more.
In addition, when the crystal grain size of the crystalline oxide semiconductor is excessively large, more than 1000 nm, a large grain boundary may be formed. If the active layer 102 is applied to a large-sized display panel, the uniformity is poor and the display is not uniform. Therefore, in the embodiment of the present application, the grain size of the crystalline oxide semiconductor is defined to be 10 nm to 1000 nm to avoid the above phenomenon.
Wherein the dopant particles comprise a combination of one or more of hydrogen, helium, boron, aluminum, nitrogen, fluorine, phosphorus, argon, and sulfur.
It should be noted that, in the prior art, the conductor region of the active layer is formed by using a conventional conductor process, which may cause the end channel effect of the array substrate. In the embodiment of the present application, the conductive region 102b of the active layer 102 is ion-doped by using the doping particles, so that the conductive region 102b of the active layer 102 forms an N + conductive region, which is convenient for connecting with the source/drain layer 103. By adopting the operation, the crystalline oxide semiconductor thin film transistor device with the specific structure is formed, the channel length of the thin film transistor device can be further shortened, and the mobility and the current driving capability of the device can be improved.
The thickness of the active layer 102 is 100 to 1000 angstroms. Specifically, the thickness of the active layer 102 is 100 angstroms, 200 angstroms, 300 angstroms, 450 angstroms, 600 angstroms, 800 angstroms, or 1000 angstroms. The specific thickness of the active layer 102 is determined by the specific requirements of the array substrate 10.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of an array substrate according to the present application. As shown in fig. 2, the array substrate 10 provided in fig. 2 is different from the array substrate 10 provided in fig. 1 in that: the array substrate 10 further includes an insulating buffer layer 104 and an interlayer insulating layer 105. An insulating buffer layer 104 is located between the substrate 101 and the active layer 102. An interlayer insulating layer 105 is provided on a face of the active layer 102 away from the substrate 101, and a through hole 105a is provided on the interlayer insulating layer 105. The source-drain layer 103 is connected to the active layer 102 through a via hole 105a.
The material of the insulating buffer layer 104 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
The insulating buffer layer 104 has a thickness of 1000 angstroms to 5000 angstroms. Specifically, the insulating buffer layer 104 has a thickness of 1000 angstroms, 1500 angstroms, 2000 angstroms, 2700 angstroms, 3400 angstroms, 4200 angstroms, or 5000 angstroms. The specific thickness of the insulating buffer layer 104 is determined by the specific requirements of the array substrate 10.
It should be noted that a metal film layer for connecting with the outside may be disposed between the active layer 102 and the substrate 101, so as to receive an external signal. Therefore, disposing the insulating buffer layer 104 between the active layer 102 and the substrate 101 may function to prevent signals received by the metal layer from affecting the active layer 102.
The material of the interlayer insulating layer 105 includes silicon oxide. The interlayer insulating layer 105 has a thickness of 3000 to 10000 angstroms. Specifically, the interlayer insulating layer 105 has a thickness of 3000 angstroms, 3500 angstroms, 4000 angstroms, 5000 angstroms, 6000 angstroms, 8000 angstroms, or 10000 angstroms. The specific thickness of the interlayer insulating layer 105 is determined by the specific requirements of the array substrate 10.
It should be noted that the source/drain electrode layer 103 is connected to the active layer 102, so that the active layer 102 is used as an intermediate transfer film layer, so that a signal received by a source in the source/drain electrode layer 103 is transferred out through a drain in the source/drain electrode layer 103. Therefore, the interlayer insulating layer 105 needs to be provided around the source-drain layer 103. The source drain layer 103 is prevented from being affected by other surrounding layers when transmitting signals.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of an array substrate according to the present application. As shown in fig. 3, the array substrate 10 provided in fig. 3 is different from the array substrate 10 provided in fig. 2 in that: the insulating buffer layer 104 includes a first insulating buffer sub-layer 1041 and a second insulating buffer sub-layer 1042 stacked in sequence. The material of the first insulating buffer layer 1041 is different from the material of the second insulating buffer layer 1042
Note that one side of the insulating buffer layer 104 is the active layer 102, and the other side of the insulating buffer layer 104 is the substrate 101. Whereas the substrate 101 and the active layer 102 are of different materials and have different surface properties. Therefore, the first insulating buffer sublayer 1041 and the second insulating buffer sublayer 1042 which are sequentially stacked are arranged, and the material of the first insulating buffer sublayer 1041 is different from the material of the second insulating buffer sublayer 1042, so that the substrate 101 and the active layer 102 can be better attached to each other, the phenomenon that the films are separated from each other is avoided, and in addition, the effect of avoiding the influence of external signals on the active layer 102 can be better achieved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a fourth embodiment of an array substrate according to the present application. As shown in fig. 4, the array substrate 10 provided in fig. 4 is different from the array substrate 10 provided in fig. 3 in that: the array substrate 10 further includes a first gate layer 106 and a first gate insulating layer 107. A first gate insulating layer 107 is located on a side of the active layer 102 remote from the substrate 101. The first gate layer 106 is located on a side of the first gate insulating layer 107 away from the substrate 101.
The material of the first gate layer 106 is a transition metal material or a metal layer material. Specifically, the material of the first gate layer 106 includes molybdenum, titanium, tungsten, chromium, nickel, copper, or aluminum. The material of the first gate layer 106 may also be an alloy material of the above metals. The material of the first gate layer 106 may be an alloy such as a molybdenum-titanium alloy and a chromium-nickel alloy.
The thickness of the first gate layer 106 is 3000 angstroms to 6500 angstroms. Specifically, the thickness of the first gate layer 106 is 3000 angstroms, 3500 angstroms, 4000 angstroms, 4600 angstroms, 5200 angstroms, 5800 angstroms, or 6500 angstroms. The specific thickness of the first gate layer 106 is determined by the specific requirements of the array substrate 10.
The material of the first gate insulating layer 107 is silicon oxide. The thickness of the first gate insulating layer 107 is 1000 angstroms to 3000 angstroms. Specifically, the thickness of the first gate insulating layer 107 is 1000 angstroms, 1200 angstroms, 1500 angstroms, 1800 angstroms, 2100 angstroms, 2500 angstroms, or 3000 angstroms. The specific thickness of the first gate insulating layer 107 is determined by the specific requirements of the array substrate 10.
In the embodiment of the present invention, the array substrate 10 has a top gate structure.
A passivation layer may be further formed on the source/drain layer 103 to protect the source/drain layer 103.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a fifth implementation manner of the array substrate according to the embodiment of the present disclosure. As shown in fig. 5, the array substrate 10 provided in fig. 5 is different from the array substrate 10 provided in fig. 4 in that: the first gate layer 106 includes a first gate sublayer 1061, a second gate sublayer 1062, and a third gate sublayer 1063 stacked in this order. And the material of the first gate sublayer 1061 is the same as that of the third gate sublayer 1063.
The material of the first gate sub-layer 1061 includes molybdenum, titanium, tungsten, chromium, nickel, or an alloy material of the above metals. Specifically, the material of the first gate sub-layer 1061 may be an alloy such as molybdenum-titanium alloy and chromium-nickel alloy. The material of the second gate sub-layer 1062 is copper or aluminum. The material of the third gate sub-layer 1063 includes molybdenum, titanium, tungsten, chromium, nickel, or an alloy material thereof. Specifically, the material of the third gate sub-layer 1063 may be an alloy such as a molybdenum-titanium alloy and a chromium-nickel alloy.
The thickness of the first gate sub-layer 1061 is 50 to 500 angstroms. Specifically, the thickness of the first gate sub-layer 1061 is 50 angstroms, 100 angstroms, 150 angstroms, 220 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms. The specific thickness of the first gate sub-layer 1061 is determined by the specific requirements of the array substrate 10.
The thickness of the second gate sub-layer 1062 is 2000 angstroms to 5000 angstroms. Specifically, the thickness of the first gate insulating layer 107 is 2000 angstroms, 2400 angstroms, 2800 angstroms, 3300 angstroms, 3800 angstroms, 4400 angstroms, or 5000 angstroms. The specific thickness of the second gate sub-layer 1062 is determined by the specific requirements of the array substrate 10.
The thickness of the third gate sub-layer 1063 is 50 to 1000 angstroms. Specifically, the thickness of the third gate sub-layer 1063 is 50 angstroms, 100 angstroms, 200 angstroms, 350 angstroms, 500 angstroms, 700 angstroms, or 1000 angstroms. The specific thickness of the third gate sub-layer 1063 is determined by the specific requirements of the array substrate 10.
It should be noted that the gate layer 106 is formed by three layers stacked in sequence, where the second gate sublayer 1062 in the middle is made of a metal layer material, and the first gate sublayer 1061 and the third gate sublayer 1063 on two sides are made of a transition metal material. The stability of the thin film transistor device can be improved better.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a sixth implementation manner of an array substrate according to the embodiment of the present disclosure. As shown in fig. 6, the array substrate 10 provided in fig. 6 is different from the array substrate provided in fig. 3 in that: the array substrate 10 further includes a second gate electrode layer 108 and a second gate insulating layer 109. The second gate layer 108 and the second gate insulating layer 109 are located between the substrate 101 and the active layer 102. And the second gate layer 108 is located on the first face 101 a. A second gate insulating layer 109 is located on a side of the second gate layer 108 remote from the substrate 101.
The material of the second gate layer 108 is a transition metal material or a metal layer material. Specifically, the material of the second gate layer 108 includes molybdenum, titanium, tungsten, chromium, nickel, copper, or aluminum. The material of the second gate layer 108 may also be an alloy material of the above metals. The material of the second gate layer 108 may be an alloy such as a molybdenum-titanium alloy and a chromium-nickel alloy.
The thickness of the second gate layer 108 is 3000 angstroms to 6500 angstroms. Specifically, the thickness of the second gate layer 108 is 3000 angstroms, 3500 angstroms, 4000 angstroms, 4600 angstroms, 5200 angstroms, 5800 angstroms, or 6500 angstroms. The specific thickness of the second gate layer 108 is determined by the specific requirements of the array substrate 10.
The second gate insulating layer 109 is silicon oxide. The thickness of the second gate insulating layer 109 is 1000 angstroms to 3000 angstroms. Specifically, the thickness of the second gate insulating layer 109 is 1000 angstroms, 1200 angstroms, 1500 angstroms, 1800 angstroms, 2100 angstroms, 2500 angstroms, or 3000 angstroms. The specific thickness of the second gate insulating layer 109 is determined by the specific requirements of the array substrate 10.
It should be noted that, in the embodiment of the present application, the array substrate 10 adopts a bottom gate structure.
Wherein the channel region 102a of the active layer 102 is provided with a protective layer. It should be noted that, since the conductive region 102b of the active layer 102 needs to be subjected to ion doping treatment, a protective layer needs to be provided in the channel region 102a of the active layer 102 to perform ion doping treatment only on the conductive region 102b of the active layer 102, so as to avoid ion doping in the channel region 102a of the active layer 102. The material of the protective layer may be photoresist.
In addition, an orthogonal projection of the channel region 102a of the active layer 102 on the substrate 101 is located in an orthogonal projection of the second gate layer 108 on the substrate 101. Note that the second gate layer 108 is used for receiving an external signal for controlling the thin film transistor. Therefore, it is necessary to have an orthogonal projection of the channel region 102a of the active layer 102 on the substrate 101 in an orthogonal projection of the second gate layer 108 on the substrate 101.
The array substrate provided by the embodiment of the application comprises a substrate, an active layer and a source drain layer; wherein the active layer is formed using a crystalline oxide semiconductor material. In addition, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and the conductive regions contain doped particles, so that a crystalline oxide semiconductor thin film transistor device with a specific structure is formed, the mobility of the array substrate can be greatly improved, the driving characteristic can be improved, and the stability of the array substrate can be improved. Therefore, by adopting the array substrate provided by the embodiment of the application, the stability of the device can be ensured on the basis of improving the mobility of the device.
The embodiment of the application also provides a manufacturing method of the array substrate. Referring to fig. 7, fig. 7 is a schematic flowchart illustrating a manufacturing method of a display panel according to an embodiment of the present disclosure. As shown in fig. 7, a method for manufacturing a display panel provided in the embodiment of the present application includes the following steps:
Referring to fig. 8, fig. 8 is a schematic view of a display panel structure corresponding to step 201 of a method for manufacturing a display panel according to an embodiment of the present disclosure. Among them, the substrate generally adopts a glass substrate. Therefore, before other layers are formed on the substrate, cleaning is required to be performed in order to coat the substrate with other layers. In addition, since the active layer plays a role of conducting signals, in order to avoid the influence of external signals on the active layer, an insulating buffer layer is usually formed on the substrate first, and then the active layer is formed.
Referring to fig. 9, fig. 9 is a sub-flow diagram illustrating a manufacturing method of a display panel according to an embodiment of the present disclosure. As shown in fig. 9, step 202 of applying for a manufacturing method of a display panel according to an embodiment includes the following steps:
Referring to fig. 10, fig. 10 is a schematic view of a display panel structure corresponding to step 2021 of a method for manufacturing a display panel according to an embodiment of the present disclosure. Wherein the amorphous oxide semiconductor layer is coated on the whole surface. The amorphous oxide semiconductor layer contains elements such as indium, zinc, calcium, and oxygen.
Wherein the temperature of the heat treatment process is between 120 and 460 ℃. Specifically, the temperature of the heat treatment process is 120 degrees, 160 degrees, 200 degrees, 260 degrees, 320 degrees, 390 degrees, or 460 degrees. The processing environment of the heat treatment process can adopt an oxygen environment, a nitrogen environment, an air environment, a vacuum environment or the like. The treatment time of the heat treatment process is 15 minutes to 120 minutes. Specifically, the treatment time of the heat treatment process is 15 minutes, 25 minutes, 35 minutes, 50 minutes, 70 minutes, 90 minutes, or 120 minutes.
In addition, when the amorphous oxide semiconductor layer is subjected to heat treatment, the crystal grain size of the crystalline oxide semiconductor layer can be formed to be between 10 nm and 1000 nm by using the above operating parameters. Thereby improving the stability of the array substrate.
In addition, the crystalline oxide semiconductor layer can be formed on the substrate in a direct deposition mode, so that the difficulty of the process is reduced, and the cost is reduced. Step 2023, etching the crystalline oxide semiconductor layer to form an active layer.
Referring to fig. 11, fig. 11 is a schematic view of a display panel structure corresponding to step 2023 of a method for manufacturing a display panel according to an embodiment of the present disclosure. Wherein the crystalline oxide semiconductor layer is etched using a photomask to form a specific crystalline oxide semiconductor layer pattern to form an active layer.
Referring to fig. 12, fig. 12 is a schematic view of a display panel structure corresponding to step 2024 of a method for manufacturing a display panel according to an embodiment of the present disclosure. The doping particles can be implanted into both ends of the active layer by thermal atmosphere particle diffusion, plasma treatment doping, high-energy particle implantation, and other processes.
And 203, forming a source drain layer on the active layer, wherein the source drain layer is connected with the conductive region.
Referring to fig. 13, fig. 13 is a schematic view of a display panel structure corresponding to step 203 of a method for manufacturing a display panel according to an embodiment of the present disclosure. And a passivation protective layer can be formed on one surface of the source drain layer, which is far away from the substrate, and is used for protecting the source drain layer.
The manufacturing method of the array substrate provided by the embodiment of the application comprises a substrate, an active layer and a source drain layer; wherein the active layer is formed using a crystalline oxide semiconductor material. In addition, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and the conductive regions contain doped particles, so that a crystalline oxide semiconductor thin film transistor device with a specific structure is formed, the mobility of the array substrate can be greatly improved, the driving characteristic can be improved, and the stability of the array substrate can be improved. Therefore, the array substrate provided by the embodiment of the application can ensure the stability of the device on the basis of improving the mobility of the device.
The embodiment of the application also provides a display panel. The display panel provided by the embodiment of the application comprises an array substrate 10 and an active light-emitting display device layer. An active light emitting display device layer is disposed over the array substrate 10. The array substrate 10 has been described in detail in the above embodiments, and therefore, in the embodiments of the present application, the array substrate 10 is not described in detail.
In the embodiment of the application, the type of the display panel is not limited, the display panel can be a top light-emitting display device, a bottom light-emitting display device and a double-sided light-emitting display device according to a light-emitting direction, and the display panel can be an OLED, a Mini-LED, a Micro-LED, a QLED and the like according to different active light-emitting display devices.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate, the manufacturing method of the array substrate, and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied in the present application to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate comprising a first side and a second side disposed opposite one another;
the active layer is arranged on the first surface, the material of the active layer is a crystalline oxide semiconductor, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and doped particles are arranged in the conductive regions;
and the source drain layer is arranged on one surface of the active layer, which is far away from the substrate, and is connected with the conductive region.
2. The array substrate of claim 1, wherein the crystalline oxide semiconductor has a grain size of 10 nm to 1000 nm.
3. The array substrate of claim 1, wherein the doping particles comprise a combination of one or more of hydrogen, helium, boron, aluminum, nitrogen, fluorine, phosphorus, argon, and sulfur.
4. The array substrate of claim 1, further comprising an insulating buffer layer and an interlayer insulating layer, wherein the insulating buffer layer is located between the substrate and the active layer, the interlayer insulating layer is disposed on a surface of the active layer away from the substrate, a through hole is disposed on the interlayer insulating layer, and the source/drain layer is connected to the active layer through the through hole.
5. The array substrate of claim 1, further comprising a first gate layer and a first gate insulating layer, wherein the first gate insulating layer is on a side of the active layer away from the substrate, and wherein the first gate layer is on a side of the first gate insulating layer away from the substrate.
6. The array substrate of claim 5, wherein the first gate layer comprises a first gate sub-layer, a second gate sub-layer and a third gate sub-layer, which are sequentially stacked, and the material of the first gate sub-layer is the same as that of the third gate sub-layer.
7. The array substrate of claim 1, further comprising a second gate layer and a second gate insulating layer between the substrate and the active layer, wherein the second gate layer is on the first side, and wherein the second gate insulating layer is on a side of the second gate layer away from the substrate.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming an active layer on the substrate, wherein the active layer is made of a crystalline oxide semiconductor, the active layer comprises a channel region and conductive regions positioned on two sides of the channel region, and doped particles are arranged in the conductive regions;
and forming a source drain layer on the active layer, wherein the source drain layer is connected with the conductive region.
9. The method for manufacturing the array substrate according to claim 8, wherein the step of forming the active layer on the substrate comprises:
forming an amorphous oxide semiconductor layer over the substrate;
performing heat treatment on the amorphous oxide semiconductor layer to form a crystalline oxide semiconductor layer;
performing an etching process on the crystalline oxide semiconductor layer to form an active layer;
and injecting doping particles into two ends of the active layer to form a channel region and conductive regions positioned on two sides of the channel region.
10. The method for manufacturing the array substrate according to claim 8, wherein the step of forming the active layer on the substrate comprises:
directly depositing a crystalline oxide semiconductor layer on the substrate;
performing an etching process on the crystalline oxide semiconductor layer to form an active layer;
and injecting doping particles into two ends of the active layer to form a channel region and conductive regions positioned on two sides of the channel region.
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