CN115274694A - Display panel, manufacturing method and display device - Google Patents

Display panel, manufacturing method and display device Download PDF

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Publication number
CN115274694A
CN115274694A CN202210806065.XA CN202210806065A CN115274694A CN 115274694 A CN115274694 A CN 115274694A CN 202210806065 A CN202210806065 A CN 202210806065A CN 115274694 A CN115274694 A CN 115274694A
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CN
China
Prior art keywords
layer
substrate
display panel
light
shading
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CN202210806065.XA
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Chinese (zh)
Inventor
李柱辉
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202210806065.XA priority Critical patent/CN115274694A/en
Publication of CN115274694A publication Critical patent/CN115274694A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Abstract

The application discloses a display panel, a manufacturing method and a display device. The display panel includes: the substrate is provided with at least two grooves; the at least two power lines are arranged on the substrate at intervals, and each power line comprises a first part arranged in the corresponding groove and a second part arranged on the corresponding first part; the functional structure layer is arranged on the substrate. This application increases and sets up the first part, has increased the thickness of power cord in other words, reduces resistance to reduce the total resistance of panel power cord and improve the IR Drop problem, and then reach and improve the inhomogeneous purpose of panel luminance.

Description

Display panel, manufacturing method and display device
Technical Field
The application relates to the technical field of display, in particular to a display panel, a manufacturing method and a display device.
Background
In recent years, the display industry has been rapidly developed, and particularly, the display industry in China has changed from the top to the bottom. The Display industry is becoming more and more competitive, and the refresh cycle is being shortened, especially for LCD (Liquid Crystal Display) and OLED (Organic electronic Display). With the maturation of OLED process and materials and the improvement of yield, LCD gradually loses its market advantage in small size, especially in mobile phone market, OLED has gradually replaced LCD. Many new display technologies have emerged in recent years, such as QLED displays, E-ink, flexible LCDs, PE displays, mini LEDs, micro LEDs, etc. These new technologies also have some problems such as cost, life, reliability, etc., and thus do not have mass productivity like LCDs and OLEDs. Micro LEDs have the advantages of wide color gamut, high contrast, fast response speed, high resolution, long service life, etc., and are widely popularized by many enterprises, and are considered as the next generation of the most promising novel display technology.
Micro LEDs are currently available in many demos, but still suffer from a number of problems. Such as non-uniform brightness, low reliability, low transfer yield, poor TFT uniformity, cross color, color mixing, poor contrast, etc. The IR Drop caused by RC loading can cause the brightness of the Micro LED panel to be uneven.
Disclosure of Invention
The embodiment of the application provides a display panel, a manufacturing method and a display device, wherein a first part is additionally arranged, namely the thickness of a power line is increased, and the resistance is reduced, so that the total resistance of the power line of the panel is reduced, the IR Drop problem is improved, and the purpose of improving the uneven brightness of the panel is achieved.
In a first aspect, an embodiment of the present application provides a display panel, including:
the substrate is provided with at least two grooves;
the at least two power lines are arranged on the substrate at intervals, and each power line comprises a first part arranged in the corresponding groove and a second part arranged on the corresponding first part;
and the functional structure layer is arranged on the substrate.
In some embodiments, the display region of the display panel includes a light emitting region and a light blocking region, the substrate extends from the light emitting region to the light blocking region, and the at least two power lines are located in the light blocking region.
In some embodiments, the functional structural layer comprises:
the thin film transistor structure layer is arranged on the substrate and is positioned in the shading area;
and the light-emitting device layer is arranged on the substrate and is positioned in the light-emitting area.
In some embodiments, the light emitting device layer comprises:
the buffer layer is arranged on the substrate;
the interlayer dielectric layer is arranged on the buffer layer;
the metal layer is arranged on the interlayer dielectric layer;
the passivation layer covers the interlayer dielectric layer and the metal layer;
the passivation layer is provided with a first through hole, and the first through hole penetrates through the passivation layer to expose a part of the metal layer;
and the electrode layer is arranged on the flat layer and is deposited in the first through hole to be in contact with the metal layer.
In some embodiments, the electrode layer comprises:
the metal electrode layer is arranged on the flat layer and is deposited in the first through hole to be in contact with the metal layer;
and the ITO electrode layer covers the metal electrode layer.
In some embodiments, the thin film transistor structure layer includes:
a light shielding layer disposed on the substrate;
the buffer layer extends from the light emitting area to the shading area and covers the shading layer;
an active layer disposed on the buffer layer;
a gate insulating layer disposed on the active layer;
a gate electrode layer disposed on the gate insulating layer;
the interlayer dielectric layer extends from the light emitting area to the shading area, covers the buffer layer, the active layer, the grid insulating layer and the grid layer, is provided with a second through hole and a third through hole, exposes a part of the active layer, and penetrates through the buffer layer to expose a part of the shading layer;
the metal layer extends from the light emitting area to the shading area, is deposited in the second via hole and is in contact with the active layer, and is deposited in the third via hole and is in contact with the shading layer;
the passivation layer extends from the light emitting area to the light shielding area;
the flat layer extends from the light emitting area to the light shielding area;
the shading passivation layer is arranged on the flat layer and is positioned in the shading area;
and the black matrix layer is arranged on the shading passivation layer and is positioned in the shading area.
In some embodiments, the thickness of the first portion is greater than that of the second portion, and the thickness direction is a stacking direction of the substrate to the functional structure layer.
In some embodiments, the first portion is provided as copper.
In a second aspect, the present application provides a method for manufacturing a display panel, including:
providing a substrate, and etching at least two grooves on the substrate;
depositing a copper film on one side of the substrate provided with the groove until the groove is filled;
grinding one side of the substrate on which the copper film is deposited until the copper film in the groove is reserved to obtain a first part;
depositing a metal layer on one side of the substrate, which is provided with the first part, and etching to obtain a second part, wherein the second part is arranged opposite to the first part;
and preparing a functional structure layer on one side of the substrate provided with the first part.
In a third aspect, the present application provides a display device comprising the display panel of any one of the above.
According to the display panel, the manufacturing method and the display device, the groove is arranged on the substrate to deposit one part of the power line, and compared with the situation that the power line is only deposited on the surface of the substrate, namely the power line only comprises the second part, the first part is additionally arranged in the embodiment, so that the thickness of the power line is increased, the resistance is reduced, the total resistance of the power line of the panel is reduced, the IR Drop problem is improved, and the aim of improving the uneven brightness of the panel is fulfilled.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present disclosure;
fig. 2 is a flowchart illustrating a process for manufacturing a display panel according to an embodiment of the present disclosure.
Reference numbers:
1. a substrate; 11. a trench; 2. a power line; 21. a first portion; 22. a second portion; 3. a functional structure layer; 31. a light emitting device layer; 311. a buffer layer; 312. an interlayer dielectric layer; 313. a metal layer; 314. a passivation layer; 315. a planarization layer; 316. an electrode layer; 3161. a metal electrode layer; 3162. an ITO electrode layer; 32. a thin film transistor structure layer; 321. a light-shielding layer; 322. an active layer; 323. a gate insulating layer; 324. a gate layer; 325. a light-shielding passivation layer; 326. and a black matrix layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation of the first and second features not being in direct contact, but being in contact with another feature between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. "beneath," "under" and "beneath" a first feature includes the first feature being directly beneath and obliquely beneath the second feature, or simply indicating that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. To simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 1 and fig. 2, a display panel according to an embodiment of the present disclosure includes a substrate 1, a power line 2, and a functional structure layer 3, where the power line 2 and the functional structure layer 3 are disposed on the substrate 1. The substrate 1 is provided with a groove 11, the power lines 2 at least comprise two power lines 2 of a VDD power line and a VSS power line, different power lines 2 are arranged at intervals, parts of the power lines 2 are deposited in the groove 11, and the power lines 2 are not communicated with each other, so that the groove 11 formed in the substrate 1 corresponds to the power lines 2 one to one.
Furthermore, each power supply line 2 comprises a first portion 21 and a second portion 22, the first portion 21 being deposited in the corresponding trench 11, the second portion 22 being deposited on the first portion 21, i.e. the first portion 21 communicating with the second portion 22, the first portion 21 being provided in copper.
The electrical parameters such as the current resistance of the display panel are determined based on the display requirements (e.g., panel definition, uniformity, etc.) of the display panel, and the minimum area of the contact surface between the first portion 21 and the second portion 22 is determined. On the basis that the size of the contact surface between the first portion 21 and the second portion 22 satisfies the required minimum area, the bottom surface of the second portion 22 may be larger than the top surface of the first portion 21, or the bottom surface of the second portion 22 may be smaller than the top surface of the first portion 21, which is not specifically limited in the present embodiment, where the bottom surface of the second portion 22 contacts the top surface of the first portion 21. For example, the width of the second portion 22 may be slightly less than the line width of the VDD, VSS Power lines in the first portion 21Pixel by 3-5um.
In the embodiment, the groove 11 is formed in the substrate 1 to deposit a part of the power line 2, and compared with the case that the power line 2 is only deposited on the surface of the substrate 1, that is, the power line 2 only includes the second portion 22, the first portion 21 is additionally formed in the embodiment, which is equivalent to increasing the thickness of the power line 2 and reducing the resistance, so that the total resistance of the panel power line 2 is reduced, the IR Drop problem is improved, and the purpose of improving the uneven brightness of the panel is achieved.
In one embodiment, the display panel includes a display area and a non-display area surrounding the display area, in which case the area includes a light-emitting area and a light-shielding area, the light-emitting area is provided with the LED beads correspondingly, and therefore all the power lines 2 are provided in the light-emitting area. The shading area is a Black Matrix (BM) area and is used for shielding the routing of components such as thin film transistors. In addition, all components of the light-shielding region and the light-emitting region of the substrate 1 are disposed on the substrate 1, so that the substrate 1 extends from the light-emitting region to the light-shielding region, wherein the substrate 1 may be a substrate 1 made of a common transparent material such as glass, quartz, sapphire, resin, etc., and the embodiment is not particularly limited.
In one embodiment, the functional structure layer 3 includes a thin film transistor structure layer 32 and a light emitting device layer 31, and the thin film transistor structure layer 32 and the light emitting device layer 31 are both disposed on the substrate 1 and are disposed on the same side of the substrate 1, except that the thin film transistor structure layer 32 is located in a light shielding region, mainly including a thin film transistor in a pixel driving circuit. The light emitting device layer 31 is located in the light emitting area and connected with the LED lamp beads.
In one embodiment, the light emitting device layer 31 includes a buffer layer 311, an interlayer dielectric layer 312, a metal layer 313, a passivation layer 314, a planarization layer 315, and an electrode layer 316, which are sequentially stacked, and all components included in the light emitting device layer 31 are located in a light emitting region.
The Buffer layer 311 (Buffer) is disposed on one side of the substrate 1, the interlayer dielectric layer 312 (ILD) is disposed on one side of the Buffer layer 311 away from the substrate 1, and the metal layer 313 is disposed on one side of the interlayer dielectric layer 312 away from the substrate 1. The power source is a part of the metal layer 313, and the power line 2 of the light-emitting area is obtained by depositing a layer of metal on the interlayer dielectric layer 312 and performing reverse etching when the display panel is prepared. Therefore, the metal layer 313 occupies only a partial region of the interlayer dielectric layer 312, and when a passivation layer 314 (PV) is deposited on the side of the interlayer dielectric layer 312 away from the substrate 1, the passivation layer 314 covers both the interlayer dielectric layer 312 and the metal layer 313.
A planar layer 315 (PLN) is disposed on the passivation layer 314, the electrode layer 316 is disposed on the planar layer 315, and the electrode layer 316 needs to be electrically connected to the metal layer 313, so that the planar layer 315 is provided with a first via hole penetrating through the passivation layer 314 to expose a portion of the metal layer 313 that needs to be electrically connected, and then the electrode layer 316 is deposited in the first via hole to achieve contact between the electrode layer 316 and the metal layer 313.
In one embodiment, the electrode layer 316 includes a metal electrode layer 3161 and an ITO (Indium Tin oxide) electrode layer 316, the metal electrode layer 3161 is deposited in the first via hole and contacts the metal layer 313, the ITO electrode layer 3162 covers the metal electrode layer 3161, and finally the ITO electrode layer 3162 is electrically connected to an electrode of the LED lamp bead. The ITO electrode layer 3162 can enhance conductivity and transparency.
In one embodiment, the thin film transistor structure layer 32 includes a light-shielding layer 321, a buffer layer 311, an active layer 322, a gate insulating layer 323, a gate layer 324, an interlayer dielectric layer 312, a metal layer 313, a passivation layer 314, a planarization layer 315, a light-shielding passivation layer 325, and a black matrix layer 326.
The light shield layer 321 (LS) is formed on the substrate 1 by exposing and etching, and the light shield layer 321 occupies only a partial region of the substrate 1, so that the buffer layer 311 is deposited on the substrate 1 and the light shield layer 321, and the buffer layer 311 covers both the substrate 1 and the light shield layer 321. It should be noted that the buffer layer 311 extends from the light emitting region to the light shielding region, that is, the buffer layer 311 in different regions is prepared by the same process and integrally formed.
The active layer 322 is disposed on the buffer layer 311, and the active layer 322 occupies only a partial region of the buffer layer 311. A Gate insulating layer 323 (GI) is disposed on the active layer 322, and the coating range of the Gate insulating layer 323 does not exceed the active layer 322, i.e., the Gate insulating layer 323 is not disposed on the buffer layer 311. The Gate electrode layer 324 (Gate Metal, GE) is disposed on the Gate insulating layer 323, and similarly, the Gate electrode layer 324 is not coated over the Gate insulating layer 323, i.e., the Gate insulating layer 323 is not formed on the buffer layer 311. The light-shielding layer 321 is provided to face the active layer 322 and shields the active layer 322. In addition, the active layer 322 includes a channel region (not shown) and a conductive region (not shown) disposed on both sides of the channel region, the channel region is disposed opposite to the gate layer 324, the light-shielding layer 321 is disposed opposite to the channel region, and the range of the light-shielding layer 321 is larger than that of the channel region to shield the channel region from light.
Therefore, when an Inter-layer Dielectric (ILD) layer 312 is deposited on the gate layer 324, the ILD layer 312 covers the buffer layer 311, the active layer 322, the gate insulating layer 323, and the gate layer 324. It should be noted that the interlayer dielectric layer 312 extends from the light emitting region to the light shielding region, that is, the interlayer dielectric layers 312 in different regions are prepared by the same process and integrally formed. In order to enable the gate electrode to be electrically connected to other electronic components and facilitate the light shielding layer 321 to be in contact with other electronic components for subsequent driving, the interlayer dielectric layer is provided with a second via hole and a third via hole, the second via hole exposes a portion of the active layer 322, and the third via hole and the second via hole penetrate through the buffer layer and expose a portion of the light shielding layer 321.
A metal layer 313 is disposed on the interlayer dielectric layer 312, the metal layer 313 includes Source and Drain electrodes (SD), the Source and Drain electrodes in the metal layer 313 are deposited in the second via holes and contact with the active layer 322, but it should be noted that the Source and Drain electrodes are deposited in different second via holes respectively and are connected to the conductor regions on both sides of the channel region of the active layer 322. In addition, the source electrode in the metal layer 313 is also deposited in the third via hole to contact the light shielding layer 321. In addition, the metal layer 313 extends from the light emitting region to the light shielding region, that is, the metal layers 313 in different regions are prepared by the same process and are integrally formed, and the metal layer 313 includes a source/drain of the light shielding region and the power line 2 of the light emitting region.
Similarly, the passivation layer 314 and the planarization layer 315 also extend from the light emitting region to the light shielding region, that is, the passivation layer 314 and the planarization layer 315 in different regions are separately prepared by the same process and integrally formed. A passivation layer 314 is disposed overlying the interlevel dielectric layer 312 and the metal layer 313, and a planarization layer 315 is disposed on the passivation layer 314.
In addition, a light-shielding passivation layer 325 is disposed on the planarization layer 315, and a black matrix layer 326 is disposed on the light-shielding passivation layer 325. The light-shielding passivation layer 325 and the black matrix layer 326 are both located only in the light-shielding region.
In one embodiment, the thickness of the first portion 21 of the power line 2 is greater than the thickness of the second portion 22, the thickness direction is the stacking direction of the substrate 1 to the functional structure layer 3, for example, the depth of the trench 11 is set to 5-100um. The first part 21 with relative thickness is additionally arranged, and the resistance is reduced, so that the total resistance of the Power lines of the panel is reduced, the problem of IR Drop is solved, and the aim of improving the uneven brightness of the panel is fulfilled.
In the embodiment, the IR Drop problem of the panel can be effectively improved by only adding the conventional process to increase the first portion 21 without reducing the PPI of the Micro LED panel, thereby improving the display quality of the Micro LED display panel.
Referring to fig. 1 to fig. 2, an embodiment of the present application provides a method for manufacturing a display panel, including:
providing a substrate 1, and etching at least two grooves 11 on the substrate 1;
depositing a copper film on one side of the substrate 1 provided with the groove 11 until the groove 11 is filled;
grinding one side of the substrate 1 on which the copper film is deposited until the copper film in the groove 11 is reserved to obtain a first part 21;
depositing a metal layer 313 on one side of the substrate 1 provided with the first part 21, and etching to obtain a second part 22, wherein the second part 22 is arranged opposite to the first part 21;
the functional structure layer 3 is prepared on the side of the substrate 1 where the first portion 21 is provided.
Specifically, grooves 11 of VDD and VSS Power auxiliary lines (i.e., first portions 21 of the Power supply lines 2) are engraved on the substrate 1 by laser, and the positions of the grooves 11 correspond to the positions of VDD and VSS Power lines (i.e., second portions 22 of the Power supply lines 2) in Pixel one by one; the depth of the groove 11 is 5-100um, and the width is slightly smaller than the line width of VDD and VSS Power lines in Pixel by 3-5um. Depositing a copper film by electroplating until the groove 11 is filled, grinding the film surface, grinding all the metal on the surface of the substrate 1, only leaving the metal in the groove 11 to form VDD and VSS Power auxiliary lines pattern (i.e. the first part 21 of the Power line 2), and then performing normal backboard process and back-end process to prepare the functional structure layer 3. The functional structure layer 3 is sequentially prepared according to the structures described in the above embodiments, and no further description is given in this embodiment.
In the embodiment, the IR Drop problem of the panel can be effectively improved by only adding the conventional process to increase the first portion 21 without reducing the PPI of the Micro LED panel, thereby improving the display quality of the Micro LED display panel.
An embodiment of the present application provides a display device, including the display panel according to any of the above embodiments.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The display panel, the manufacturing method and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present invention, and the description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A display panel, comprising:
the substrate is provided with at least two grooves;
the at least two power lines are arranged on the substrate at intervals, and each power line comprises a first part arranged in the corresponding groove and a second part arranged on the corresponding first part;
and the functional structure layer is arranged on the substrate.
2. The display panel according to claim 1, wherein the display region of the display panel includes a light-emitting region and a light-shielding region, the substrate extends from the light-emitting region to the light-shielding region, and the at least two power lines are located in the light-shielding region.
3. The display panel of claim 2, wherein the functional structure layer comprises:
the thin film transistor structure layer is arranged on the substrate and is positioned in the shading area;
and the light-emitting device layer is arranged on the substrate and is positioned in the light-emitting area.
4. The display panel according to claim 3, wherein the light emitting device layer comprises:
the buffer layer is arranged on the substrate;
the interlayer dielectric layer is arranged on the buffer layer;
the metal layer is arranged on the interlayer dielectric layer;
the passivation layer covers the interlayer dielectric layer and the metal layer;
the passivation layer is provided with a first through hole, and the first through hole penetrates through the passivation layer to expose a part of the metal layer;
and the electrode layer is arranged on the flat layer and is deposited in the first through hole to be in contact with the metal layer.
5. The display panel according to claim 4, wherein the electrode layer comprises:
the metal electrode layer is arranged on the flat layer and is deposited in the first through hole to be in contact with the metal layer;
and the ITO electrode layer covers the metal electrode layer.
6. The display panel of claim 4, wherein the thin film transistor structure layer comprises:
a light shielding layer disposed on the substrate;
the buffer layer extends from the light emitting area to the shading area and covers the shading layer;
an active layer disposed on the buffer layer;
a gate insulating layer disposed on the active layer;
a gate electrode layer disposed on the gate insulating layer;
the interlayer dielectric layer extends from the light emitting area to the shading area, covers the buffer layer, the active layer, the grid insulating layer and the grid layer, is provided with a second through hole and a third through hole, the second through hole exposes one part of the active layer, and the third through hole penetrates through the buffer layer to expose one part of the shading layer;
the metal layer extends from the light emitting area to the shading area, is deposited in the second via hole and is in contact with the active layer, and is deposited in the third via hole and is in contact with the shading layer;
the passivation layer extends from the light emitting area to the light shielding area;
the flat layer extends from the light emitting area to the light shielding area;
the shading passivation layer is arranged on the flat layer and is positioned in the shading area;
and the black matrix layer is arranged on the shading passivation layer and is positioned in the shading area.
7. The display panel according to claim 1, wherein a thickness of the first portion is greater than a thickness of the second portion, and the thickness direction is a stacking direction of the substrate to the functional structure layer.
8. A display panel as claimed in claim 1 characterized in that the first part is provided as copper.
9. A method for manufacturing a display panel, for manufacturing the display panel according to any one of claims 1 to 8, comprising:
providing a substrate, and etching at least two grooves on the substrate;
depositing a copper film on one side of the substrate, which is provided with the groove, until the groove is filled;
grinding one side of the substrate, on which the copper film is deposited, until the copper film in the groove is reserved to obtain a first part;
depositing a metal layer on one side of the substrate, which is provided with the first part, and etching to obtain a second part, wherein the second part is arranged opposite to the first part;
and preparing a functional structure layer on one side of the substrate provided with the first part.
10. A display device characterized in that it comprises a display panel according to any one of claims 1 to 8.
CN202210806065.XA 2022-07-08 2022-07-08 Display panel, manufacturing method and display device Pending CN115274694A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210806065.XA CN115274694A (en) 2022-07-08 2022-07-08 Display panel, manufacturing method and display device

Publications (1)

Publication Number Publication Date
CN115274694A true CN115274694A (en) 2022-11-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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