CN115274555A - Array substrate manufacturing method, array substrate and display panel - Google Patents

Array substrate manufacturing method, array substrate and display panel Download PDF

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Publication number
CN115274555A
CN115274555A CN202211180027.4A CN202211180027A CN115274555A CN 115274555 A CN115274555 A CN 115274555A CN 202211180027 A CN202211180027 A CN 202211180027A CN 115274555 A CN115274555 A CN 115274555A
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layer
electrode layer
organic
array substrate
grinding
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霍英东
荣誉东
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Nanchang Virtual Reality Institute Co Ltd
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Nanchang Virtual Reality Institute Co Ltd
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Priority to CN202211180027.4A priority Critical patent/CN115274555A/en
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Priority to CN202310914060.3A priority patent/CN116864448A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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Abstract

The invention provides a method for manufacturing an array substrate, the array substrate and a display panel, and belongs to the technical field of display; the method comprises the steps of forming a first organic flat layer with a through hole on a substrate base plate formed with a thin film transistor; forming a first reflective electrode layer on the first organic planarization layer so that the first reflective electrode layer is electrically connected with the drain electrode of the thin film transistor through the via hole, and forming a recessed structure at the via hole; forming a second organic planarization layer on the first reflective electrode layer; grinding the second organic flat layer by using grinding equipment until the grinding equipment contacts the first reflecting electrode layer, and stopping grinding; and forming a second reflecting electrode layer on the first reflecting electrode layer to realize the integral flatness of the upper surface of the second reflecting electrode layer. Can solve the second reflection electrode that prior art exists and inevitably form convex sphere or concave sphere in the porefilling department through this application to produce the technical problem that stray light influences display effect and pixel aperture ratio in porefilling department.

Description

Array substrate manufacturing method, array substrate and display panel
Technical Field
The invention belongs to the technical field of display, and particularly relates to a method for manufacturing an array substrate, the array substrate and a display panel.
Background
In order to make the surface flatness of the reflective electrode film good, in the conventional manufacturing method of the pixel architecture of the array substrate of the conventional display panel, the first organic planarization layer 30 is grown on the lower surface of the first reflective electrode layer 40 as shown in fig. 1 to make the first reflective electrode flat, but because the first reflective electrode layer 40 at the via hole 31 is in a concave state, the electric field intensity generated by the first reflective electrode layer 40 and the common electrode of the upper substrate is larger than that of the open regions of other pixels, so that the first reflective electrode layer 40 at the via hole 31 cannot be used. In the prior art, in order to improve the pixel aperture ratio of the reflective electrode at the via hole, a hole filling method is usually adopted, and the process mainly includes depositing a second organic planarization layer 50 on the first reflective electrode layer 40 in a film forming manner in the structure of fig. 1, exposing a portion of the second organic planarization layer 50 corresponding to the via hole 31 in a blocking manner, developing and stripping to remove the second organic planarization layer 50, thereby partially leaving the second organic planarization layer 50 at the via hole 31, and growing a second reflective electrode layer 60 to cover the first reflective electrode layer 40 and the portion of the second organic planarization layer 50 for hole filling, as shown in fig. 2.
The hole filling method in the prior art is complex and complicated in process, and more fundamentally, because the organic material used by the organic flat layer and the metal material used by the reflective electrode have the phenomena of infiltration and non-infiltration, the surface of the second organic flat layer at the hole filling position can form a convex spherical surface or a concave spherical surface (specifically, the phenomenon of infiltration of the two materials can form a concave spherical surface, and the phenomenon of non-infiltration forms a convex spherical surface). However, the two materials are not capable of being infiltrated or not infiltrated, so that the second reflective electrode inevitably forms a convex spherical surface or a concave spherical surface at the filling hole, which means that the reflective electrode at the filling hole processed by the filling hole method in the prior art is not flat, and stray light is generated at the filling hole to affect the display effect and the pixel aperture ratio, thereby the aperture ratio of the reflective electrode cannot be really improved.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a method for manufacturing an array substrate, an array substrate and a display panel, wherein a second organic flat layer having a thickness greater than a depth of a first reflective electrode layer and formed on a first organic flat upper recess structure is subjected to organic grinding by using a grinding device, and grinding is stopped when the second organic flat layer is just in contact with the first reflective electrode by precisely controlling grinding processing, so that a film surface of a second reflective electrode layer formed on the first reflective electrode layer is in a completely flat state, thereby effectively improving a pixel aperture ratio of the array substrate and a display effect of the display panel, and effectively solving a technical problem that the aperture ratio of a pixel is affected by that the second reflective electrode at a filling hole is not flat because a convex spherical surface or a concave spherical surface is inevitably formed at the filling hole by the second reflective electrode in a coating film forming method in the prior art.
In a first aspect, the present invention provides a method for manufacturing an array substrate, including:
forming a first organic planarization layer having a via hole on a substrate base plate on which a thin film transistor is formed;
forming a first reflecting electrode layer on the first organic flat layer, so that the first reflecting electrode layer is electrically connected with the drain electrode of the thin film transistor through the through hole, and a concave structure is formed at the through hole;
forming a second organic planarization layer on the first reflective electrode layer, wherein the second organic planarization layer has a thickness greater than the depth of the recess structure;
grinding the second organic flat layer by using grinding equipment until the grinding equipment contacts the first reflecting electrode layer, and stopping grinding so that part of the second organic flat layer accommodated by the concave structure is remained, and the upper surface of the part of the second organic flat layer is flush with the upper surface of the first reflecting electrode;
and forming a second reflecting electrode layer on the first reflecting electrode layer so that the second reflecting electrode layer entirely covers the first reflecting electrode layer and the part of the second organic flat layer, and the upper surface of the second reflecting electrode layer is entirely flat.
Compared with the prior art, the invention has the beneficial effects that: forming a first reflecting electrode layer on the first organic flat layer with the through hole, and forming a concave structure at the through hole; forming a second organic flat layer with the thickness larger than the depth of the concave structure on the first reflecting electrode layer; the second organic flat layer is ground by adopting grinding equipment until the grinding equipment contacts the first reflection electrode layer, and grinding is stopped, so that the upper surface of the second organic flat layer is flush with the upper surface of the first reflection electrode layer, and the whole upper surface of the second reflection electrode layer formed on the first reflection electrode layer is flat, thereby effectively improving the pixel aperture ratio of the array substrate, and effectively solving the technical problem that the second reflection electrode at a filling hole is uneven because a convex spherical surface or a concave spherical surface is inevitably formed at the filling hole by the second reflection electrode in the coating and film forming method in the prior art.
Preferably, the polishing apparatus employs a chemical mechanical polishing process with a pre-prepared slurry to polish the second organic planarization layer.
Preferably, the chemical mechanical polishing process specifically includes: disposing a polishing pad of the polishing apparatus opposite to a film surface of the second organic planarization layer to be polished, and providing the pre-prepared slurry on the polishing pad; when the second organic flat layer is contacted with the grinding pad, the pre-prepared slurry generates hydrolysis reaction on the contacted second organic flat layer and cooperates with mechanical grinding to remove the second organic flat layer contacted with the grinding pad.
Preferably, the pre-slurry comprises ultrapure water, an abrasive, cerium oxide and an oxidant.
Preferably, the oxidizing agent comprises one or more of hydrogen peroxide, potassium persulfate, sodium persulfate and ammonium persulfate.
Preferably, the grinding processing time of the grinding equipment is determined by an end point detection method and the maximum grinding time.
Preferably, the end point detection method adopts laser reflected to the surface of the ground object, and judges whether the grinding end point is reached or not by analyzing the light intensity signal reflected by the surface of the ground object.
Preferably, the maximum polishing time is calculated by the thickness of the object to be polished and the polishing rate.
In a second aspect, the present invention further provides an array substrate, which is manufactured by the method for manufacturing an array substrate according to the first aspect.
Compared with the prior art, the invention has the beneficial effects that: by adopting the array substrate manufactured by the first aspect method, the pixel aperture opening ratio of the array substrate manufactured by the prior art method can be effectively improved, and the technical problem that the pixel aperture opening ratio is influenced because the second reflective electrode at the via hole is not flat due to the fact that the second reflective electrode inevitably forms a convex spherical surface or a concave spherical surface at the via hole in the coating film forming method in the prior art is effectively solved.
In a third aspect, the present invention further provides a display panel, which includes the array substrate of the first aspect.
Compared with the prior art, the invention has the beneficial effects that: by adopting the array substrate manufactured by the method of the first aspect, the display effect of the display panel can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic cross-sectional view of a pixel structure of an array substrate manufactured by a conventional method;
FIG. 2 is a flow chart illustrating a method for fabricating an array substrate according to the prior art;
fig. 3 is a schematic structural cross-sectional view of an array substrate according to embodiment 1 of the present invention;
fig. 4 is a schematic flow chart illustrating a manufacturing method of an array substrate according to embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of the specific structure prepared in step S04 of the array substrate manufacturing method in embodiment 1 of the present invention.
Description of reference numerals:
10-a substrate base plate;
20-thin film transistor, 21-drain;
30-a first organic planarization layer, 31-a via;
40-a first reflective electrode layer;
50-a second organic planarization layer;
60-a second reflective electrode layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the embodiments of the present invention and should not be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Example 1
As shown in fig. 3, the present embodiment provides an array substrate including a base substrate 10, and a thin film transistor 20, a first organic planarization layer 30, a first reflective electrode layer 40, a second organic planarization layer 50, and a second reflective electrode layer 60 sequentially grown on the base substrate 10. The first organic planarization layer 30 has a via hole 31, the first reflective electrode layer 40 is electrically connected to the drain electrode 21 of the thin film transistor 20 through the via hole 31, and the first reflective electrode layer 40 is formed on the first organic planarization layer 30 by a plating method, so that the first reflective electrode layer 40 forms a recess structure at the via hole 31. In this embodiment, the first organic planarization layer 30 and the second organic planarization layer 50 are made of organic materials, such as resin or rubber, and the first reflective electrode layer 40 and the second reflective electrode layer 60 are made of highly reflective metal materials, such as metal aluminum or metal copper.
Further, the recessed structure of the embodiment is filled with the second organic planarization layer 50, and the upper surface of the second organic planarization layer 50 having the filling function is flush with the upper surface of the first reflective electrode layer 40, so that the second reflective electrode layer 60 entirely covers the first reflective electrode layer 40 and a portion of the second organic planarization layer 50 at the via hole 31, thereby achieving the overall planarization of the upper surface of the second reflective electrode layer, thereby increasing the aperture ratio of the pixel at the via hole, and effectively solving the problem that the second reflective electrode at the via hole is not planarized due to the unavoidable formation of a convex spherical surface or a concave spherical surface at the via hole by the second reflective electrode in the film forming method of the prior art shown in fig. 2, so that the aperture ratio of the pixel at the via hole cannot be really increased by the array substrate manufactured by the coating film forming method of the prior art shown in fig. 2. It should be noted that the specific structure of the thin film transistor in this embodiment may be a conventional structure, and the specific structure is not related to the content to be protected in this application, so that details are described herein.
Fig. 4 shows a method for manufacturing an array substrate according to the present embodiment, the method includes:
and S01, forming a first organic flat layer with a through hole on the substrate base plate on which the thin film transistor is formed.
Specifically, before depositing the thin film transistor on the provided substrate, the substrate may be cleaned, and the thin film transistor may be deposited on the cleaned substrate, and may include a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode; and forming a first organic planarization layer having a via hole on the substrate base plate on which the thin film transistor is formed using a coating method. In other embodiments, the first organic planarization layer may be deposited by physical vapor deposition or chemical vapor deposition.
And S02, forming a first reflecting electrode layer on the first organic flat layer so that the first reflecting electrode layer is electrically connected with the drain electrode of the thin film transistor through the via hole, and forming a concave structure at the via hole.
Specifically, a first reflective electrode layer is formed on the first organic flat layer by a coating method, and because the first organic flat layer is provided with a via hole, when the first organic flat layer at the via hole is coated, the first reflective electrode layer covers the via hole and contacts with the drain electrode of the thin film transistor corresponding to the via hole, so that the first reflective electrode layer is electrically connected with the thin film transistor; in addition, the first reflective electrode layer at the via hole forms a recess structure. The specific structure prepared by this step can be referred to as shown in fig. 1.
And S03, forming a second organic flat layer on the first reflecting electrode layer, wherein the thickness of the second organic flat layer is greater than the depth of the concave structure.
Specifically, in order to ensure that the film surface of the second organic planarization layer filling the via hole is higher than the film surface of the first reflective electrode layer, when the second organic planarization layer is formed on the first reflective electrode layer by a coating method, the thickness of the second organic planarization layer must be larger than the depth of the recess structure. In this embodiment, the reason why the film surface of the second organic planarization layer at the via hole is higher than the film surface of the first reflective electrode layer is that the subsequent polishing process for the second organic planarization layer is facilitated, and the upper surface of the second organic planarization layer subjected to the polishing process is flush with the upper surface of the first reflective electrode layer. The specific structure prepared by this step can be referred to as the first diagram in fig. 2.
And S04, grinding the second organic flat layer by adopting grinding equipment until the grinding equipment contacts the first reflecting electrode layer to stop grinding, so that a part of the second organic flat layer accommodated by the concave structure is reserved, and the upper surface of the part of the second organic flat layer is flush with the upper surface of the first reflecting electrode.
And the grinding equipment is matched with the prefabricated grinding slurry to grind the second organic flat layer by adopting a chemical mechanical grinding process. In this embodiment, the pre-slurry includes ultrapure water, an abrasive, cerium oxide, and an oxidant, which is one or a combination of two or more of hydrogen peroxide, potassium persulfate, sodium persulfate, and ammonium persulfate.
Specifically, the chemical mechanical polishing process specifically includes: arranging a grinding pad of grinding equipment opposite to the film surface of the second organic flat layer to be ground, and providing prefabricated grinding slurry on the grinding pad; when the second organic flat layer is contacted with the grinding pad, the pre-prepared grinding slurry generates hydrolysis reaction on the contacted second organic flat layer and is matched with mechanical grinding so as to remove the second organic flat layer contacted with the grinding pad; when the polishing device polishes the upper surface of the first reflective electrode layer, the polishing device recognizes the first reflective electrode layer and stops the organic polishing operation because the aluminum material of the first reflective electrode layer is hard. The method can completely remove the second organic flat layer in the non-via hole region, and leave the second organic flat layer at the via hole, so that the surface of the second organic flat layer at the via hole is completely flat and flush with the surface of the first reflecting electrode layer. In this embodiment, the surface of the second organic planarization layer to be polished can be in a completely flat state by the chemical mechanical polishing process, the completely flat second organic planarization layer is manufactured to fill the via hole, the flatness of the film surface is greatly improved compared with the coating film forming manner in the prior art, and after the chemical mechanical polishing process is completed, the second reflective electrode layer is formed, so that the second reflective electrode layer with a completely flat whole surface is formed, which solves the problem that the aperture opening ratio of the pixel at the via hole cannot be really improved even in the array substrate manufactured by the coating film forming method in the prior art as shown in fig. 2, thereby improving the aperture opening ratio of the pixel of the array substrate in this embodiment.
Further, in the present embodiment, the polishing time of the cmp process for the second organic planarization layer is determined by the endpoint detection method and the maximum polishing time. Specifically, the end point detection method adopts laser to reflect to the surface of an object to be ground, and judges whether the grinding end point is reached or not by analyzing a light intensity signal reflected by the surface of the object to be ground; in the grinding process, the end point detection method utilizes laser to emit to the surface of the ground second organic flat layer, judges whether the ground object reaches the grinding end point by analyzing a light intensity signal reflected by the surface of the ground object, specifically utilizes the difference of the reflectivity of the ground second organic flat layer made of organic materials and the reflectivity of the metal first reflecting electrode layer, judges whether the metal first reflecting metal layer is ground by analyzing the light intensity change of the reflected light, and indicates that the metal first reflecting metal layer is ground when the light intensity of the reflected light reaches the maximum value and does not change in a short time.
Furthermore, in order to avoid the abnormality of the chemical mechanical polishing process or the machine during the polishing process, the chemical mechanical polishing process can set a maximum polishing time parameter through the thickness of the second organic planarization layer to be polished to restrict and control the maximum polishing time, thereby preventing the first reflective electrode layer from being over-polished and even preventing the film layer from being damaged due to the abnormality of the machine or other reasons. The maximum polishing time in this example was calculated from the thickness of the object to be polished and the polishing rate.
In this step, the membrane surface of the second organic planarization layer to be polished is disposed opposite to the rotating polishing pad by using the principle of mechanical polishing, and a pre-prepared polishing slurry of a polishing material and a chemical additive is provided on the polishing pad. By the repeated action of the chemical reaction and the mechanical grinding, the end point detection method and the parameter method for setting the maximum grinding time, the chemical mechanical grinding process can be stopped in time when the second organic flat layer is ground to the film surface of the first reflecting electrode layer, so that the grinding work is accurately controlled. The specific structure prepared by this step is shown in fig. 5.
And S05, forming a second reflecting electrode layer on the first reflecting electrode layer so that the second reflecting electrode layer entirely covers the first reflecting electrode layer and the part of the second organic flat layer, and realizing the integral flatness of the upper surface of the second reflecting electrode layer.
Specifically, by means of a chemical mechanical polishing process for the second organic flat layer, the second organic flat layer is filled in the via holes, and the upper surfaces of the first reflective electrodes on the upper surface of the partially remained second organic flat layer are flush with each other, so that the deposited second reflective electrode layer is a reflective electrode with a completely flat whole surface, the pixel aperture ratio of the via holes is really improved, and the pixel aperture ratio of the array substrate is integrally improved. The specific structure prepared by this step can be seen in fig. 3.
In summary, through the above steps, the pixel aperture ratio of the array substrate is effectively improved, and the technical problem that the second reflective electrode at the filled hole is uneven due to the fact that the second reflective electrode inevitably forms a convex spherical surface or a concave spherical surface at the filled hole in the coating and film forming method in the prior art is effectively solved. Compared with the coating film forming method in the prior art, the method of the embodiment simplifies the manufacturing process steps, reduces the process complexity, particularly saves the exposure and development processing procedures of the second organic flat layer in the prior art, and saves the manufacturing time and cost.
Example 2
The embodiment provides a display panel, and the array substrate of embodiment 1 is specifically adopted, so that the display effect of the display panel can be effectively improved. The display panel of the embodiment adopts the array substrate manufactured by the manufacturing method of embodiment 1, so that the pixel aperture ratio of the array substrate manufactured by the method in the prior art can be effectively improved, and the problem that the pixel aperture ratio of the display panel in the prior art is affected because the second reflective electrode at the via hole is not flat due to the fact that the second reflective electrode inevitably forms a convex spherical surface or a concave spherical surface at the via hole in the coating and film forming method in the prior art as shown in fig. 2 is effectively solved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. A method for manufacturing an array substrate is characterized by comprising the following steps:
forming a first organic planarization layer having a via hole on a substrate base plate on which a thin film transistor is formed;
forming a first reflecting electrode layer on the first organic flat layer, so that the first reflecting electrode layer is electrically connected with the drain electrode of the thin film transistor through the through hole, and a concave structure is formed at the through hole;
forming a second organic planarization layer on the first reflective electrode layer, wherein the second organic planarization layer has a thickness greater than the depth of the recess structure;
grinding the second organic flat layer by using grinding equipment until the grinding equipment contacts the first reflecting electrode layer, and stopping grinding so that part of the second organic flat layer accommodated by the concave structure is remained, and the upper surface of the part of the second organic flat layer is flush with the upper surface of the first reflecting electrode;
and forming a second reflecting electrode layer on the first reflecting electrode layer so that the second reflecting electrode layer entirely covers the first reflecting electrode layer and the part of the second organic flat layer, and the integral flatness of the upper surface of the second reflecting electrode layer is realized.
2. The method of claim 1, wherein the polishing apparatus is used to polish the second organic planarization layer with a pre-prepared slurry by a chemical mechanical polishing process.
3. The method of claim 2, wherein the chemical mechanical polishing process comprises: disposing a polishing pad of the polishing apparatus opposite to a film surface of the second organic planarization layer to be polished, and providing the pre-prepared slurry on the polishing pad; when the second organic flat layer is contacted with the grinding pad, the pre-prepared slurry generates hydrolysis reaction on the contacted second organic flat layer and cooperates with mechanical grinding to remove the second organic flat layer contacted with the grinding pad.
4. The method of claim 2 or 3, wherein the pre-slurry comprises ultrapure water, an abrasive, cerium oxide and an oxidant.
5. The method of claim 4, wherein the oxidant comprises one or more of hydrogen peroxide, potassium persulfate, sodium persulfate, and ammonium persulfate.
6. The method of claim 1, wherein the polishing time of the polishing apparatus is determined by an endpoint detection method and a maximum polishing time.
7. The method for manufacturing an array substrate of claim 6, wherein the end point detection method employs laser reflection to the surface of the object to be polished, and determines whether the polishing end point is reached by analyzing the light intensity signal reflected by the surface of the object to be polished.
8. The method of claim 6, wherein the maximum polishing time is calculated from a thickness of the object to be polished and a polishing rate.
9. An array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 8.
10. A display panel comprising the array substrate according to claim 9.
CN202211180027.4A 2022-09-27 2022-09-27 Array substrate manufacturing method, array substrate and display panel Pending CN115274555A (en)

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CN109904211A (en) * 2019-03-28 2019-06-18 合肥京东方卓印科技有限公司 A kind of array substrate, its production method, display panel and display device
CN110164930A (en) * 2019-05-22 2019-08-23 上海视涯信息科技有限公司 A kind of strong microcavity silicon-based organic light-emitting display device and forming method thereof

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CN103094306A (en) * 2011-11-03 2013-05-08 三星显示有限公司 Flexible display device
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