CN115274551A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The present disclosure relates to a semiconductor structure and a method of fabricating the same. The preparation method of the semiconductor structure comprises the following steps: forming a plurality of bit line structures which are arranged at intervals on a substrate; forming an initial filling dielectric layer, wherein the initial filling dielectric layer at least fills the gap between the adjacent bit line structures; removing part of the initial filling dielectric layer between the adjacent bit line structures to form a filling dielectric layer, wherein the height of the filling dielectric layer is smaller than that of the bit line structures in the direction vertical to the substrate; removing the filling dielectric layer and part of the bit line dielectric layer to form a storage node contact hole between adjacent bit line structures; and forming a storage node contact structure in the storage node contact hole, wherein the storage node contact structure is filled in the storage node contact hole without a pore. The preparation method of the semiconductor structure can reduce the depth-to-width ratio of the prepared groove, avoid the existence of pores due to insufficient filling of the storage node contact structure, further improve the electrical property of the obtained semiconductor structure and improve the process yield.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for fabricating the same.

Background

With the shrinking of semiconductor process dimensions, the critical dimensions become smaller in the Dynamic Random Access Memory (DRAM) process; in the process of manufacturing the contact structure, the aspect ratio of the trench is higher and higher, which results in insufficient filling of the contact structure material and more serious defects of voids (Void), thereby causing serious electrical anomaly problems, such as higher resistance, and further affecting the yield (yield loss) of the semiconductor manufacturing process.

Therefore, it is an urgent need to solve the problem of insufficient filling of contact structure material and void in semiconductor process.

Disclosure of Invention

In view of the above, it is necessary to provide a semiconductor structure and a method for fabricating the same.

In one aspect, the present disclosure provides a method for fabricating a semiconductor structure, including:

providing a substrate;

forming a plurality of bit line structures arranged at intervals on the substrate; the bit line structure comprises a stacked structure; the laminated structure comprises a bit line conducting layer and a bit line dielectric layer which are sequentially laminated from bottom to top;

forming an initial filling dielectric layer, wherein the initial filling dielectric layer at least fills the gap between the adjacent bit line structures;

removing part of the initial filling dielectric layer positioned between the adjacent bit line structures to form a filling dielectric layer; in the direction vertical to the substrate, the height of the filling dielectric layer is smaller than that of the bit line structure;

removing the filling dielectric layer and part of the bit line dielectric layer to form a storage node contact hole between adjacent bit line structures;

and forming a storage node contact structure in the storage node contact hole, wherein the storage node contact structure is filled in the storage node contact hole without a pore.

In one embodiment, the removing the portion of the initial filling medium layer includes:

forming a patterned photoresist layer on the bit line structure and the upper surface of the initial filling dielectric layer;

etching and removing a part of the initial filling dielectric layer positioned between the adjacent bit line structures based on the patterned photoresist layer;

and removing the patterned photoresist layer.

In one embodiment, a bottom dielectric layer is further formed on the upper surface of the substrate between the adjacent bit line structures;

the removing the filling dielectric layer and part of the bit line dielectric layer comprises the following steps:

removing the bit line dielectric layer higher than the upper surface of the filling dielectric layer;

removing the filling dielectric layer;

after the filling dielectric layer is removed, the preparation method of the semiconductor structure further comprises the following steps:

and removing the bottom dielectric layer to expose the substrate.

In one embodiment, the bit line structure further includes a spacer;

the side wall is positioned on the side wall of the laminated structure;

and removing part of the side wall while removing part of the bit line dielectric layer.

In one embodiment, after forming the storage node contact structure in the storage node contact hole, the method for manufacturing the semiconductor structure further includes:

and removing the exposed side wall.

In one embodiment, the forming of the storage node contact structure in the storage node contact hole includes:

forming a conductive material layer; the conductive material layer fills the storage node contact hole and covers the bit line structure;

back-etching the conductive material layer to remove the conductive material layer outside the storage node contact hole and part of the conductive material layer in the storage node contact hole; the conductive material layer remained in the storage node contact hole is the storage node contact structure.

In one embodiment, the substrate comprises an array region and a peripheral region located at the periphery of the array region;

a covering dielectric layer is also formed in the peripheral area and covers the peripheral area;

while removing part of the bit line dielectric layer, the preparation method of the semiconductor structure further comprises the following steps:

and removing part of the covering dielectric layer to enable the upper surface of the remaining covering dielectric layer to be flush with the upper surface of the filling dielectric layer.

In one embodiment, the conductive material layer also covers the upper surface of the covering dielectric layer reserved in the peripheral region;

the forming of the storage node contact structure in the storage node contact hole includes:

and back-etching the conductive material layer to remove the conductive material layer on the upper surface of the reserved covering dielectric layer.

In one embodiment, a transistor is further formed on the upper surface of the peripheral region, and the covering dielectric layer covers the transistor.

In one embodiment, in the process of removing a part of the initial filling dielectric layer between adjacent bit line structures, the thickness of the removed initial filling dielectric layer is 1/2-2/3 of the height of the bit line dielectric layer.

In one embodiment, before forming a plurality of bit line structures arranged at intervals on the substrate, the method for manufacturing a semiconductor structure further includes:

forming an embedded word line in the substrate, the embedded word line extending along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction.

In one embodiment, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate;

after forming the embedded word lines in the substrate and before forming a plurality of bit line structures arranged at intervals on the substrate, the method for manufacturing a semiconductor structure further includes:

forming a bit line contact structure in the substrate, wherein the bit line contact structure is in contact with the active region; the bit line conductive layer of the bit line structure is in contact with the bit line contact structure.

In another aspect, the present disclosure also provides, in accordance with some embodiments, a semiconductor structure, comprising:

the bit line structure comprises a substrate, a bit line structure and a bit line structure, wherein the substrate is provided with a plurality of bit line structures which are arranged at intervals; the bit line structure comprises a stacked structure; the laminated structure comprises a bit line conducting layer and a bit line dielectric layer which are sequentially laminated from bottom to top;

a storage node contact hole located between adjacent bit line structures;

a storage node contact structure located within the storage node contact hole;

the forming method of the storage node contact hole comprises the following steps:

forming an initial filling dielectric layer, wherein the initial filling dielectric layer at least fills the gap between the adjacent bit line structures;

removing part of the initial filling dielectric layer between the adjacent bit line structures to form a filling dielectric layer, wherein the height of the filling dielectric layer is smaller than that of the bit line structures in the direction perpendicular to the substrate;

and removing the filling dielectric layer and part of the bit line dielectric layer to form a storage node contact hole between adjacent bit line structures.

In one embodiment, the bit line structure further includes a sidewall spacer, and the sidewall spacer is located on a sidewall of the stacked structure;

the substrate is also provided with an embedded word line, and the embedded word line extends along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction;

a shallow trench isolation structure is formed in the substrate and isolates a plurality of active regions arranged at intervals in the substrate; the semiconductor structure further includes:

a bit line contact structure contacting the active region; the bit line conductive layer of the bit line structure is in contact with the bit line contact structure.

In one embodiment, the substrate comprises an array region and a peripheral region located at the periphery of the array region;

a transistor is further formed on the upper surface of the peripheral area, a covering dielectric layer is formed in the peripheral area, and the transistor is covered by the covering dielectric layer.

The semiconductor structure and the preparation method thereof provided by the disclosure have at least the following beneficial effects:

according to the preparation method of the semiconductor structure, when the groove for accommodating the storage node contact structure between the adjacent bit line structures is prepared, the initial filling dielectric layer is removed to form the filling dielectric layer, and then the filling dielectric layer and part of the bit line dielectric layer are removed by utilizing the difference of the etching ratio of the initial filling dielectric layer and the bit line dielectric layer, so that the depth-to-width ratio of the prepared groove can be reduced, the situation that the hole exists due to insufficient filling of the storage node contact structure is avoided, the electrical property of the obtained semiconductor structure can be improved, and the process yield is improved.

In the semiconductor structure provided by the disclosure, the storage node contact hole is formed by removing part of the initial filling dielectric layer to form the filling dielectric layer and then removing the filling dielectric layer and part of the bit line dielectric layer by utilizing the difference of the etching ratio of the initial filling dielectric layer to the bit line dielectric layer, so that the depth-to-width ratio of the groove for accommodating the storage node contact structure between the adjacent bit line structures is reduced, the storage node contact structure in the storage node contact hole does not have a hole, and the problem of electrical property abnormity can be avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present disclosure, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 2 (a) is a schematic cross-sectional structure diagram of a structure obtained in step S3 in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure in the aa 'direction in fig. 3, (b) in fig. 2 is a schematic cross-sectional structure diagram of a structure obtained in step S3 in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure in the bb' direction in fig. 3, and (c) in fig. 2 is a schematic cross-sectional structure diagram of a structure obtained in step S3 in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure in the peripheral region;

fig. 3 is a schematic top-view structural diagram of an array region in the structure obtained in step S2 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 4 is a flowchart of step S4 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 5 (a) is a schematic cross-sectional structure diagram of the structure obtained in step S401 in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure, the direction aa 'in fig. 3, fig. 5 (b) is a schematic cross-sectional structure diagram of the structure obtained in step S401 in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure, the direction bb' in fig. 3, and fig. 5 (c) is a schematic cross-sectional structure diagram of the structure obtained in step S401 in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure, the peripheral region;

fig. 6 (a) is a schematic cross-sectional structure view of the structure obtained in step S403 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the direction aa 'in fig. 3, (b) in fig. 6 is a schematic cross-sectional structure view of the structure obtained in step S403 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the direction bb' in fig. 3, and (c) in fig. 6 is a schematic cross-sectional structure view of the structure obtained in step S403 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the peripheral region;

fig. 7 is a flowchart illustrating a step S5 in a method for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 8 (a) is a schematic cross-sectional structure diagram of the structure obtained in step S502 in the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure, the direction aa 'in fig. 3, fig. 8 (b) is a schematic cross-sectional structure diagram of the structure obtained in step S502 in the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure, the direction bb' in fig. 3, and fig. 8 (c) is a schematic cross-sectional structure diagram of the structure obtained in step S502 in the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure, the peripheral region;

fig. 9 is a flowchart of step S6 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 10 (a) is a schematic cross-sectional structure view of the structure obtained in step S601 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the direction aa 'in fig. 3, (b) in fig. 10 is a schematic cross-sectional structure view of the structure obtained in step S601 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the direction bb' in fig. 3, and (c) in fig. 10 is a schematic cross-sectional structure view of the structure obtained in step S601 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the peripheral region;

fig. 11 (a) is a schematic cross-sectional structure view of the structure obtained in step S602 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the aa 'direction in fig. 3, (b) in fig. 11 is a schematic cross-sectional structure view of the structure obtained in step S602 in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, taken along the bb' direction in fig. 3, and (c) in fig. 11 is a schematic cross-sectional structure view of the structure obtained in step S602 in the peripheral region in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 12 (a) is a schematic cross-sectional structure view of a structure obtained after removing the exposed side wall in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure in the direction aa 'in fig. 3, fig. 12 (b) is a schematic cross-sectional structure view of a structure obtained after removing the exposed side wall in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure in the direction bb' in fig. 3, and fig. 12 (c) is a schematic cross-sectional structure view of a structure obtained after removing the exposed side wall in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure in the peripheral region; fig. 12 (a) is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the disclosure along a direction aa 'in fig. 3, fig. 12 (b) is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the disclosure along a direction bb' in fig. 3, and fig. 12 (c) is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the disclosure along a peripheral region.

Description of reference numerals:

1. a substrate; 101. covering the dielectric layer; 102. a transistor; 103. a buried word line; 104. a shallow trench isolation structure; 105. an active region; 106. a bit line contact structure; 2. a bit line structure; 201. a bit line conductive layer; 202. a bit line dielectric layer; 203. a side wall; 3. initially filling a dielectric layer; 4. filling the dielectric layer; 401. patterning the photoresist layer; 5. a storage node contact hole; 6. a storage node contact structure; 601. a layer of conductive material; 7. a bottom dielectric layer.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It will be understood that when an element or layer is referred to as being "on" 8230a other element or layer, it can be directly on the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure; for example, a first direction may be referred to as a second direction, and similarly, a second direction may be referred to as a first direction; the first direction and the second direction are different directions.

Spatial relationship terms such as "on 8230; upper", "… upper surface", etc., may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, the top surface elements or features described as "on 8230; up", "\8230"; would be oriented "under" the other elements or features. Thus, the exemplary terms "at 8230; upper", "… upper surface" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

The present disclosure provides, according to some embodiments, a method of fabricating a semiconductor structure.

Referring to fig. 1, in one embodiment, a method for fabricating a semiconductor structure may include the steps of:

s1: a substrate is provided.

S2: forming a plurality of bit line structures arranged at intervals on a substrate; the bit line structure may include a stacked structure; the stacked structure may include a bit line conductive layer and a bit line dielectric layer stacked in sequence from bottom to top.

S3: forming an initial filling dielectric layer; the initial fill dielectric layer should at least fill the gaps between adjacent bitline structures.

S4: removing part of the initial filling dielectric layer positioned between the adjacent bit line structures to form a filling dielectric layer; wherein, in the direction vertical to the substrate, the height of the filling dielectric layer should be smaller than that of the bit line structure.

S5: and removing the filling dielectric layer and part of the bit line dielectric layer to form a storage node contact hole between the adjacent bit line structures.

S6: and forming a storage node contact structure in the storage node contact hole, wherein the storage node contact structure is filled in the storage node contact hole without a pore.

In the method for manufacturing a semiconductor structure according to the embodiment, when the trench for accommodating the storage node contact structure between the adjacent bit line structures is formed, the filling dielectric layer is formed by removing a part of the initial filling dielectric layer by using the difference between the etching ratios of the initial filling dielectric layer and the bit line dielectric layer, the size of the subsequent trench is defined, and then the filling dielectric layer and a part of the bit line dielectric layer are removed, so that the aspect ratio of the prepared trench can be reduced, the existence of pores due to insufficient filling of the storage node contact structure is avoided, the electrical property of the obtained semiconductor structure can be improved, and the process yield is improved.

Referring to fig. 2, in step S1, a substrate 1 is provided.

The material of the substrate 1 is not particularly limited in the method for manufacturing a semiconductor structure provided in the present disclosure. By way of example, the substrate 1 may include, but is not limited to, any one or more of a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or the like; that is, the material of the substrate 1 may include, but is not limited to, any one or more of silicon (Si), sapphire, glass, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like.

In some possible embodiments of the present disclosure, the substrate 1 may include an array region and a peripheral region (Periphery) located at the Periphery of the array region.

Referring to fig. 2 (a) and fig. 2 (b), in the method for fabricating a semiconductor structure according to the present disclosure, a shallow trench isolation structure 104 may be formed in a substrate 1, and the shallow trench isolation structure 104 isolates a plurality of active regions 105 arranged at intervals in the substrate 1.

With reference to fig. 2, in step S2, a plurality of bit line structures 2 arranged at intervals are formed on a substrate 1.

Specifically, the bit line structure 2 may include a stacked structure. The stacked structure may include a bit line conductive layer 201 and a bit line dielectric layer 202 stacked in sequence from bottom to top.

In one embodiment, before forming the plurality of bit line structures 2 arranged at intervals on the substrate 1, the method for manufacturing a semiconductor structure may further include a step of forming the buried word lines 103.

Specifically, the buried word lines 103 extending in the first direction may be formed within the substrate 1. On this basis, the bit line structure 2 should extend in the second direction, and the second direction should intersect the first direction.

In the method for manufacturing the semiconductor structure provided by the present disclosure, the materials of the bit line conductive layer 201 and the bit line dielectric layer 202 are not specifically limited. As an example, the material of the bit line conductive layer 201 may include, but is not limited to, titanium (Ti) or tungsten (W). By way of example, the bit line dielectric layer 202 may include, but is not limited to, a silicon nitride (SiN) layer.

In some embodiments in which the embedded word line 103 is formed in the substrate 1, the method for manufacturing the semiconductor structure may further form a bit line contact structure 106 in the substrate 1 before forming the bit line structure 2.

Specifically, the bit line contact structure 106 should contact the active region 105. On this basis, the bit line conductive layer 201 of the bit line structure 2 should be in contact with the bit line contact structure 106.

The material of the bit line contact structure 106 in the method for manufacturing a semiconductor structure provided in the present disclosure is not particularly limited. By way of example, the bit line contact structure 106 may include, but is not limited to, any one or more of a polysilicon layer, a titanium nitride (TiN) layer, and/or a tungsten layer.

With continued reference to fig. 2, in step S3, an initial filling dielectric layer 3 is formed.

Specifically, the initial filling dielectric layer 3 should at least fill the gap between the adjacent bit line structures 2.

Continuing to refer to FIG. 2 in conjunction with FIG. 3, FIG. 3 illustrates the aa 'and bb' directions in an embodiment of the disclosure; fig. 2 (a) shows a schematic cross-sectional structure of the structure obtained in step S3 in the present disclosure in the direction aa 'in fig. 3, and fig. 2 (b) shows a schematic cross-sectional structure of the structure obtained in step S3 in the present disclosure in the direction bb' in fig. 3.

Fig. 3 is a schematic top view of the array region in the structure obtained in step S2.

In step S4, a part of the initial filling dielectric layer 3 located between the adjacent bit line structures 2 is removed, and the remaining initial filling dielectric layer 3 is used as a filling dielectric layer 4. The height of the fill dielectric layer 4 should be less than the height of the bit line structure 2 in the direction perpendicular to the substrate 1.

In the method for manufacturing a semiconductor structure provided by the present disclosure, the filling dielectric layer 4 may be formed by removing a portion of the initial filling dielectric layer 3 in step S4, and the size of the bit line dielectric layer 202 to be removed in step S5 is defined.

In the method for manufacturing a semiconductor structure provided by the present disclosure, the thickness of the initial filling dielectric layer 3 removed in the process of removing a portion of the initial filling dielectric layer 3 located between adjacent bit line structures 2 is not specifically limited. As an example, the thickness of the removed initial filling dielectric layer 3 in the process of removing the part of the initial filling dielectric layer 3 located between the adjacent bit line structures 2 may be 1/2 to 2/3 of the height of the bit line dielectric layer 202; for example, the thickness of the removed initial fill dielectric layer 3 may be 1/2, 7/12, or 2/3, etc. of the height of the bit line dielectric layer 202.

The material of the initial filling dielectric layer 3 and the material of the filling dielectric layer 4 are not specifically limited in the method for manufacturing the semiconductor structure provided by the present disclosure. By way of example, the initial fill Dielectric layer 3 and the fill Dielectric layer 4 may each include, but are not limited to, a Spin On Dielectric (SOD) layer. The initial filling dielectric layer 3 and the filling dielectric layer 4 formed by adopting a spin coating mode can have better adhesiveness and gap filling capability.

Referring to fig. 5 to fig. 6 in conjunction with fig. 4, in one embodiment, the following steps may be adopted to remove a portion of the initial filling dielectric layer 3 located between adjacent bit line structures 2, including:

s401: a patterned photoresist layer 401 is formed on the upper surface of the bit line structure 2 and the initial filling dielectric layer 3.

As shown in fig. 5, (a) in fig. 5 shows a schematic cross-sectional structure of the structure obtained at step S401 in the present disclosure in the direction aa 'in fig. 3, and (b) in fig. 5 shows a schematic cross-sectional structure of the structure obtained at step S401 in the present disclosure in the direction bb' in fig. 3. It should be noted that, since the patterned photoresist layer 401 has an opening (not shown) therein, the opening exposes the array region, and thus, fig. 5 (a) and fig. 5 (b) correspond to the opening in the patterned photoresist layer 401, and the patterned photoresist layer 401 does not exist.

S402: based on the patterned photoresist layer 401, the initial filling dielectric layer 3 between the adjacent bit line structures 2 is etched and removed.

S403: the patterned photoresist layer 401 is removed.

As shown in fig. 6, (a) in fig. 6 shows a schematic cross-sectional structure of the structure obtained at step S403 in the present disclosure in the direction aa 'in fig. 3, and (b) in fig. 6 shows a schematic cross-sectional structure of the structure obtained at step S403 in the present disclosure in the direction bb' in fig. 3.

The present disclosure does not specifically limit the manner of forming the patterned photoresist layer 401 in step S401. By way of example, patterned photoresist layer 401 may be formed using the following methods, such as: forming a photoresist layer covering the upper surface of the obtained structure by a coating-curing method, an ink-jet printing method or a deposition method; the photoresist layer is patterned through patterning processing modes such as masking, exposure, development, etching and the like, so that the patterned photoresist layer 401 is obtained.

In the method for manufacturing a semiconductor structure provided in the present disclosure, the material of the patterned photoresist layer 401 in step S401 is not particularly limited. As an example, the material of the patterned photoresist layer 401 may include a resist material.

The present disclosure does not specifically limit the manner of removing part of the initial filling dielectric layer 3 in step S402. By way of example, but not limitation, an oxide Clean (CLN) process may be employed to remove portions of the initial fill dielectric layer 3.

The present disclosure does not specifically limit the manner of removing the patterned photoresist layer 401 in step S403. By way of example, but not limitation, an Ashing (ASH) process may be used to remove patterned photoresist layer 401.

Referring to fig. 7 to 8, in step S5, the filling dielectric layer 4 and a portion of the bit line dielectric layer 202 are removed to form a storage node contact hole 5 between adjacent bit line structures 2.

As shown in fig. 7, in one embodiment, the following steps may be taken to remove the fill dielectric layer 4 and a portion of the bit line dielectric layer 202, including:

s501: the bit line dielectric layer 202 above the upper surface of the fill dielectric layer 4 is removed.

S502: the filling medium layer 4 is removed.

As shown in fig. 8, (a) in fig. 8 shows a schematic cross-sectional structure of the structure obtained at step S502 in the present disclosure in the direction aa 'in fig. 3, and (b) in fig. 8 shows a schematic cross-sectional structure of the structure obtained at step S502 in the present disclosure in the direction bb' in fig. 3.

In some possible embodiments of the present disclosure, as shown in fig. 6 (a), the upper surface of the substrate 1 between adjacent bit line structures 2 may also be formed with a bottom dielectric layer 7. On the basis, as shown in (a) of fig. 8, the method for manufacturing the semiconductor structure may further remove the bottom dielectric layer 7 after removing the filling dielectric layer 4 to expose the substrate 1.

In some possible embodiments of the present disclosure, as shown in fig. 6 (a), the bit line structure 2 may further include a sidewall spacer 203. On this basis, as shown in (a) of fig. 8, the method for manufacturing the semiconductor structure may remove a part of the sidewall spacers 203 while removing a part of the bit line dielectric layer 202.

As previously described, in some possible embodiments of the present disclosure, the substrate 1 may include an array region and a peripheral region located at the periphery of the array region. As shown in fig. 6 (c), the peripheral region is also formed with a cover dielectric layer 101 covering the peripheral region.

On the basis, as shown in fig. 8 (c), the manufacturing method of the semiconductor structure may remove a portion of the capping dielectric layer 101 while removing a portion of the bit line dielectric layer 202, and make the upper surface of the remaining capping dielectric layer 101 flush with the upper surface of the filling dielectric layer 4.

In the above embodiment, when the bit line dielectric layer 202 higher than the upper surface of the filling dielectric layer 4 is removed, part of the capping dielectric layer 101 may be removed simultaneously until the upper surface of the remaining capping dielectric layer 101 is flush with the upper surface of the filling dielectric layer 4, and the removal may be stopped.

In one embodiment, a transistor 102 is also formed on the top surface of the peripheral region.

Specifically, the capping dielectric layer 101 may encapsulate the transistor 102.

The method for manufacturing the semiconductor structure provided in the present disclosure is not particularly limited to the form of the transistor 102. By way of example, the Transistor 102 may include, but is not limited to, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET or MOS).

The material of the cover dielectric layer 101 in the method for manufacturing a semiconductor structure provided in the present disclosure is not particularly limited. By way of example, the material of the capping dielectric layer 101 may include, but is not limited to, a silicon nitride layer.

In one embodiment, the material of the capping dielectric layer 101 may be the same as the material of the bit line dielectric layer 202.

In some possible embodiments, a pad oxide layer and a nitride layer may be formed in the peripheral region. A pad oxide layer and a nitride layer may be sequentially formed on the substrate 1, and the shallow trench isolation structure 104 may be formed on the surface of the nitride layer away from the pad oxide layer.

Referring to fig. 9 to 11, in step S6, a storage node contact structure 6 is formed in the storage node contact hole 5, and the storage node contact structure 6 is filled in the storage node contact hole 5 without a void.

As shown in fig. 9, in one embodiment, the following steps may be employed to form a storage node contact structure 6 within the storage node contact hole 5, including:

s601: a layer of conductive material 601 is formed.

Specifically, the conductive material layer 601 should fill the storage node contact hole 5 and cover the bit line structure 2.

As shown in fig. 10, (a) in fig. 10 shows a schematic cross-sectional structure of the structure obtained in step S601 in the present disclosure in the direction aa 'in fig. 3, and (b) in fig. 10 shows a schematic cross-sectional structure of the structure obtained in step S601 in the present disclosure in the direction bb' in fig. 3.

S602: etching back the conductive material layer 601 to remove the conductive material layer 601 outside the storage node contact hole 5 and a part of the conductive material layer 601 inside the storage node contact hole 5; the conductive material layer 601 remaining in the storage node contact hole 5 is the storage node contact structure 6.

As shown in fig. 11, (a) in fig. 11 shows a schematic cross-sectional structure of the structure obtained at step S602 in the present disclosure in the direction aa 'in fig. 3, and (b) in fig. 11 shows a schematic cross-sectional structure of the structure obtained at step S602 in the present disclosure in the direction bb' in fig. 3.

The present disclosure does not specifically limit the manner of forming the conductive material layer 601 in step S601. By way of example, the conductive material layer 601 may be formed by a Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), high density Plasma Deposition (PCVD), plasma Enhanced Deposition (PECVD), or Atomic Layer Deposition (ALD) process.

The material of the conductive material layer 601 is not specifically limited in the method for manufacturing the semiconductor structure provided by the present disclosure. As an example, the material of the conductive material layer 601 may include, but is not limited to, titanium nitride, titanium, tungsten silicide (Si)₂W), tungsten, and the like.

In an embodiment where the substrate 1 may include a peripheral region, the conductive material layer 601 formed in step S601 may further cover the upper surface of the cover dielectric layer 101 remaining in the peripheral region.

On the basis, in the process of forming the storage node contact structure 6 in the storage node contact hole 5, the step of etching back the conductive material layer 601 to remove the conductive material layer 601 on the upper surface of the remaining cover dielectric layer 101 may be further included.

Referring to fig. 12 (a) and 12 (b), in the embodiment where the bit line structure 2 includes the sidewall spacers 203, after the storage node contact structure 6 is formed in the storage node contact hole 5, the method for manufacturing the semiconductor structure may further include a step of removing the exposed sidewall spacers 203.

It should be understood that, although the steps in the flowcharts of fig. 1, 4, 7 and 9 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least some of the steps in fig. 1, 4, 7, and 9 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the steps or stages in other steps.

The present disclosure also provides a semiconductor structure according to some embodiments. The semiconductor structure can be prepared by adopting the preparation method in some embodiments.

With continued reference to fig. 12 (a) and 12 (b), in one embodiment, the semiconductor structure may include a substrate 1, a storage node contact hole 5, and a storage node contact structure 6.

Wherein, a substrate 1 is provided with a plurality of bit line structures 2 arranged at intervals; the bit line structure 2 includes a stacked structure; the stacked structure includes a bit line conductive layer 201 and a bit line dielectric layer 202 stacked in sequence from bottom to top. The storage node contact hole 5 is located between adjacent bit line structures 2. The storage node contact structure 6 is located within the storage node contact hole 5.

The storage node contact hole 5 in the above embodiment may be prepared by the following steps, for example:

forming an initial filling dielectric layer 3, wherein the initial filling dielectric layer 3 at least fills the gap between the adjacent bit line structures 2; after the initial filling dielectric layer 3 is formed, removing part of the initial filling dielectric layer 3 positioned between the adjacent bit line structures 2 to form a filling dielectric layer 4, wherein the height of the filling dielectric layer 4 is smaller than that of the bit line structures 2 in the direction vertical to the substrate 1; after the filling dielectric layer 4 is formed, the filling dielectric layer 4 and a part of the bit line dielectric layer 202 are removed to form a storage node contact hole 5 between the adjacent bit line structures 2.

In the semiconductor structure provided in the above embodiment, the storage node contact hole 5 is formed by removing a part of the initial filling dielectric layer 3 to form the filling dielectric layer 4 and then removing the filling dielectric layer 4 and a part of the bit line dielectric layer 202 by using the difference between the etching ratios of the initial filling dielectric layer 3 and the bit line dielectric layer 202, so that the depth-to-width ratio of the trench between adjacent bit line structures 2 for accommodating the storage node contact structure 6 is reduced, and the storage node contact structure 6 in the storage node contact hole 5 does not have a void, thereby avoiding the problem of electrical anomaly.

As an example, the substrate 1 in the semiconductor structure provided in the present disclosure may include any one or more of a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or the like.

As an example, the material of the bit line conductive layer 201 in the semiconductor structure provided by the present disclosure may include, but is not limited to, titanium (Ti) or tungsten (W). The bit line dielectric layer 202 may include, but is not limited to, a silicon nitride (SiN) layer.

As an example, the material of the storage node contact structure 6 in the semiconductor structure provided by the present disclosure may include, but is not limited to, titanium nitride, titanium, tungsten silicide (Si)₂W), tungsten, and the like.

Referring to fig. 12 (a) and fig. 12 (b), in an embodiment, the bit line structure 2 may further include a sidewall spacer 203, and the sidewall spacer 203 is located on a sidewall of the stacked structure.

Referring to fig. 12 (a) and 12 (b), in one embodiment, the substrate 1 may further include a buried word line 103 extending along the first direction. On this basis, the bit line structure 2 should extend along the second direction, and the second direction intersects with the first direction.

Referring to fig. 12 (a) and fig. 12 (b), in one embodiment, a shallow trench isolation structure 104 is formed in the substrate 1, and the shallow trench isolation structure 104 can isolate a plurality of active regions 105 arranged at intervals in the substrate 1.

With continued reference to fig. 12 (a) and fig. 12 (b), in one embodiment, the semiconductor structure may further include a bit line contact structure 106. The bit line contact structure 106 should be in contact with the active region 105; on this basis, the bit line conductive layer 201 of the bit line structure 2 is in contact with the bit line contact structure 106.

As an example, the bit line contact structure 106 in the semiconductor structure provided in the present disclosure may include, but is not limited to, any one or more of a polysilicon layer, a titanium nitride layer, and/or a tungsten layer.

With reference to fig. 12 (c), the substrate 1 includes an array region and a peripheral region located at the periphery of the array region. On this basis, the upper surface of the peripheral region may also be formed with a transistor 102.

As an example, the transistor 102 in the semiconductor structure provided in the present disclosure may include, but is not limited to, a MOS transistor.

In one embodiment, a capping dielectric layer 101 may be further formed in the peripheral region, and the transistor 102 is covered by the capping dielectric layer 101.

As an example, the material of the capping dielectric layer 101 in the semiconductor structure provided in the present disclosure may include, but is not limited to, a silicon nitride layer.

It should be noted that the methods for manufacturing the semiconductor structures in the embodiments of the present disclosure can be used to manufacture corresponding semiconductor structures, so that the technical features between the method embodiments and the structure embodiments can be replaced and supplemented without conflict, so as to enable those skilled in the art to learn the technical content of the present disclosure.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present disclosure, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present disclosure, and these changes and modifications are all within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.

Claims (15)

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming a plurality of bit line structures arranged at intervals on the substrate; the bit line structure comprises a stacked structure; the laminated structure comprises a bit line conducting layer and a bit line dielectric layer which are sequentially laminated from bottom to top;

forming an initial filling dielectric layer, wherein the initial filling dielectric layer at least fills a gap between the adjacent bit line structures;

removing part of the initial filling dielectric layer positioned between the adjacent bit line structures to form a filling dielectric layer; in the direction vertical to the substrate, the height of the filling dielectric layer is smaller than that of the bit line structure;

removing the filling dielectric layer and part of the bit line dielectric layer to form a storage node contact hole between adjacent bit line structures;

and forming a storage node contact structure in the storage node contact hole, wherein the storage node contact structure is filled in the storage node contact hole without a pore.

2. The method of claim 1, wherein said removing a portion of said initial fill dielectric layer comprises:

forming a patterned photoresist layer on the upper surfaces of the bit line structure and the initial filling dielectric layer;

etching and removing a part of the initial filling dielectric layer positioned between the adjacent bit line structures based on the patterned photoresist layer;

and removing the patterned photoresist layer.

3. The method of claim 1, wherein a bottom dielectric layer is further formed on the upper surface of the substrate between adjacent bitline structures;

the removing the filling dielectric layer and part of the bit line dielectric layer comprises the following steps:

removing the bit line dielectric layer higher than the upper surface of the filling dielectric layer;

removing the filling dielectric layer;

after the filling dielectric layer is removed, the preparation method of the semiconductor structure further comprises the following steps:

and removing the bottom dielectric layer to expose the substrate.

4. The method of claim 3, wherein the bit line structure further comprises a spacer;

the side wall is positioned on the side wall of the laminated structure;

and removing part of the side wall while removing part of the bit line dielectric layer.

5. The method as claimed in claim 4, wherein after forming the storage node contact structure in the storage node contact hole, the method further comprises:

and removing the exposed side wall.

6. The method as claimed in claim 1, wherein forming a storage node contact structure in the storage node contact hole comprises:

forming a conductive material layer; the conductive material layer fills the storage node contact hole and covers the bit line structure;

back-etching the conductive material layer to remove the conductive material layer outside the storage node contact hole and part of the conductive material layer in the storage node contact hole; the conductive material layer remained in the storage node contact hole is the storage node contact structure.

7. The method of claim 6, wherein the substrate comprises an array region and a peripheral region located at the periphery of the array region;

a covering dielectric layer is also formed in the peripheral area and covers the peripheral area;

the preparation method of the semiconductor structure further comprises the following steps of while removing part of the bit line dielectric layer:

and removing part of the covering dielectric layer to enable the upper surface of the remaining covering dielectric layer to be flush with the upper surface of the filling dielectric layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein the conductive material layer further covers an upper surface of the cover dielectric layer remaining in the peripheral region;

the forming of the storage node contact structure in the storage node contact hole includes:

and carrying out back etching on the conductive material layer to remove the conductive material layer on the upper surface of the reserved covering dielectric layer.

9. The method as claimed in claim 7, wherein a transistor is further formed on the upper surface of the peripheral region, and the cover dielectric layer covers the transistor.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein in the process of removing the portion of the initial filling dielectric layer located between the adjacent bit line structures, the thickness of the removed initial filling dielectric layer is 1/2-2/3 of the height of the bit line dielectric layer.

11. The method of claim 1, wherein before forming the plurality of spaced apart bitline structures on the substrate, the method further comprises:

forming embedded word lines in the substrate, the embedded word lines extending along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction.

12. The method of claim 11, wherein a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate;

after forming the embedded word lines in the substrate and before forming a plurality of bit line structures arranged at intervals on the substrate, the method for manufacturing a semiconductor structure further includes:

forming a bit line contact structure in the substrate, wherein the bit line contact structure is in contact with the active region; the bit line conductive layer of the bit line structure is in contact with the bit line contact structure.

13. A semiconductor structure, comprising:

the bit line structure comprises a substrate, a bit line structure and a bit line structure, wherein the substrate is provided with a plurality of bit line structures which are arranged at intervals; the bit line structure comprises a stacked structure; the laminated structure comprises a bit line conductive layer and a bit line dielectric layer which are sequentially laminated from bottom to top;

a storage node contact hole located between adjacent bit line structures;

a storage node contact structure located within the storage node contact hole;

the forming method of the storage node contact hole comprises the following steps:

forming an initial filling dielectric layer, wherein the initial filling dielectric layer at least fills the gap between the adjacent bit line structures;

removing part of the initial filling dielectric layer between the adjacent bit line structures to form a filling dielectric layer, wherein the height of the filling dielectric layer is smaller than that of the bit line structures in the direction perpendicular to the substrate;

and removing the filling dielectric layer and part of the bit line dielectric layer to form a storage node contact hole between adjacent bit line structures.

14. The semiconductor structure of claim 13, wherein the bit line structure further comprises a sidewall spacer, the sidewall spacer being located on a sidewall of the stacked structure;

the substrate is also provided with an embedded word line, and the embedded word line extends along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction;

a shallow trench isolation structure is formed in the substrate, and a plurality of active regions which are distributed at intervals are isolated in the substrate by the shallow trench isolation structure; the semiconductor structure further includes:

a bit line contact structure contacting the active region; the bit line conductive layer of the bit line structure is in contact with the bit line contact structure.

15. The semiconductor structure of claim 13, wherein the substrate comprises an array region and a peripheral region located at a periphery of the array region;

a transistor is further formed on the upper surface of the peripheral area, a covering dielectric layer is formed in the peripheral area, and the transistor is covered by the covering dielectric layer.

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