CN115274469A - Integrated fan-out package and method of forming the same - Google Patents

Integrated fan-out package and method of forming the same Download PDF

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Publication number
CN115274469A
CN115274469A CN202210868282.1A CN202210868282A CN115274469A CN 115274469 A CN115274469 A CN 115274469A CN 202210868282 A CN202210868282 A CN 202210868282A CN 115274469 A CN115274469 A CN 115274469A
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CN
China
Prior art keywords
die
redistribution structure
molding compound
redistribution
conductive
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CN202210868282.1A
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Chinese (zh)
Inventor
黄立贤
林岳霆
苏安治
叶名世
叶德强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/908,466 external-priority patent/US11177142B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN115274469A publication Critical patent/CN115274469A/en
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Abstract

The method includes attaching a first die and a second die to a carrier; forming a molding compound between the first die and the second die; and forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region; a second redistribution region; and a cutting region located between the first redistribution region and the second redistribution region. The method also includes forming a first opening and a second opening in the cutting region, the first opening and the second opening extending through the redistribution structure and exposing the molding compound; and separating the first die and the second die from a second side of the molding compound toward the first side of the molding compound by cutting through a portion of the molding compound aligned with the cutting region, the second side opposite the first side. Embodiments of the invention relate to an integrated fan-out package and a method of forming the same.

Description

Integrated fan-out package and method of forming the same
The present application is a divisional application entitled "integrated fanout package and method of forming the same," filed 2018, 07, month 02, having a patent application number 201810707996.8.
Technical Field
Embodiments of the invention relate to an integrated fan-out package and a method of forming the same.
Background
The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of individual electrical components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density comes from the continual reduction in minimum feature size, which allows more components to be integrated into a given area. With the recent increase in demand for smaller electronic devices, a need for smaller and more inventive packaging techniques for semiconductor dies has arisen.
An example of these packaging technologies is the Package On Package (POP) technology. In a PoP package, a top semiconductor package is stacked on top of a bottom semiconductor package to allow high integration and component density. Another example is multi-chip module (MCM) technology, in which a plurality of semiconductor dies are packaged in one semiconductor package to provide a semiconductor device with integrated functionality.
The high integration of advanced packaging technologies enables the production of semiconductor devices with enhanced functionality and smaller footprints, which is advantageous for small devices such as cell phones, tablet computers, and digital music players. Another advantage is that the length of the conductive path connecting the interoperable portions within the semiconductor package is reduced. This improves the electrical performance of the semiconductor device, since the shorter paths of the interconnects between the circuits result in faster signal propagation and reduced noise and crosstalk.
Disclosure of Invention
According to some embodiments of the present invention, there is provided a method of forming a semiconductor package, including: attaching the first die and the second die to a carrier; forming a molding compound between the first die and the second die; forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure comprising: a first redistribution region located over the first die; a second redistribution region located over the second die; and a cutting region located between the first redistribution region and the second redistribution region; forming first and second openings in the cut region, the first and second openings extending through the redistribution structure and exposing a first side of the molding compound; and separating the first die and the second die by dicing through portions of the molding compound aligned with the dicing regions, wherein the dicing is performed from a second side of the molding compound toward a first side of the molding compound, the second side being opposite the first side.
According to further embodiments of the present invention, there is also provided a method of forming a semiconductor package, including: forming a first conductive pillar and a second conductive pillar over a first side of a carrier; attaching the first die and the second die to a first side of the carrier, the first die and the second die being adjacent to the first conductive pillar and the second conductive pillar, respectively; forming a molding compound over the first side of the carrier, the molding compound extending along the sidewalls of the first die, the sidewalls of the second die, the sidewalls of the first conductive pillars, and the sidewalls of the second conductive pillars; forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region over the first die, a second redistribution region over the second die, and a dicing region between the first redistribution region and the second redistribution region; removing portions of the redistribution structure in the cut region to form a first opening proximate the first die and a second opening proximate the second die, the first opening being separated from the second opening by remaining portions of the redistribution structure in the cut region; debonding the carrier; electrically connecting the first semiconductor package to the first conductive pillars; electrically connecting the second semiconductor package to the second conductive pillars; and dicing with a blade through the molding compound from the back side of the first die, the dicing separating the first die from the second die.
According to still further embodiments of the present invention, there is also provided a semiconductor package including: a lower package, comprising: a die and conductive pillars proximate to the die, the die and the conductive pillars being located over a redistribution structure; and a molding compound over the redistribution structure, the molding compound interposed between the die and the conductive posts, the molding compound extending beyond a lateral extent of the redistribution structure.
Drawings
Various aspects of this invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1-6, 7A, 7B, and 8-11 illustrate various views of a semiconductor package at various stages of manufacture according to an embodiment.
Fig. 12 illustrates a flow diagram of a method for forming a semiconductor package, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Also, spatially relative terms such as "below 8230; below", "lower", "above", "upper" and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embodiments of the invention are discussed in the context of semiconductor packages and methods of forming semiconductor packages, and more particularly, in the context of integrated fan out (InFO) semiconductor packages. In some embodiments, a plurality of semiconductor dies and conductive pillars are formed over a carrier, and a molding compound is formed over the carrier and around the dies and around the conductive pillars. A redistribution structure is formed over the molding compound, die, and conductive pillars to form a semiconductor structure comprising a plurality of individual semiconductor packages to be diced in a subsequent process. According to some embodiments, no seal ring is formed in the redistribution structure around the die, which saves space for a seal ring and allows more individual semiconductor packages to be formed over the carrier, thereby improving the throughput of the manufacturing process. In some embodiments, to separate the individual semiconductor packages, a pre-cutting process is performed to form openings at a first side of the semiconductor structure (e.g., in the cut regions of the redistribution structure), followed by starting the cutting process from a second side of the semiconductor structure opposite the first side. The openings formed by the pre-cutting process may prevent or reduce delamination of the redistribution structure during the cutting process.
Fig. 1-6, 7A, 7B, and 8-11 illustrate various views (e.g., cross-sectional, top-down) of a package on package (PoP) semiconductor package 500 at various stages of fabrication, according to an embodiment. In particular, fig. 1-6, 7A, 7B, and 8 show various views of one or more bottom packages 1100 (e.g., 1100A, 1100B) of the PoP package, and fig. 9-11 show cross-sectional views of the PoP package after a top package 160 (e.g., 160A, 160B) is attached to the bottom package 1100.
Referring to fig. 1, a dielectric layer 110, which may be a buffer layer, is formed over a carrier 101. Conductive pillars 119 are formed over the dielectric layer 110.
Carrier 101 may be made of materials such as silicon, polymer composite, metal foil, ceramic, glass epoxy, beryllium oxide, tape, or other suitable material for structural support. In some embodiments, the dielectric layer 110 is made of a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; nitrides, such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. The dielectric layer 110 may be formed by a suitable deposition process such as spin coating, chemical Vapor Deposition (CVD), lamination, or the like, or combinations thereof.
In some embodiments, an adhesive layer (not shown) is deposited or laminated over the carrier 101 prior to forming the dielectric layer 110. The adhesive layer may be photosensitive and may be easily released from the carrier 101 by irradiating ultra-violet (UV) light on the carrier 101, for example, in a subsequent carrier debonding process. For example, the bond coat may be a light-to-heat conversion (LTHC) coating manufactured by 3M company or other supplier of st paul, minnesota.
Still referring to fig. 1, conductive pillars 119 are formed over dielectric layer 110. Conductive post 119 may be formed by: forming a seed layer over the dielectric layer 110; forming a patterned photoresist over the seed layer, wherein each opening in the patterned photoresist corresponds to a location of a conductive post 119 to be formed; filling the openings with a conductive material such as copper using, for example, electroplating or electroless plating; removing the photoresist using, for example, an ashing or stripping process; and removing portions of the seed layer on which the conductive pillars 119 are not formed. Other methods for forming conductive pillars 119 are possible and are all fully intended to be included within the scope of the present invention. In some embodiments, the dielectric layer 110 is omitted, and the conductive posts 119 are formed on an adhesion layer (e.g., LTHC coating) deposited or laminated over the carrier 101.
Next, in fig. 2, a semiconductor die 120 (which may also be referred to as a die or an Integrated Circuit (IC) die) is attached to the upper surface of the dielectric layer 110. An adhesive film 118, such as a Die Attach Film (DAF), may be used to attach die 120 to dielectric layer 110.
Prior to bonding to dielectric layer 110, die 120 may be processed according to applicable manufacturing processes to form an integrated circuit in die 120. For example, die 120 may include a semiconductor substrate and one or more overlying metallization layers, collectively shown as element 121. The semiconductor substrate may be, for example, doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. Devices (not shown) such as transistors, diodes, capacitors, resistors, and the like may be formed in and/or on a semiconductor substrate and may be interconnected by metallization layers, such as metallization patterns in one or more dielectric layers over the semiconductor substrate, to form an integrated circuit.
Die 120 also includes pads 126, such as aluminum pads, that make external connections. The pads 126 are located at what may be referred to as the active side or front side of the die 120. A passivation film 127 is formed at the front side of the die 120 and on portions of the pads 126. An opening is formed extending through the passivation film 127 to the pad 126. Die connections 128, such as conductive pillars (e.g., comprising a metal such as copper), extend into openings through the passivation film 127 and are mechanically and electrically connected to respective pads 126. Die attach 128 may be formed by, for example, plating or the like. Die attach 128 electrically connects the integrated circuits of die 120.
A dielectric material 129 is formed at the active side of the die 120, such as on the passivation film 127 and/or the die attach 128. Dielectric material 129 laterally encapsulates die attach 128, and dielectric material 129 is laterally coterminous with die 120. The dielectric material 129 may be a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; nitrides such as silicon nitride and the like; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like; or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like.
Next, in fig. 3, a molding compound 130 is formed over dielectric layer 110, around die 120, and around conductive pillars 119. For example, the molding compound 130 may include an epoxy, an organic polymer, a polymer with or without added silica or glass based fillers, or other materials. In some embodiments, the molding compound 130 comprises a Liquid Molding Compound (LMC) that is a gel-type liquid when applied. When applied, the molding compound 130 may also comprise a liquid or a solid. Optionally, the molding compound 130 may include other insulating and/or sealing materials. In some embodiments, the molding compound 130 is applied using a wafer level molding process. The molding compound 130 may be molded using, for example, compression molding, transfer molding, or other methods.
Next, in some embodiments, a curing process is used to cure the molding compound 130. The curing process may include heating the molding compound 130 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process may also include an Ultraviolet (UV) exposure process, an Infrared (IR) energy exposure process, a combination thereof, or a combination thereof with a heating process. Alternatively, other methods may be used to cure the molding compound 130. In some embodiments, a curing process is not included.
A planarization process, such as Chemical and Mechanical Polishing (CMP), may optionally be performed to remove excess portions of the molding compound 130 over the front side of the die 120. In some embodiments, after the planarization process, the molding compound 130, the conductive pillars 119, and the die attach 128 have coplanar upper surfaces.
Next, referring to fig. 4, a redistribution structure 140 (which may also be referred to as a front side redistribution structure) is formed over the molding compound 130, conductive pillars 119, and die 120. Redistribution structure 140 includes one or more layers of conductive features (e.g., conductive lines 143, vias 145) formed in one or more dielectric layers (e.g., 142, 144, 146, and 148).
In some embodiments, one or more of the dielectric layers (e.g., 142, 144, 146, and 148) is made of a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; nitrides, such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. The one or more dielectric layers may be formed by a suitable deposition process such as spin coating, chemical Vapor Deposition (CVD), lamination, or the like, or combinations thereof.
In some embodiments, the conductive components of the redistribution structure 140 include conductive lines (e.g., 143) and conductive vias (e.g., 145) formed from a suitable conductive material, such as copper, titanium, tungsten, aluminum, and the like. In some embodiments, the conductive features are formed by forming openings in the dielectric layer of the redistribution structure 140 to expose the underlying conductive features, forming a seed layer (not shown) over the dielectric layer and in the openings, forming a patterned photoresist (not shown) having a designed pattern over the seed layer, plating (e.g., electroplating or electroless plating) a conductive material in the designed pattern and over the seed layer, and removing portions of the photoresist and seed layer on which the conductive material is not formed. Other methods of forming the redistribution structure 140 are possible and are all fully intended to be included within the scope of the present invention.
The number of dielectric layers and the number of layers of conductive features in the redistribution structure 140 of fig. 4 are merely non-limiting examples. Other numbers of dielectric layers and layers of conductive features are also possible and are all fully intended to be included within the scope of the present invention.
Fig. 4 also shows an Under Bump Metal (UBM) structure 147 formed over the redistribution structure 140 and electrically connected to the redistribution structure 140. To form the UBM structure 147, openings are formed in the uppermost dielectric layer (e.g., 142) of the redistribution structure 140 to expose conductive components (e.g., copper lines or copper pads) of the redistribution structure 140. After forming the openings, UBM structures 147 may be formed in electrical contact with the exposed conductive features. In an embodiment, UBM structure 147 includes three layers of conductive material, such as a layer of titanium, copper, and nickel. However, there are many suitable materials and layer arrangements suitable for forming UBM structure 147, such as an arrangement of chromium/chromium-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold. Any suitable material or layers of materials that may be used for UBM structure 147 are fully intended to be included within the scope of the present invention.
UBM structure 147 may be formed by: forming a seed layer over the uppermost dielectric layer (e.g., 142) and along an interior of the opening in the uppermost dielectric layer; forming a patterned masking layer (e.g., photoresist) over the seed layer; forming (e.g., by plating) a conductive material in the openings of the patterned mask layer and over the seed layer; the mask layer is removed and the portions of the seed layer on which the conductive material is not formed are removed. Other methods for forming UBM structure 147 are possible and are all fully intended to be included within the scope of the present invention. The upper surface of UBM structure 147 in fig. 4 is shown as planar merely as an example, and the upper surface of UBM structure 147 may not be planar. For example, portions (e.g., peripheral portions) of each UBM structure 147 may be formed over an uppermost dielectric layer (e.g., 142), and other portions (e.g., central portions) of each UBM structure 147 may be conformally formed along sidewalls of the uppermost dielectric layer exposed by the corresponding opening, as will be understood by those skilled in the art.
Next, in fig. 5, a connection 155 is formed over UBM structure 147, in accordance with some embodiments. Connections 155 may be solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro-bumps, bumps formed by Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), combinations thereof (e.g., metal posts with attached solder balls), and the like. The connection 155 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, for example, connection 155 comprises a eutectic material and may comprise a solder bump or ball. The solder material may be, for example, lead-based solders and lead-free solders, such as the Pb-Sn component used for lead-based solders; a lead-free solder comprising InSb; tin, silver and copper (SAC) components; and other eutectic materials that have a common melting point and form conductive solder connections in electronic applications. For example, for lead-free solders, SAC solders of different compositions may be used, such as SAC 105 (Sn 98.5%, ag 1.0%, cu 0.5%), SAC 305, and SAC 405. Lead-free connections, such as solder balls, are also formed from SnCu compounds that do not use silver (Ag). Alternatively, the lead-free solder connections may include tin and silver, sn-Ag, without the use of copper. The connectors 155 may form a grid, such as a Ball Grid Array (BGA). In some embodiments, a reflow process may be performed, giving in some embodiments a partially spherical shaped connection 155. Alternatively, the connection 155 may include other shapes. For example, the connection 155 may also include a non-spherical conductive connection.
In some embodiments, the connection 155 comprises a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like, with or without solder material thereon. The metal posts may be solderless and have substantially vertical sidewalls or tapered sidewalls.
Fig. 5 further shows an electronic device 171, such as an Integrated Passive Device (IPD), electrically connected to redistribution structure 140 through, for example, UBM structure 147. Conductive contacts 173, such as solder contacts, may be formed between the electronic device 171 and the redistribution structure 140. The conductive contact 173 may include the same material (e.g., solder) as the connection 155. In addition, an underfill material 175 may be formed in the gap between the electronic device 171 and the redistribution structure 140.
For illustrative purposes, the example of fig. 5 shows one semiconductor package 1100 formed over a carrier 101. Those skilled in the art will appreciate that tens, hundreds, or even more semiconductor packages (e.g., 1100) may be formed over carrier 101 in the same process steps as shown in fig. 1-5. Fig. 6-10 illustrate further processing of the semiconductor package 1100 of fig. 5 using, for example, the formation of two semiconductor packages (e.g., 1100A and 1100B) over carrier 101, it being understood that more than two semiconductor packages may be formed over carrier 101.
Fig. 6 illustrates a semiconductor structure including a semiconductor package 1100A and a semiconductor package 1100B formed in regions 100 and 200 of the semiconductor structure, respectively. In the illustrated embodiment, each of the semiconductor packages 1100A and 1100B is the same as the semiconductor package 1100 illustrated in fig. 5.
As shown in fig. 6, redistribution structure 140' is formed continuously over molding compound 130 and over all of the dies 120. The portions of redistribution structure 140' in region 100 are located over (e.g., directly over) and electrically connected to die 120/conductive pillars 119 in region 100, and correspond to a redistribution structure such as redistribution structure 140 shown in fig. 5. Similarly, the portions of redistribution structure 140' in region 200 are located over (e.g., directly over) and electrically connected to die 120/conductive pillars 119 in region 200, and correspond to a redistribution structure such as redistribution structure 140 shown in fig. 5.
As shown in fig. 6, the redistribution structure 140' also includes portions in a region 300 (which may also be referred to as a cut region) between the regions 100 and 200. The width of the cutting region 300 may be between about 40 μm and about 260 μm, such as about 40 μm, although other dimensions are possible. In some embodiments, the portion of the redistribution structure 140' in the region 300 includes only dielectric layers (e.g., see 142, 144, 146, 148 in fig. 4) and no conductive components (e.g., wires, vias) are present. Furthermore, in the illustrated embodiment, no sealing rings are formed in the redistribution structure 140'.
The seal rings typically include dummy conductive features such as metal lines and metal vias formed in redistribution structures (e.g., 140') around the perimeter of each semiconductor package (e.g., 1100A and 1100B). In other words, each seal ring has a ring shape (e.g., a rectangular shape) and surrounds the corresponding semiconductor package (e.g., 1100A, 1100B) in plan view. The metal lines and metal vias of the seal ring may be formed in the same process step and using the same materials as the conductive lines (see, e.g., 143 in fig. 4) and conductive vias (see, e.g., 145 in fig. 4) of the redistribution structure 140'. For example, the metal lines and metal vias of the seal ring may be formed in the same dielectric layer as the conductive lines and conductive vias forming the redistribution structure 140', except that the metal lines and metal vias of the seal ring are electrically isolated. The seal ring is constructed to protect the redistribution structure, e.g., semiconductor package, from cracking and/or delamination during subsequent dicing processes. For example, when a blade of a dicing saw cuts into the cutting region 300 between two adjacent seal rings, the cracking in the redistribution structure 140' caused by the blade may be impeded by the seal rings and damage to the semiconductor package may be avoided. Similarly, delamination of the redistribution structure 140 (which may occur due to dicing) may also be prevented or reduced by the seal ring.
However, the seal ring occupies space in the semiconductor structure. For example, the width of the seal ring may be about 40 μm, and a region of about 80 μm total width between two semiconductor packages (e.g., 1100A and 1100B) is used to form the seal ring. The present invention frees up more space on the carrier 101 to form semiconductor packages by not forming any seal rings around the semiconductor packages (e.g., 1100A and 1100B) in the redistribution structure 140'. For example, by not forming a seal ring, about 2% or more of the semiconductor packages can be formed on the carrier, thereby achieving higher throughput. Further, the pre-cutting process and the cutting process disclosed below avoid or reduce cracking/delamination in the redistribution structure 140' without the use of a seal ring.
Referring now to fig. 7A, a pre-cut process is performed to form openings 311/313 in the redistribution structure 140' in the cut regions 300. As illustrated in fig. 7A, an opening 311 is formed near the semiconductor package 1100A and an opening 313 is formed near the semiconductor package 1100B. The width W1 of opening 311 is between about 20 μm and about 80 μm, and the width W1' of opening 313 is between about 20 μm and about 80 μm. In some embodiments, width W1 is substantially the same as width W1'. In other embodiments, width W1 is different from width W1'. The width W2 measured between the sidewall 311E of the opening 311 and the sidewall 313E of the opening 313 is between about 20 μm and about 80 μm, wherein the sidewall 311E is the sidewall of the opening 311 closest to the semiconductor package 1100A, and in some embodiments, the sidewall 313E is the sidewall of the opening 313 closest to the semiconductor package 1100B. The rectangular cross-sections of the openings 311 and 313 shown in fig. 7A are merely non-limiting examples. Other shapes for the cross-section of the openings 311 and 313 are possible and are all fully manufactured within the scope of the present invention. For example, the bottoms of the openings 311 and 313 may have an irregular shape depending on, for example, a method for forming the openings.
As shown in fig. 7A, portions of the dielectric layer of the redistribution structure 140' in the cut region 300 are removed to form openings 311/313. In the example of fig. 7A, the openings 311 and 313 are physically separated from each other in the cut region 300 by the remaining portion 140R of the dielectric layer of the redistribution structure 140. In some embodiments, the width W4 of the remaining portion 140R is between about 140 μm and 200 μm. In addition, the portion of the molding compound 130 in the cutting region 300 is also removed to form an opening. Thus, in the illustrated embodiment, the openings 311 and 313 pass through the redistribution structure 140 and extend into the molding compound 130. For example, the openings 311 and 313 may extend into the molding compound 130 to a depth in a range between about 20 μm and 100 μm.
In an exemplary embodiment, two laser beams are usedOpenings 311 and 313 are formed. In other words, the openings 311 and 313 are formed in parallel using two laser beams, instead of forming the openings 311 and 313 sequentially, to increase the throughput of production, but it is possible to form the openings 311 and 313 using one laser beam, for example, sequentially. In some embodiments, the laser used may be CO2Laser, UV laser or green laser. Other types of lasers, such as fiber lasers and Yttrium Aluminum Garnet (YAG) lasers, are also contemplated within the scope of the present invention. In some embodiments, the average output power of the laser is in a range between about 0.5 watts and about 8 watts, although other output power ranges are possible and are all fully intended to be within the scope of the present invention. The average output power of the laser is determined by various factors such as the material of the dielectric layer of the redistribution structure 140', the depth of the openings 311/313, and the desired processing speed.
In fig. 7A, two openings 311/313 are formed by a pre-cut process, wherein each opening provides protection against cracking and/or delamination of adjacent semiconductor packages during a subsequent cutting process, as will be discussed in more detail below with reference to fig. 10. Specifically, the opening 311 protects the redistribution structure of the semiconductor package 1100A, and the opening 313 protects the redistribution structure of the semiconductor package 1100B. Forming more than two openings between two adjacent semiconductor packages may not be necessary as the additional openings, if formed, do not provide more additional protection against cracking and/or delamination of the redistribution structure 140' during dicing. On the other hand, forming only one opening (e.g., forming only 311 or forming only 313) may not provide protection for one of two adjacent semiconductor packages. While an opening having a wide width (e.g., an opening having a width extending from 311E to 313E) may be formed between two adjacent semiconductor packages to provide protection against cracking and/or delamination, forming such a wide opening may require a significantly longer time, and/or may require a higher output power laser. Thus, the two openings (e.g., 311 and 313) formed between two adjacent semiconductor packages by the pre-cut process in combination with the cutting process discussed below with reference to fig. 10 provides an efficient (e.g., shorter manufacturing time and higher throughput) and easily implemented manufacturing process that does not require a sealing ring, yet provides protection against cracking and delamination.
Fig. 7B illustrates a top view of the semiconductor structure of fig. 7A in some embodiments. In addition to semiconductor packages 1100A and 1100B, additional semiconductor packages (e.g., 1100C, 1100D, 1100E, and 1100F) formed on the carrier 101 are also shown in fig. 7B. For simplicity, not all details of the semiconductor package are shown in fig. 7B. As shown in fig. 7B, openings (e.g., 311, 313, 311', and 313') are formed in the dicing regions between the adjacent semiconductor packages through a pre-cutting process. In the top view of fig. 7B, each pair of openings (e.g., 311 plus 313) between two adjacent semiconductor packages (e.g., 1100A and 1100B) may form two parallel trenches. The pre-cut process may form two parallel trenches along each side (e.g., sidewall) of the corresponding semiconductor package. In other words, in a top view, each semiconductor package may be surrounded by, for example, four pairs of openings, wherein each side of the semiconductor package has a pair of openings (e.g., two parallel trenches) extending along a side of the semiconductor package.
Next, in fig. 8, the semiconductor structure shown in fig. 7A is flipped over and external connections 155 are attached to a tape 159 (e.g., dicing tape) supported by a frame 157. Next, the carrier 101 is debonded from the dielectric layer 110 by a suitable process such as etching, grinding, or mechanical debonding. In embodiments where an adhesion layer (e.g., LTHC film) is formed between the carrier 101 and the dielectric layer 110, the carrier 101 is debonded by exposing the carrier 101 to laser or UV light. The laser or UV light destroys the chemical bond of the adhesive layer bonded to the carrier 101, and thereafter the carrier 101 can be easily detached. The adhesive layer (if formed) may be removed by a carrier de-bonding process. The residues of the adhesive layer, if any, may be removed by a cleaning process performed after the carrier debonding process.
After debonding carrier 101, openings 116 are formed in dielectric layer 110 to expose conductive pillars 119. To form the opening 116, a laser drilling process, an etching process, or the like may be used. In some embodiments, the etch process is a plasma etch process. Although not shown, solder paste may be formed in the opening 116 using, for example, a solder paste printing process in preparation for attaching the top package (see fig. 9).
In embodiments where the dielectric layer 110 is omitted and the conductive pillars 119 are formed over an adhesion layer (e.g., LTHC coating) deposited or laminated over the carrier 101, the conductive pillars 119 may be exposed at the upper surface of the molding compound 130 after the carrier de-bonding process. Accordingly, a drilling process or an etching process for exposing the conductive pillars 119 may be omitted. Fig. 8-11 illustrate an embodiment of forming the dielectric layer 110. One skilled in the art would be able to modify the processes shown in fig. 8-11 to an embodiment for omitting dielectric layer 110 after reading the present disclosure.
Next, referring to fig. 9, semiconductor packages 160A and 160B (also referred to as top packages), such as memory packages, are attached to semiconductor packages 1100A and 1100B (also referred to as bottom packages), respectively, to form semiconductor packages 500A and 500B in fig. 9, thereby forming a plurality of semiconductor packages 500 (e.g., 500A, 500B) having a package on package (PoP) structure.
As shown in fig. 9, each semiconductor package 160 (e.g., 160A, 160B) has a substrate 161 and one or more semiconductor die 162 (e.g., memory die) attached to an upper surface of the substrate 161. In some embodiments, substrate 161 comprises silicon, gallium arsenide, silicon-on-insulator ("SOI"), or other similar materials. In some embodiments, substrate 161 is a multilayer circuit board. In some embodiments, substrate 161 comprises Bismaleimide Triazine (BT) resin, FR-4 (a composite of woven fiberglass cloth and a flame retardant epoxy adhesive), ceramic, glass, plastic, tape, film, or other support material. The substrate 161 may include conductive features (e.g., conductive lines and vias, not shown) formed in/on the substrate 161. As shown in fig. 9, the substrate 161 has conductive pads 163 formed on the upper and lower surfaces of the substrate 161, the conductive pads 163 being electrically connected to the conductive members of the substrate 161. One or more semiconductor die 162 are electrically connected to conductive pads 163 through, for example, bond wires 167. A molding compound 165, which may include an epoxy, organic polymer, etc., is formed over substrate 161 and around semiconductor die 162. In some embodiments, the molding compound 165 is coterminous with the substrate 161, as shown in fig. 8.
In some embodiments, a reflow process is performed to electrically and mechanically connect the conductive pads 163 of the semiconductor package 160 to the conductive pillars 119 through the conductive contacts 168. In some embodiments, the conductive joints 168 comprise solder regions, conductive pillars (e.g., copper pillars having solder regions on at least the end faces of the copper pillars), or any other suitable material.
After the reflow process, a baking process may be performed. The baking process may remove moisture from the semiconductor structure. Next, an underfill material 169 is formed in the gap between the top package 160 (e.g., 160A, 160B) and the corresponding bottom package 1100 (e.g., 1100A, 1100B). The underfill material 169 may be dispensed in the gap between the top package 160 and the bottom package 1100 using, for example, a needle or jet dispenser. A curing process may be performed to cure the underfill material 169. Although not shown, the underfill material 169 may extend along sidewalls of the top package 160.
Next, in fig. 10, a dicing process is performed to separate the PoP packages 500 (e.g., 500A, 500B) into a plurality of individual PoP packages. In an exemplary embodiment, the PoP packages are cut using a blade 315 of width W3. In some embodiments, width W3 is less than width W2 measured between sidewall 311E of opening 311 and sidewall 313E of opening 313. In the illustrated embodiment, blade 315 is located in a central region between sidewall 311E and sidewall 313E, and therefore does not overlap or contact sidewall 311E/313E during the cutting process. In other words, blade 315 is laterally positioned between sidewall 311E and sidewall 313E. In some embodiments, the width W3 of the blade 315 is wider than the width W4 of the remaining portion 140R of the redistribution structure 140' disposed between the openings 311 and 313. This may allow blade 315 to remove the remaining portion 140R in one cut to reduce the processing time of the cutting process. For example, the remaining portion 140R of the redistribution structure 140 'may be located laterally between opposing vertical sidewalls of the blade 315 such that the remaining portion 140R is removed in one cut when the blade 315 cuts down toward the redistribution structure 140'.
As shown in fig. 10, a blade 315 cuts into the dicing area 300 from a side of the semiconductor package 1100 opposite the opening 311/313. In other words, blade 315 begins to cut into the semiconductor structure shown in fig. 10 from the upper surface of the bottom package near the backside of die 120. As the blade 315 travels toward the redistribution structure 140', the blade 315 does not contact the redistribution structure 140' because the openings 311/313 isolate the blade 315 from the redistribution structure 140', except for the remainder 140R of the redistribution structure 140'. Thus, cracking and/or delamination of the redistribution structure 140' is avoided or reduced.
Although not shown, the pre-cutting process and the cutting process shown in fig. 7A to 10 may be performed in other cutting regions, for example, cutting regions between the PoP packages 500A/500B and other adjacent PoP packages (not shown). After the dicing process is completed, a plurality of individual PoP packages, such as the PoP package 500 shown in fig. 11, are formed.
As shown in fig. 11, the individual PoP packages 500 have redistribution structures 140 in which the die 120 and conductive pillars 119 are electrically connected to the upper surface of the redistribution structures 140. A molding compound 130 is formed over the redistribution structure 140 and around the die 120 and around the conductive pillars 119. In the example of fig. 11, the molding compound 130 extends beyond the lateral extent of the redistribution structure 140. In other words, the molding compound 130 is wider than (and thus, not co-terminal with) the redistribution structure 140. For example, the molding compound 130 may extend beyond the boundary (e.g., sidewall) width W5 of the redistribution structure 140, and the width W5 may range from about 1 μm to about 810 μm. This is because in some embodiments, the width W3 of blade 315 is less than the width W2 between sidewall 311E and sidewall 313E.
As shown in fig. 11, an upper portion of the molding compound 130 (e.g., the portion distal from the redistribution structure 140) has sidewalls 130S1 that extend beyond the lateral extent of the redistribution structure 140. Further, a lower portion of the molding compound 130 (e.g., the portion in physical contact with the redistribution structure 140) may have sidewalls 130S2 aligned with the sidewalls of the redistribution structure 140, e.g., the lower portion of the molding compound 130 may have the same width as the redistribution structure 140.
Still referring to fig. 11, the upper portion of the molding compound 130 that extends beyond the lateral extent of the redistribution structure 140 has a height H1, the height H1 being less than the height H2 of the portion of the molding compound 130 disposed within the lateral extent of the redistribution structure 140. The openings 311/313 may extend into the molding compound 130 (see, e.g., FIG. 7A). This means that in some embodiments, the portion of the molding compound 130 in the cutting area 300 is removed, such that the height H1 of the molding compound 130 disposed at the upper portion beyond the boundary (e.g., sidewalls) of the redistribution structure 140 is smaller. In fig. 11, the lower surface 130L of the upper portion of the molding compound 130 is shown as a planar surface. This is merely an example. As described above, the lower surface 130L may have other shapes (e.g., irregular surfaces) depending on the process for forming the openings 311/313.
Variations of the disclosed embodiments are possible and are all intended to be fully included within the scope of the invention. For example, the number of dies 120 in each PoP package, the number and/or location of conductive pillars 119 in each PoP package may be modified. For another example, the dielectric layer 110 may be completely removed from the PoP package 500. As another example, the amount and/or shape of the underfill material 169 may be modified. For example, the underfill material 169 may be a continuous volume of dielectric material that fills the gap between the top package and the bottom package and extends continuously from the first conductive contact 168 to the other conductive contact 168. Optionally, the underfill material 169 may include multiple portions that are physically separated from one another, wherein each portion of the underfill material 169 surrounds a respective conductive contact 168.
Embodiments may achieve a number of advantages. By omitting the sealing rings in the redistribution structure, more space is available for forming the semiconductor package, thereby achieving higher throughput. The disclosed pre-cutting and cutting processes avoid or reduce cracking/delamination without the use of sealing rings, thereby improving productivity without the problems associated with cracking and delamination.
Fig. 12 illustrates a flow chart of a method 3000 of fabricating a semiconductor device according to some embodiments. It should be understood that the embodiment method shown in FIG. 12 is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps shown in FIG. 12 may be added, removed, replaced, rearranged, and repeated.
Referring to fig. 12, in step 3010, the first die and the second die are attached to a carrier. In step 3020, a molding compound is formed between the first die and the second die. In step 3030, a redistribution structure is formed over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region over the first die; a second redistribution region located over the second die; and a cutting region located between the first redistribution region and the second redistribution region. In step 3040, first and second openings are formed in the cut region, the first and second openings extending through the redistribution structure and exposing a first side of the molding compound. In step 3050, the first die and the second die are separated by dicing through portions of the molding compound aligned with the dicing regions, wherein the dicing is performed from a second side of the molding compound toward a first side of the molding compound, the second side being opposite the first side.
In an embodiment, a method includes attaching a first die and a second die to a carrier; forming a molding compound between the first die and the second die; and forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region located over the first die; a second redistribution region located over the second die; and a cutting region located between the first redistribution region and the second redistribution region. The method also includes forming first and second openings in the dicing region, the first and second openings extending through the redistribution structure and exposing a first side of the molding compound; and separating the first die and the second die by cutting through a portion of the molding compound aligned with the cut region, wherein the cutting is performed from a second side of the molding compound toward the first side of the molding compound, the second side being opposite the first side. In an embodiment, the cutting area is free of conductive features. In an embodiment, the first opening and the second opening are physically separated from each other. In an embodiment, the first opening and the second opening extend into the molding compound. In an embodiment, forming the first and second openings includes removing portions of the redistribution structure in the cut region using a first laser beam and a second laser beam, respectively, to form the first and second openings. In an embodiment, the first laser beam and the second laser beam are applied to the cutting area simultaneously. In an embodiment, the cutting is performed using a blade. In an embodiment, the first opening is laterally between the first die and the second opening, wherein a first width of the blade is less than a second width between a first sidewall of the first opening closest to the first die and a second sidewall of the second opening closest to the second die. In an embodiment, the blade is located laterally between the first sidewall of the first opening and the second sidewall of the second opening during cutting. In an embodiment, the redistribution structure is free of sealing rings. In an embodiment, the method further comprises: prior to separating the first die and the second die: forming a first conductive pillar in the molding compound adjacent to the first die; forming a second conductive pillar in the molding compound adjacent to the second die; and attaching the first and second packages to the first and second conductive pillars, respectively.
In an embodiment, a method comprises: forming a first conductive pillar and a second conductive pillar over a first side of a carrier; attaching a first die and a second die to the first side of the carrier, the first die and the second die being adjacent to the first conductive pillar and the second conductive pillar, respectively; forming a molding compound over the first side of the carrier, the molding compound extending along the sidewalls of the first die, the sidewalls of the second die, the sidewalls of the first conductive pillars, and the sidewalls of the second conductive pillars; forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region over the first die, a second redistribution region over the second die, and a cutting region between the first redistribution region and the second redistribution region; removing portions of the redistribution structure in the cut region to form a first opening proximate to the first die and a second opening proximate to the second die, the first opening being separated from the second opening by remaining portions of the redistribution structure in the cut region; debonding the carrier; electrically connecting the first semiconductor package to the first conductive pillar; electrically connecting the second semiconductor package to the second conductive pillars; and dicing, using a blade, through the molding compound from the back side of the first die, the dicing separating the first die from the second die. In an embodiment, removing the portion of the redistribution structure in the dicing region also removes a portion of the molding compound such that the first opening and the second opening extend into the molding compound. In an embodiment, removing the portion of the redistribution structure in the cut region is performed using a laser. In an embodiment, the blade has a first width, wherein a first sidewall of the first opening closest to the first die is spaced apart from a second sidewall of the second opening closest to the second die by a second width, and wherein the first width is less than the second width. In an embodiment, during cutting, the blade is laterally positioned between and does not contact the first sidewall of the first opening and the second sidewall of the second opening. In an embodiment, the redistribution structure is free of sealing rings.
In an embodiment, a semiconductor package includes a lower package including a die and conductive pillars proximate to the die, the die and conductive pillars being located over a redistribution structure; and a molding compound disposed over the redistribution structure, the molding compound interposed between the die and the conductive posts, the molding compound extending beyond a lateral extent of the redistribution structure. In an embodiment, a first portion of the molding compound that extends beyond the lateral extent of the redistribution structure has a first height and a second portion of the molding compound that contacts the die has a second height, wherein the first height is less than the second height. In an embodiment, the semiconductor package further includes a top package electrically connected to the conductive pillars.
According to some embodiments of the present invention, there is provided a method of forming a semiconductor package, including: attaching the first die and the second die to a carrier; forming a molding compound between the first die and the second die; forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure comprising: a first redistribution region located over the first die; a second redistribution region located over the second die; and a cutting region located between the first redistribution region and the second redistribution region; forming first and second openings in the cut region, the first and second openings extending through the redistribution structure and exposing a first side of the molding compound; and separating the first die and the second die by cutting through a portion of the molding compound aligned with the cut region, wherein the cutting is performed from a second side of the molding compound toward a first side of the molding compound, the second side being opposite the first side.
In the above method, the cutting area is free of conductive members.
In the above method, the first opening and the second opening are physically separated from each other.
In the above method, the first opening and the second opening extend into the molding compound.
In the above method, forming the first opening and the second opening includes removing portions of the redistribution structure in the cutting region using a first laser beam and a second laser beam to form the first opening and the second opening, respectively.
In the above method, the first laser beam and the second laser beam are simultaneously applied to the cutting region.
In the above method, the cutting is performed using the blade.
In the above method, the first opening is located laterally between the first die and the second opening, wherein a first width of the blade is less than a second width between a first sidewall of the first opening closest to the first die and a second sidewall of the second opening closest to the second die.
In the above method, the blade is located laterally between a first sidewall of the first opening and a second sidewall of the second opening during the cutting.
In the above method, the redistribution structure is free of sealing rings.
In the above method, further comprising, prior to separating the first die and the second die: forming a first conductive pillar in the molding compound adjacent to the first die; forming a second conductive pillar in the molding compound adjacent to the second die; and attaching the first and second packages to the first and second conductive pillars, respectively.
According to further embodiments of the present invention, there is also provided a method of forming a semiconductor package, including: forming a first conductive pillar and a second conductive pillar over a first side of a carrier; attaching the first die and the second die to a first side of the carrier, the first die and the second die being adjacent to the first conductive pillar and the second conductive pillar, respectively; forming a molding compound over the first side of the carrier, the molding compound extending along the sidewalls of the first die, the sidewalls of the second die, the sidewalls of the first conductive pillars, and the sidewalls of the second conductive pillars; forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region over the first die, a second redistribution region over the second die, and a cut region between the first redistribution region and the second redistribution region; removing portions of the redistribution structure in the cut region to form a first opening proximate the first die and a second opening proximate the second die, the first opening being separated from the second opening by remaining portions of the redistribution structure in the cut region; debonding the carrier; electrically connecting the first semiconductor package to the first conductive pillars; electrically connecting the second semiconductor package to the second conductive pillars; and dicing with a blade through the molding compound from the back side of the first die, the dicing separating the first die from the second die.
In the above method, removing the portion of the redistribution structure in the cut region also removes a portion of the molding compound such that the first and second openings extend into the molding compound.
In the above method, removing the portion of the redistribution structure in the cut region is performed using a laser.
In the above method, the blade has a first width, wherein a first sidewall of the first opening closest to the first die is spaced apart from a second sidewall of the second opening closest to the second die by a second width, and wherein the first width is less than the second width.
In the above method, during the cutting, the blade is laterally positioned between and does not contact the first sidewall of the first opening and the second sidewall of the second opening.
In the above method, the redistribution structure is free of sealing rings.
According to still further embodiments of the present invention, there is also provided a semiconductor package including: a lower package, comprising: a die and conductive pillars proximate to the die, the die and the conductive pillars being located over a redistribution structure; and a molding compound over the redistribution structure, the molding compound interposed between the die and the conductive posts, the molding compound extending beyond a lateral extent of the redistribution structure.
In the above semiconductor package, a first portion of the molding compound extending beyond the lateral extent of the redistribution structure has a first height and a second portion of the molding compound contacting the die has a second height, wherein the first height is less than the second height.
In the above semiconductor package, a top package electrically connected to the conductive pillar is further included.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced by oneself. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of forming a semiconductor package, comprising:
attaching the first die and the second die to a carrier;
forming a first conductive pillar over the carrier and adjacent to the first die;
forming a molding compound between the first and second die and the first conductive pillar;
forming a redistribution structure over the first die, the second die, the first conductive pillars, and the molding compound, the redistribution structure comprising:
a first redistribution region located over the first die;
a second redistribution region over the second die; and
a cutting region located between the first redistribution region and the second redistribution region;
an Under Bump Metal (UBM) structure formed over the redistribution structure and electrically connected to the redistribution structure;
forming a connector and an electronic device over the under bump metal structure;
forming first and second openings in the cut region, the first and second openings extending through the redistribution structure and exposing a first side of the molding compound;
attaching the redistribution structure to a tape after forming the first and second openings; and
separating the first die and the second die by cutting through a portion of the molding compound aligned with the cutting region using a blade, wherein the cutting is performed from a second side of the molding compound toward a first side of the molding compound, the second side being opposite the first side, wherein the blade does not cut into the tape during the cutting,
wherein, after separating the first die and the second die, the first conductive pillar is a conductive pillar farthest from the first die, a first connection piece corresponding to the position of the first conductive pillar and closest to the electronic device is provided in the connection piece, and in the cross-sectional view, the first conductive pillar and the first connection piece are not physically connected through the conductive wire and the metal through hole in the redistribution structure.
2. The method of claim 1, wherein the cut region is free of conductive features.
3. The method of claim 1, wherein the first opening and the second opening are physically separated from each other.
4. The method of claim 1, wherein the first opening and the second opening extend into the molding compound.
5. The method of claim 1, wherein forming the first and second openings comprises removing portions of the redistribution structure in the cut region using first and second laser beams to form the first and second openings, respectively.
6. The method of claim 5, wherein the first and second laser beams are applied to the cutting area simultaneously.
7. The method of claim 1, wherein cutting is performed using the blade.
8. The method of claim 7, wherein the first opening is located laterally between the first die and the second opening, wherein a first width of the blade is less than a second width between a first sidewall of the first opening closest to the first die and a second sidewall of the second opening closest to the second die.
9. A method of forming a semiconductor package, comprising:
forming a first conductive pillar and a second conductive pillar over a first side of a carrier;
attaching the first die and the second die to a first side of the carrier, the first die and the second die being adjacent to the first conductive pillar and the second conductive pillar, respectively;
forming a molding compound over the first side of the carrier, the molding compound extending along the sidewalls of the first die, the sidewalls of the second die, the sidewalls of the first conductive pillars, and the sidewalls of the second conductive pillars;
forming a redistribution structure over the first die, the second die, and the molding compound, the redistribution structure including a first redistribution region over the first die, a second redistribution region over the second die, and a dicing region between the first redistribution region and the second redistribution region;
an Under Bump Metal (UBM) structure formed over the redistribution structure and electrically connected to the redistribution structure;
forming a connector and an electronic device over the under bump metal structure;
removing portions of the redistribution structure in the cut region to form a first opening proximate the first die and a second opening proximate the second die, the first opening being separated from the second opening by remaining portions of the redistribution structure in the cut region;
attaching the redistribution structure to a tape after removing portions of the redistribution structure;
debonding the carrier;
electrically connecting the first semiconductor package to the first conductive pillars;
electrically connecting the second semiconductor package to the second conductive pillars; and
dicing through the molding compound from a back side of the first die using a blade, the dicing separating the first die from the second die, wherein during the dicing the blade does not cut into the tape,
wherein, after separating the first die and the second die, the first conductive pillar is a conductive pillar farthest from the first die, a first connection piece corresponding to the position of the first conductive pillar and closest to the electronic device is provided in the connection piece, and in the cross-sectional view, the first conductive pillar and the first connection piece are not physically connected through the conductive wire and the metal through hole in the redistribution structure.
10. A semiconductor package, comprising:
a lower package, comprising:
a redistribution structure;
a die and conductive pillars proximate to the die, the die and the conductive pillars being located over the redistribution structure, the conductive pillars having first and second conductive pillars furthest from the die and located on opposite sides of the die; and
a molding compound over the redistribution structure, the molding compound interposed between the die and the conductive posts, the molding compound extending beyond a lateral extent of the redistribution structure;
an Under Bump Metallurgy (UBM) structure underlying the redistribution structure, wherein an electronic device is electrically connected to the redistribution structure through the under bump metallurgy structure;
a connector under bump metal structure having a first connector therein closest to the electronic device and corresponding to the location of the first conductive pillar, and in cross-sectional view, the first conductive pillar is not physically connected to the first connector by a conductive line and a metal via in the redistribution structure.
CN202210868282.1A 2017-11-30 2018-07-02 Integrated fan-out package and method of forming the same Pending CN115274469A (en)

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US15/908,466 2018-02-28
CN201810707996.8A CN109860136A (en) 2017-11-30 2018-07-02 It is integrated to be fanned out to packaging part and forming method thereof

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