CN115269450A

CN115269450A - Memory cooperative management system and method

Info

Publication number: CN115269450A
Application number: CN202210925106.7A
Authority: CN
Inventors: 贾复山; 孙文瀚
Original assignee: Suzhou Centec Communications Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2022-11-01

Abstract

The application provides a memory collaborative management system and a memory collaborative management method, wherein a physical storage space and a virtual storage space are distributed on a memory and are respectively divided and set into a plurality of physical storage units and a plurality of virtual storage units, wherein the size of each virtual storage unit is set as the maximum allowable message length. And constructing an address translation table to store the corresponding relation between each physical storage unit pointer and each virtual storage unit pointer so as to realize mapping transformation of the physical storage unit pointer and the virtual storage unit pointer. In the scheme, the mapping of the virtual storage unit and the physical storage unit is realized through the address conversion controller, the splicing of the physical storage units is realized by hardware equipment, a CPU only needs to face the virtual storage unit, and the virtual storage unit is set to be the maximum allowable message length size so as to meet the requirement of completely storing a complete message. Therefore, the memory management is released from the CPU, and the utilization rate of the storage space can be well improved.

Description

Memory cooperative management system and method

Technical Field

The invention relates to the technical field of memory management, in particular to a memory cooperative management system and a memory cooperative management method.

Background

The development of embedded technology has higher and higher requirements on data Processing capability, and the data interaction amount between a Central Processing Unit (CPU) on a chip and other dedicated data Processing units or peripherals is also larger and larger. This data interaction is basically realized by a DMA (Direct Memory Access) method. In order to further improve the processing efficiency of the whole system, zero copy is required to be achieved as much as possible when the DMA and the CPU interact data, namely, the DMA writes data in a memory, the CPU can directly read and write according to addresses and does not need to copy to other addresses; on the contrary, the DMA can also directly read the data modified by the CPU according to the address. One operation that is important in the operation of DMA is the handling of descriptors. A descriptor is a basic information for the interaction between a DMA controller and a CPU. When the CPU receives data, the DMA is required to write the data into the memory and then update the information in the descriptor, including the data type, the length and the like, so that the CPU can read the descriptor again and process the received data conveniently. When the CPU sends data, the CPU is required to write the data into the memory, information such as the initial position and the size of the data in the memory is marked in the descriptor, and then the DMA controller reads the descriptor and reads the data from the memory according to the information and sends the data. In this process, the management mechanism of the memory affects the processing efficiency of the whole system. Because the processing procedure of the CPU is more complex and takes more time than the processing of the hardware logic, the processing efficiency of the CPU is not as high as that of the hardware. Thus, the less CPU involvement in memory management, the higher the processing efficiency of the overall system and vice versa. Therefore, in the above data interaction process, improving the efficiency of memory management is an important means for improving the processing efficiency of the whole system.

In the prior art, memory management is usually implemented in a software manner, and a CPU is used to complete application and release of a storage unit. In an existing common processing mode, storage units are generally divided and set according to a small granularity, but the data length of one ethernet message is uncertain, and the size of the storage unit pre-allocated by a CPU cannot necessarily store a complete ethernet message, and at this time, the CPU needs to add extra processing logic according to information in a received descriptor to splice data of a plurality of storage units into a complete ethernet message before normal processing, which will occupy a large amount of processing time of the CPU. If the storage unit is set according to the maximum message length, the storage resource may be wasted.

In addition, in the prior art, there is also a way to divide and set memory cells of multiple sizes and types according to different sizes, in this way, the size of each memory cell is still fixed, and only a limited number of options are available, if more options are to be set, more memory space must be allocated during initialization, which greatly increases the logic complexity of chip design. In addition, the message length in a short time is random, the number and the proportional relation of various storage units with different sizes cannot be accurately allocated during system initialization, and it is likely that some storage units with different sizes are used up, but other storage units are still left, so that the utilization rate of the storage space cannot be well improved.

Disclosure of Invention

The invention provides a memory collaborative management system and a memory collaborative management method, which can liberate memory management from a CPU and well improve the utilization rate of a storage space.

Embodiments of the invention may be implemented as follows:

in a first aspect, the present invention provides a memory cooperation management system, which includes a CPU, a DMA, an address conversion controller, and a memory, where the CPU and the DMA are connected to each other and are respectively connected to the address conversion controller, and the address conversion controller is connected to the memory through a system bus;

distributing a physical storage space and a virtual storage space on the memory, wherein the physical storage space comprises a plurality of physical storage units, the virtual storage space comprises a plurality of virtual storage units, the number of the physical storage units is the same as that of the virtual storage units, and the size of each virtual storage unit is set as the maximum allowable message length;

constructing an address conversion table in the address conversion controller, wherein the address conversion table stores the corresponding relation between each physical storage unit pointer and each virtual storage unit pointer so as to realize mapping conversion between the physical storage unit pointer and the virtual storage unit pointer;

the CPU is used for reading the stored message in the memory or writing the message to be sent into the memory based on the obtained virtual memory unit pointer;

the DMA is used for writing the received message into the corresponding physical storage unit or sending the written message in the corresponding physical storage unit based on the obtained physical storage unit pointer, and releasing the physical storage unit after the message in the physical storage unit is read or sent.

In an optional embodiment, when receiving a packet, the DMA is configured to obtain a physical storage unit pointer required by the packet to be received, write the received packet into a physical storage unit corresponding to the physical storage unit pointer, and write a virtual storage unit pointer corresponding to the physical storage unit pointer into a descriptor;

the CPU is used for reading the descriptor to obtain a virtual storage unit pointer after detecting that the message is received completely, obtaining a physical storage unit pointer corresponding to the virtual storage unit pointer by searching the address translation table, and reading the written message from the physical storage unit corresponding to the physical storage unit pointer.

In an optional embodiment, when receiving a packet, the CPU is further configured to modify a flag bit in the descriptor to notify that the DMA packet is completely read after the packet is completely read;

and the DMA is also used for searching the address translation table according to the virtual storage unit pointer in the descriptor to obtain a physical storage unit pointer corresponding to the virtual storage unit pointer and releasing the physical storage unit corresponding to the physical storage unit pointer.

In an optional embodiment, if the CPU is further configured to edit the read packet after the CPU finishes reading the packet, updating a flag bit in a descriptor of the edited packet after the editing is finished to notify the DMA;

and the DMA is also used for reading the edited message according to the information in the descriptor and releasing the physical storage unit occupied by the edited message after sending the edited message.

In an alternative embodiment, the physical storage unit pointer and the virtual storage unit pointer having the corresponding relationship have the same pointer number;

the DMA is used for writing the pointers of the physical storage units of the written messages into the positions of corresponding pointer numbers in the address translation table in sequence after the messages are received;

the CPU is used for subtracting the base address of the virtual storage unit on the basis of the virtual storage unit pointer through the address conversion controller to obtain a pointer number after reading the descriptor to obtain the virtual storage unit pointer, and searching the address conversion table according to the pointer number to obtain a corresponding physical storage unit pointer.

In an optional embodiment, when sending a message, the CPU is configured to, after completing editing of the message to be sent, obtain, by the address conversion controller, a virtual storage unit pointer corresponding to a first physical storage unit pointer of a physical storage unit in which the message to be sent is stored;

the CPU is also used for writing the message to be sent into a physical storage unit pointed by a physical storage unit pointer corresponding to the obtained virtual storage unit pointer, and writing the virtual storage unit pointer into a descriptor to inform the DMA of completing the writing of the message;

and the DMA is used for acquiring a corresponding physical storage unit pointer according to the virtual storage unit pointer in the descriptor after detecting that the message to be sent exists, and reading and sending the message to be sent from the physical storage unit pointed by the physical storage unit pointer.

the CPU is used for sequentially writing all physical storage unit pointers of the physical storage unit storing the message to be sent into the corresponding pointer numbers in the address conversion table after the virtual storage unit pointer corresponding to the first physical storage unit pointer is obtained through the address conversion controller;

the CPU is used for subtracting the base address from the obtained virtual storage unit pointer to obtain a pointer number, searching the address conversion table based on the pointer number to obtain a corresponding physical storage unit pointer, and writing the message to be sent into the corresponding physical storage unit according to the sequence of the physical storage unit pointer;

the DMA is used for subtracting the base address from the virtual storage unit pointer in the obtained descriptor to obtain a pointer number, searching the address conversion table based on the pointer number to obtain a physical storage unit pointer, and sequentially reading and sending the message to be sent according to the physical storage unit pointer.

In an optional embodiment, the physical storage unit pointer and the virtual storage unit pointer are in a one-to-one correspondence.

In an alternative embodiment, the physical storage units have the same size, and the virtual storage units have the same size.

In a second aspect, the present invention provides a memory cooperation management method, which is applied to the memory cooperation management system described in any one of the foregoing embodiments, where the system includes a CPU, a DMA, an address translation controller, and a memory, where the CPU and the DMA are connected to each other and are respectively connected to the address translation controller, and the address translation controller is connected to the memory through a system bus, and the method includes:

constructing an address translation table in the address translation controller, wherein the address translation table stores the corresponding relation between each physical storage unit pointer and each virtual storage unit pointer so as to realize mapping transformation between the physical storage unit pointer and the virtual storage unit pointer;

the CPU reads the messages stored in the memory or writes the messages to be sent into the memory based on the obtained virtual memory unit pointer;

and the DMA writes the received message into the corresponding physical storage unit or sends the written message out of the corresponding physical storage unit based on the obtained physical storage unit pointer, and releases the physical storage unit after the message in the physical storage unit is read or sent.

The beneficial effects of the embodiment of the invention include, for example:

the application provides a memory collaborative management system and a method, an address conversion controller is added on the basis of a traditional architecture, a physical storage space and a virtual storage space are distributed on a memory and are respectively divided and set into a plurality of physical storage units and a plurality of virtual storage units, wherein the size of each virtual storage unit is set as the maximum allowable message length. And constructing an address translation table in the address translation controller to store the corresponding relation between each physical storage unit pointer and each virtual storage unit pointer so as to realize mapping transformation of the physical storage unit pointer and the virtual storage unit pointer. The CPU can read and write the message based on the virtual storage unit pointer, and the DMA can write or send the message based on the physical storage unit pointer and release the physical storage unit.

In the scheme, the mapping of the virtual storage unit and the physical storage unit is realized through the address conversion controller, the splicing of the physical storage units is realized by hardware equipment, a CPU only needs to face the virtual storage unit, and the virtual storage unit is set to be the maximum allowable message length size so as to meet the requirement of completely storing a complete message. Therefore, the memory management is released from the CPU, and the utilization rate of the storage space can be well improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a schematic diagram of a memory cooperation management system in the prior art;

fig. 2 is a second schematic structural diagram of a memory cooperation management system in the prior art;

fig. 3 is a schematic structural diagram of a memory cooperation management system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a physical storage space and a virtual storage space provided in an embodiment of the present application;

fig. 5 is a flowchart of a memory cooperation management method according to an embodiment of the present application.

Detailed Description

In the prior art, two processing methods are mainly used for improving the processing efficiency of the whole system. The first processing mode is realized by adopting a software mode, and the CPU manages the whole memory. As shown in fig. 1, the CPU contains a Memory Management Unit (MMU) for managing the entire memory space. The CPU allocates a plurality of memory locations (i.e. BUFs) in the memory in advance, the physical addresses of the memory locations may be continuous or discontinuous, and when the physical addresses are discontinuous, the MMU of the CPU can change the addresses into logically continuous addresses through logical processing.

When the CPU receives data, the CPU is to configure available BufPtr (memory location pointer) into a descriptor to be used for DMA. When receiving the data, the DMA controller writes the received data into the specified BUF according to BufPtr in the descriptor. If more data is received and the memory space in the descriptor is not sufficient (i.e., the BUF is not large enough to store the entire received data), the DMA controller is required to fetch more descriptors and BUFs to continue storing the data. The DMA controller updates the information in the descriptor, including the data type and the size of the actual data received, upon completion of data reception, and informs the CPU at the end. And the CPU processes the received data according to the information in the descriptor, and releases the occupied Buf after the processing is finished.

When the CPU sends data, the CPU is required to obtain an available BufPtr, write the data to be sent into the Buf, and then notify the DMA controller of the data size and the corresponding BufPtr through a descriptor. And the DMA controller reads the data to be sent in the memory according to the BufPtr and other information in the descriptor, sends the data to be sent to the specified target device, and finally updates the state of the descriptor and informs the CPU. And after the CPU checks that the DMA operation is completed, releasing the occupied BUF.

As shown in fig. 1, the DMA controller and the CPU are connected to the memory through a bus. The CPU controls the address allocation of the whole memory, and the DMA controller completely operates the reading and writing of data in the memory according to the instruction of the CPU.

In this processing mode, the CPU generally has MMU and IOMMU to manage the memory, and when initializing the BUF, the memory can be set with a finer granularity (e.g. 1 KB), and the physically discontiguous addresses are changed into logically continuous addresses, so as to facilitate the cache coherency processing (cache coherency can improve the performance of the whole system).

However, as can be seen from the above description, in the data interaction process between the CPU and the DMA controller, the application and release of the BUF are all completed by the CPU, which occupies a large amount of operation time of the CPU, and results in low overall processing efficiency. If the received data is similar to the ethernet message, because the data length of an ethernet message is uncertain (generally, 64 bytes is minimum, and the longest is not more than 16 KB), the BUF size pre-allocated by the CPU is not necessarily capable of storing a complete ethernet message, and in this case, a plurality of descriptors and a plurality of BUFs (only one BUF can be included in one descriptor) are necessarily occupied. And the CPU is required to add extra processing logic according to the received information in the descriptor to splice the data in the multiple BUFs into a complete Ethernet message before the data can be normally processed. This operation will also take up a significant amount of processing time by the CPU. If the CPU allocates each BUF to ensure that a complete ethernet message can be stored, it must be set to the maximum message length (i.e., 16 KB), which occupies the entire 16KB BUF even if a smaller message is received (because only a maximum of one message can be stored in one BUF). The average length of ethernet messages in a real environment is mostly between 1KB and 2 KB. Therefore, setting the BUF size according to the maximum message length inevitably wastes a large amount of memory resources.

In the second processing mode, a memory management module shown in the figure is added as shown in fig. 2, and the management of the memory is realized by hardware logic in the module. When the system is initialized, a CPU firstly develops a storage space for receiving and sending data, the storage space is fixed and can only be managed by the memory management module, and other processing on the CPU cannot be occupied. These storage spaces are subdivided into a plurality of BUFs of different sizes. For example, cut multiple BUFs in 1KB, 2KB, 4KB, and 16KB sizes, and compose their bufptrs into multiple BPPs by size. For example, BPP1 is used to store 1KB of BufPtr for BUF, BPP2 is used to store 2KB of BufPtr for BUF, BPP3 is used to store 4KB of BufPtr for BUF, and BPP4 is used to store 16KB of BufPtr for BUF.

When receiving data, the CPU only configures other field information in the descriptor, and does not need to perform the operation of actively acquiring the available BufPtr and writing the BufPtr into the descriptor. When the DMA controller receives the data, the DMA controller selects BufPtr with proper size from the 4 BPPs through the memory management module according to the length of the received data, writes the received data into the BUF corresponding to the BufPtr, and then updates the information (including the BufPtr and the actually written data length) in the descriptor. After the CPU checks that the data reception is completed, the descriptor is read, and specific data is acquired according to BufPtr and other information in the descriptor. After the CPU finishes processing data, only the descriptor needs to be updated and the DMA controller is informed, and the BUF does not need to be released actively. After the DMA controller detects that the CPU processing is finished, the DMA controller finishes message receiving processing and releases the occupied BUF through the memory management module, namely, the BufPtr is rewritten into the original BPP.

When sending data, the CPU needs to select BufPtr with an appropriate size from 4 BPPs according to the length of the data to be sent (implemented by the memory management module), write the data to be sent into the corresponding BUF, then update the descriptor information (including the BufPtr and the actual length of the data to be sent), and notify the DMA controller. And the DMA controller reads the data to be sent from the corresponding BUF according to the BufPtr in the descriptor and other information to complete the processing of data sending. The DMA controller then updates the state, informs the CPU, and automatically releases the BUF through the memory management module (i.e., rewriting BufPtr into the original BPP). The CPU no longer needs to perform the operation of releasing the BUF at this time.

In the processing mode, the memory management module configures the DMA controller to complete the application and release of the BUF, so that the processing process of a CPU is omitted, the time occupation of the CPU is reduced, and the processing efficiency of the overall system is improved.

But the size of each BUF in this approach is fixed and only a limited number of choices (1 KB, 2KB, 4KB, and 16KB in the above example) are available. If more options are to be set, more memory space must be allocated at initialization, which also greatly increases the logic complexity of the chip design. In practical application environments, although the length of the ethernet message has an approximate proportional relationship in the long term, the message length is random in a short time. Therefore, the number and the proportional relation of the BUFs with different sizes cannot be accurately distributed during system initialization, so that the situation that part of the BUFs with different sizes are used up is likely to occur, but other BUFs have more surplus, and the utilization rate of the storage space cannot be well improved.

Based on the above research, it is found that the processing modes in the prior art all have many defects, and therefore the present application provides a memory cooperation management scheme, in this scheme, mapping of a virtual storage unit and a physical storage unit is realized through an address conversion controller, splicing of the physical storage unit is realized by hardware equipment, a CPU only needs to face the virtual storage unit, and the virtual storage unit is set to the maximum allowable message length size, so that the requirement of completely storing a complete message can be met. Therefore, the memory management is released from the CPU, and the utilization rate of the storage space can be well improved.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.

Referring to fig. 3, a memory cooperation management system provided in the embodiment of the present application includes a CPU, a DMA, an address conversion controller and a memory, where the CPU and the DMA are connected to each other, the CPU and the DMA are respectively connected to the address conversion controller, and the address conversion controller is connected to the memory through a system bus.

In addition, in this embodiment, the memory cooperation management system further includes a memory management module, and the memory management module is connected between the CPU and the DMA. The memory management module may be used to manage cell pointers for the memory cells.

In this embodiment, a physical storage space and a virtual storage space are allocated on a memory, the physical storage space includes a plurality of physical storage units, the virtual storage space includes a plurality of virtual storage units, the number of the physical storage units is the same as that of the virtual storage units, and the size of each virtual storage unit is set to be the maximum allowable message length. The physical storage units have the same size, and the virtual storage units have the same size.

When the system is initialized, a large block of storage space with continuous or discontinuous physical addresses, namely physical storage space, is allocated on the storage. The physical memory space is used as the data memory space of the CPU and the DMA, and other operations can not occupy the address space. Correspondingly, a section of virtual storage space is allocated on the address visible to the CPU, and the section of virtual storage space is visible to the CPU and can be read and written normally, but is actually a virtual address space.

Taking processing of ethernet packets as an example, 1MB of continuous physical address storage space can be initialized as physical storage space, and is recorded as storage space a. The physical memory space is divided into 1K physical memory cells (1kb × 1k = 1mb) in a fixed 1KB size. The physical memory location pointers of the 1K physical memory locations are written to the BPP of the memory management module.

In addition, a virtual storage space which can be operated by the CPU is defined and is marked as a storage space B, and the size of the virtual storage space is larger than that of the physical storage space. And each virtual storage unit in the virtual storage space is guaranteed to be enough to store a section of data with the maximum length. Taking the example of ethernet message data, the maximum message data length is 16KB, and therefore, the size of the virtual memory unit can be set to 16KB.

Each physical storage unit in the physical storage space has a corresponding virtual storage unit in the virtual storage space. In the above example, the virtual storage space should also contain 1K virtual storage units, and the size of each virtual storage unit is 16KB, that is, the virtual storage space is set to be 16 times the size of the physical storage space.

In the above examples, the size of the physical storage space is only an example, and this embodiment is not limited to this example, and specifically needs to be set according to the actual size of the system memory and the requirement of a specific application. For example, the size of the physical storage space is typically over a few hundred MB.

In addition, the size of each physical storage space is not limited to this, and may be determined according to the requirements of a specific application, and the smaller the granularity is, the more storage unit pointers are managed, the more complex the logic is, and vice versa, the simpler the logic is.

The virtual storage space is divided into virtual storage units with the size of 16KB, which is set according to the Ethernet message and usually does not exceed 16KB, and the specific setting is only required to meet the requirement of storing the maximum message length. The total size of the virtual storage space is determined by the granularity of the split of the virtual storage space and the physical storage space: virtual memory size = (virtual memory granularity/physical memory granularity) = physical memory size.

In this embodiment, the virtual memory space is virtual, but occupies an address space that is actually accessible to the CPU. Most current CPUs support 64-bit address space, so that the virtual memory space is large, but has no influence on the design of the CPU.

In the above example, the physical storage space is physically continuous, but may be set to be discontinuous in actual use. In this case, the memory cooperation management system further includes a Memory Management Unit (MMU), and the memory management unit may convert the discontinuous physical memory space into a continuous address space and then set corresponding to the virtual memory space.

In this embodiment, an address translation table is built in the address translation controller, and the address translation table stores the corresponding relationship between each physical memory location pointer and each virtual memory location pointer, so as to implement mapping transformation between the physical memory location pointer and the virtual memory location pointer.

Specifically, the virtual storage unit pointers and the physical storage unit pointers are in a one-to-one correspondence relationship, and then each virtual storage unit pointer is numbered and named as a pointer number BUF _ ID. Because the addresses of the current virtual memory space are contiguous, the virtual memory location pointer and pointer number are effectively identical. The pointer number plus the base address of the virtual memory unit is the virtual memory unit pointer. I.e. the pointer number and the physical memory location pointer are also in a one-to-one correspondence. And the address translation table realizes reading and writing by using the pointer number as an index.

In this embodiment, the memory cooperation management process mainly relates to a data receiving process and a data sending process. On the basis of the setting, the CPU can be used for reading the stored message in the memory or writing the message to be sent into the memory based on the obtained virtual memory unit pointer.

The DMA may be configured to write the received packet into the corresponding physical storage unit or send the packet written in the corresponding physical storage unit based on the obtained physical storage unit pointer, and release the physical storage unit after the packet in the physical storage unit is read or sent.

In the scheme, the mapping of the virtual storage unit and the physical storage unit is realized through the address conversion controller, the splicing of the physical storage units is realized by hardware equipment, a CPU only needs to face the virtual storage unit, and the virtual storage unit is set to be the maximum allowable message length size so as to meet the requirement of completely storing a complete message. Therefore, the memory management is liberated from the CPU, and the utilization rate of the storage space can be well improved.

First, the address conversion setting in the present embodiment will be described below. In this embodiment, as shown in the left box in fig. 4, the physical storage units in the physical storage space may be named BUF _ a, and there are N total (the specific data of N is determined according to the actual application requirement, such as 1K in the above example). Each virtual storage unit in the virtual storage space may be named BUF _ B, again N, as shown in the right-hand box in FIG. 4. Each BUF _ B corresponds to one or more BUF _ As, and the first BUF _ A is the BUF _ A of the left physical storage space in the figure. The BUF _ a contained in each BUF _ B is selected in order from the BPP by the memory management module starting from the second. The number of BUF _ as each BUF _ B contains is determined by the size of the actual received or transmitted data. As in the above example, when the DMA receives a 4KB ethernet packet, the corresponding BUF _ B should include 4 BUF _ as.

On the basis, when receiving a message, the DMA may be configured to obtain a physical storage unit pointer required by the message to be received, write the received message into a physical storage unit corresponding to the physical storage unit pointer, and write a virtual storage unit pointer corresponding to the physical storage unit pointer into the descriptor.

And the CPU can be used for reading the descriptor to obtain the virtual storage unit pointer after detecting that the message is received completely, obtaining the physical storage unit pointer corresponding to the virtual storage unit pointer by searching the address conversion table, and reading the written message from the physical storage unit corresponding to the physical storage unit pointer.

As can be seen from the above, in the present embodiment, the physical storage unit pointer and the virtual storage unit pointer having the corresponding relationship have the same pointer number.

The DMA is used for writing the physical memory unit pointers of the written messages into the corresponding pointer numbers in the address translation table in sequence after the messages are received.

Specifically, when receiving a message, the DMA finishes the current message receiving operation after the message is received, for example, when receiving an end flag of the message. The DMA writes BufPtr _ a (physical memory unit pointer) of the written message into the corresponding BUF _ ID (pointer number) in the address translation table in sequence. That is, the BUF _ ID corresponding to the BufPtr _ a of the write message may be used as an index to find the corresponding location in the address translation table, and the BufPtr _ a is written into the corresponding location, which indicates that the actual physical address of the BufPtr _ B (virtual memory cell pointer) currently written into the descriptor is the BufPtr _ a written into the address translation table.

When one BUF _ a is not enough to store the whole received message, the DMA needs to acquire a plurality of BufPtr _ as from the BPP and write the received message into the corresponding BUF _ a. When the BufPtr _ a is written into the address translation table, the BufPtr _ a is sequentially written in the order of the BUF _ as, and thus, the order information of the BufPtr _ as is recorded to indicate that the BUF _ as are currently occupied.

And the CPU can be used for subtracting the base address of the virtual memory unit on the basis of the virtual memory unit pointer by the address conversion controller to obtain a pointer number after the descriptor is read to obtain the virtual memory unit pointer, and searching the address conversion table according to the pointer number to obtain the corresponding physical memory unit pointer.

Specifically, when the message reception is performed and the CPU detects that the message reception is completed, the CPU acquires BufPtr _ B by reading the descriptor information, and initiates a request for reading the message based on the BufPtr _ B. The request for reading the message is processed by the address conversion controller, and the BUF _ ID is obtained by subtracting the base address of the BUF _ B from the BufPtr _ B, and then the corresponding position of the address translation table is indexed according to the BUF _ ID, so that all BufPtr _ A used when the message data is actually stored and the sequence information of the BufPtr _ A are found. Finally, the request to read the message is converted to read the BufPtr _ a in order to obtain the received message data.

Although the BufPtr _ a may be physical address discontinuity, the CPU operates with BufPtr _ B, so that the CPU operates with a larger continuous address space, and all cache coherency processing corresponding to the address can be performed normally without being affected.

On the basis, when the message is received, the CPU is also used for modifying the flag bit in the descriptor to inform that the DMA message is completely read after the message is completely read. The DMA is also used for searching the address translation table according to the virtual memory unit pointer in the descriptor to obtain a physical memory unit pointer corresponding to the virtual memory unit pointer and releasing the physical memory unit corresponding to the physical memory unit pointer.

Specifically, after obtaining the descriptor updated by the CPU, the DMA calculates the BUF _ ID according to the BufPtr _ B in the descriptor through hardware logic, indexes the BUF _ ID to a corresponding position in the address translation table, obtains the occupied actual BufPtr _ a, and writes the BufPtr _ a into the BPP for subsequent operation, that is, releases the BUF _ a pointed by the BufPtr _ a.

In addition, in the process of sending the message, after the CPU finishes editing the message to be sent, the CPU obtains, by the address conversion controller, a virtual storage unit pointer corresponding to the first physical storage unit pointer of the physical storage unit storing the message to be sent. The CPU is also used for writing the message to be sent into the physical storage unit pointed by the physical storage unit pointer corresponding to the obtained virtual storage unit pointer, and writing the virtual storage unit pointer into the descriptor to complete the writing of the message through the DMA.

And the DMA is used for obtaining a corresponding physical storage unit pointer according to the virtual storage unit pointer in the descriptor after detecting that the message to be sent exists, and reading and sending the message to be sent from the physical storage unit pointed by the physical storage unit pointer.

In the process that the CPU writes the message to be sent into the corresponding physical storage unit, the CPU sequentially writes all physical storage unit pointers of the physical storage unit storing the message to be sent into the corresponding pointer numbers in the address conversion table after obtaining the virtual storage unit pointer corresponding to the first physical storage unit pointer through the address conversion controller. And the CPU subtracts the base address from the obtained virtual memory unit pointer to obtain a pointer number, searches an address conversion table based on the pointer number to obtain a corresponding physical memory unit pointer, and writes the message to be sent into the corresponding physical memory unit according to the sequence of the physical memory unit pointer.

In the process of reading and sending the message to be sent by the DMA, the DMA obtains a pointer number by subtracting the base address of the virtual storage unit pointer in the obtained descriptor, searches an address conversion table based on the pointer number to obtain a physical storage unit pointer, and reads and sends the message to be sent according to the physical storage unit pointer in sequence.

Specifically, in the process of sending a message, the CPU first completes the editing of the message to be sent, and then sends an instruction to obtain a physical storage unit sufficient for storing the data of the message to be sent from the BPP. After receiving the instruction, the address conversion controller obtains one or more BufPtr _ as according to the size of the physical storage unit required by the CPU, sends the BufPtr _ B corresponding to the first BufPtr _ a to the CPU, writes all the BufPtr _ as into the corresponding positions of the address conversion tables indexed by the BUF _ ID, and records the use sequence among the BufPtr _ as well.

And the CPU executes write operation according to the received BufPtr _ B and writes the message data to be sent into the memory. The request for the write operation is also first processed by the address switch controller. And calculating the BUF _ ID according to the BufPtr _ B, indexing the corresponding position of the address translation table according to the BUF _ ID, sequentially switching to the corresponding BufPtr _ A, and sequentially writing the message data to be sent. After the CPU executes the data writing operation, it writes BufPtr _ B and other information of the message to be sent into the descriptor, and notifies the DMA.

And after the DMA detects that the message to be sent is detected, initiating the operation of reading the message data to be sent according to the BufPtr _ B in the descriptor. The read operation request is first processed by the address translation controller to obtain all ButPtr _ A and the sequence relationship between them from the virtual address translation table according to BufPtr _ B. And then, the message data to be sent is really read from the memory in sequence, and finally the message is sent to the appointed target equipment.

In addition, after the DMA sends the message data, the BufPtr _ a occupied by the DMA is released, that is, the BufPtr _ a is written into the BPP for use in subsequent operations.

In the memory cooperation management process, besides the above message receiving and sending processes, a message forwarding process is also involved. The message forwarding process is essentially a process of re-editing the message by the CPU after the message reception is completed, and then sending out the re-edited message.

In the process of forwarding the message, the process of receiving the message may refer to the above, which is not described herein again. On the basis, if the CPU is also used for editing the read message after the CPU finishes reading the message, the flag bit in the descriptor of the edited message is updated to inform the DMA after the editing is finished. The DMA is also used for reading the edited message according to the information in the descriptor and releasing the physical storage unit occupied by the edited message after sending the edited message.

Specifically, in the message forwarding process, when the above received message data processing is completed, the BUF cannot be released yet. When the CPU is required to update the descriptor, the CPU marks whether the BUF is to be released currently. If the message is processed normally, the BUF management logic of the hardware needs to release the BUF according to the description information in the descriptor in the message receiving process. Otherwise, the process of releasing the BUF is not executed.

And after the CPU finishes editing, directly updating the descriptor of the message to be sent to inform the DMA to finish the message sending processing, and normally finishing the BUF releasing operation.

In the process, the message is received and finally sent out again, and the used BUF is always in an occupied state. The storage position of the message is ensured to be unchanged, the operation of copying the message data by the CPU is reduced, and the message logic is finished in the original position. The operation of the CPU is reduced, and the overall message forwarding efficiency is improved.

According to the memory cooperation management scheme provided by the embodiment, the memory space is managed through hardware logic, and the application and release of the memory unit are not required to be realized by a CPU. And based on the address translation tables in the address translation controller to handle the address translation process at DMA accesses and CPU accesses. The virtual memory unit in the virtual memory space faced by the CPU is a larger memory unit capable of storing the maximum allowable data length, even if the physical address is discontinuous, the splicing of a plurality of smaller physical memory units can be realized based on the address translation table, so that the requirement of large-quantity storage is facilitated. For the CPU, the virtual storage unit corresponding to the spliced virtual storage unit is a complete storage space with continuous addresses, and the CPU does not perceive the actual physical organization form, and does not affect all operations performed on the virtual storage unit by the CPU, including read-write access, cache coherency processing, and the like. Thereby releasing the storage management from the CPU well and improving the utilization rate of the storage space.

Referring to fig. 5, a memory cooperation management method provided in the embodiment of the present application is implemented by the memory cooperation management system, and the memory cooperation management method includes the following steps:

s101, distributing a physical storage space and a virtual storage space on the memory, wherein the physical storage space comprises a plurality of physical storage units, the virtual storage space comprises a plurality of virtual storage units, the number of the physical storage units is the same as that of the virtual storage units, and the size of each virtual storage unit is set as the maximum allowable message length.

S102, an address translation table is constructed in the address translation controller, and the address translation table stores the corresponding relation between each physical storage unit pointer and each virtual storage unit pointer so as to realize mapping transformation between the physical storage unit pointer and the virtual storage unit pointer.

And S103, the CPU reads the messages stored in the memory or writes the messages to be sent into the memory based on the obtained virtual memory unit pointer.

And S104, the DMA writes the received message into the corresponding physical storage unit or sends the written message out of the corresponding physical storage unit based on the obtained physical storage unit pointer, and releases the physical storage unit after the message in the physical storage unit is read or sent out.

The memory cooperation management method provided by this embodiment can implement mapping between the virtual storage unit and the physical storage unit through the address conversion controller, the physical storage unit is spliced by the hardware device, the CPU only needs to face the virtual storage unit, and the virtual storage unit is set to the maximum allowable message length size, which can satisfy the requirement of completely storing a complete message. Therefore, the memory management is liberated from the CPU, and the utilization rate of the storage space can be well improved.

It should be noted that the memory cooperation management method provided in this embodiment is implemented by the memory cooperation management system, and has the same and similar technical effects as the memory cooperation management system. For details, reference may be made to corresponding parts in the above embodiments, which are not described herein.

To sum up, the memory cooperation management system and method provided in the embodiments of the present application add an address translation controller on the basis of a traditional architecture, allocate a physical storage space and a virtual storage space on a memory, and respectively divide and set the physical storage space and the virtual storage space into a plurality of physical storage units and a plurality of virtual storage units, where the size of each virtual storage unit is set as the maximum allowable message length. And constructing an address translation table in the address translation controller to store the corresponding relation between each physical storage unit pointer and each virtual storage unit pointer so as to realize mapping transformation of the physical storage unit pointer and the virtual storage unit pointer. The CPU can read and write the message based on the virtual storage unit pointer, and the DMA can write or send the message based on the physical storage unit pointer and release the physical storage unit.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A memory collaborative management system is characterized by comprising a CPU, a DMA, an address conversion controller and a memory, wherein the CPU and the DMA are mutually connected and respectively connected with the address conversion controller, and the address conversion controller is connected with the memory through a system bus;

2. The memory cooperation management system according to claim 1, wherein when receiving a packet, the DMA is configured to obtain a physical storage unit pointer required by the packet to be received, write the received packet into a physical storage unit corresponding to the physical storage unit pointer, and write a virtual storage unit pointer corresponding to the physical storage unit pointer into a descriptor;

3. The memory cooperation management system according to claim 2, wherein when receiving a message, the CPU is further configured to modify a flag bit in the descriptor to notify that the DMA message is completely read after the message is completely read;

4. The memory cooperation management system according to claim 3, wherein if the CPU is further configured to edit the read message after the CPU finishes reading the message, the flag bit in the descriptor of the edited message is updated to notify the DMA after the editing is finished;

5. The memory co-management system according to claim 2, wherein the physical storage unit pointer and the virtual storage unit pointer having the correspondence relationship have the same pointer number;

6. The memory cooperation management system according to claim 1, wherein when a message is sent, the CPU is configured to obtain, by the address conversion controller, a virtual storage unit pointer corresponding to a first physical storage unit pointer of a physical storage unit storing the message to be sent after the CPU completes editing of the message to be sent;

and the DMA is used for obtaining a corresponding physical storage unit pointer according to the virtual storage unit pointer in the descriptor after detecting that a message to be sent exists, and reading and sending the message to be sent from the physical storage unit pointed by the physical storage unit pointer.

7. The memory co-management system according to claim 6, wherein the physical storage unit pointer and the virtual storage unit pointer having the correspondence relationship have the same pointer number;

8. The memory co-management system according to any one of claims 1 to 7, wherein the physical storage unit pointer and the virtual storage unit pointer are in a one-to-one correspondence.

9. The memory co-management system according to any one of claims 1 to 7, wherein the physical storage units have the same size, and the virtual storage units have the same size.

10. A memory cooperation management method applied to the memory cooperation management system of any one of claims 1 to 9, wherein the system comprises a CPU, DMAs, an address conversion controller and a memory, the CPU and the DMAs are connected to each other and respectively connected to the address conversion controller, and the address conversion controller is connected to the memory through a system bus, the method comprises:

allocating a physical storage space and a virtual storage space on the memory, wherein the physical storage space comprises a plurality of physical storage units, the virtual storage space comprises a plurality of virtual storage units, the number of the physical storage units is the same as that of the virtual storage units, and the size of each virtual storage unit is set as the maximum allowable message length;