CN115268206A

CN115268206A - OPC correction hot spot pattern inspection method

Info

Publication number: CN115268206A
Application number: CN202210862834.8A
Authority: CN
Inventors: 张月雨; 汪悦
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2022-07-20
Filing date: 2022-07-20
Publication date: 2022-11-01

Abstract

The invention discloses an OPC correction hot spot pattern inspection method, which comprises the following steps: firstly, carrying out OPC correction on an original layout for N + M times to obtain a first corrected layout; n is the desired number of convergence and M is the number of additional cycles. And step two, carrying out OPC correction on the original layout for N times to obtain a second corrected layout. And step three, carrying out difference check on the first corrected layout and the second corrected layout to obtain the layout graph difference. And step four, classifying the difference of the layout graphs and obtaining OPC correction hot spot graphs of corresponding types according to the classification. The method does not need to use an OPC model for simulation operation, can save the retrieval time of OPC hot-spot graphs, is convenient and quick to position and optimize, and can obviously improve the efficiency of OPC development and optimization in the OPC development and optimization.

Description

OPC correction hot spot pattern inspection method

Technical Field

The present invention relates to a semiconductor integrated circuit manufacturing method, and more particularly, to a method for inspecting a hot spot pattern (hot spot) of an Optical Proximity Correction (OPC) pattern.

Background

In the photoetching process, a graphic structure corresponding to a layout on a Mask, namely a photomask (Mask), is projected into a photoresist through an exposure system and forms a corresponding graphic structure in the photoresist, but due to optical reasons or chemical reactions of the photoresist in the exposure process, the graphic structure formed in the photoresist and the graphic structure on the Mask have deviation, the deviation needs to be corrected through OPC in advance to modify the graphic structure on the Mask, and when the Mask corrected through OPC is used for exposure, the graphic structure formed in the photoresist conforms to the designed graphic structure and meets the process production requirements.

The OPC includes Rule-based OPC and model-based OPC.

Early rule-based OPC was widely used due to its simplicity and fast computation. However, this method requires manual OPC rules, which become extremely cumbersome and difficult to follow as optical distortions become more severe.

At this time, model-based OPC should be generated. The OPC method based on the model establishes an accurate calculation model through optical simulation, and then adjusts the edge of the graph to continuously simulate and iterate until the graph approaches to an ideal graph. Model-based OPC makes the OPC process more complex and the demand for computing resources grows exponentially.

With the development of semiconductor manufacturing processes and the continuous reduction of the size of graphs, the number of graphs in a unit area is multiplied, the graphs of a layout (mask) become more and more complex, the precision requirement on an OPC model is continuously improved, the time of OPC operation is continuously increased due to the high-precision OPC model and the more complex and more huge number of the graphs of the layout, and higher challenges are provided for the development and operation of OPC.

The existing OPC correction hot spot pattern inspection method comprises the following steps:

and carrying out simulation operation on the corrected Mask by using an OPC model to obtain a simulated Contour line (Contour), comparing the simulated Contour line obtained by operation with a correction target, and finding out a position where the deviation of Edge Placement Error (EPE) exceeds a specification (Spec), namely an OPC correction hotspot graph. This method requires simulation calculation using an OPC model and comparison of deviation values between all simulated contours and the corrected target, and therefore takes a lot of calculation resources and a long time.

The conventional method for checking the OPC correction hotspot is slow in operation, large in error reporting quantity of the operated file, occupies a large disk space, is easy to submerge a key graph in the large error reporting, is not beneficial to development and optimization of the OPC program, and has very adverse effects on timeliness and speed of development and optimization of the OPC program.

Example (c): taking 28nm as an example, the operation time of a single Graphic Data Stream (GDS) single layer is more than 10 hours by using 500 cpus to check hot spot graphics; for more advanced technology nodes, if published for Multi Project Wafer (MPW), there are typically tens of GDS data, and the computational resource consumption is huge.

When new development or OPC program development with larger OPC adjustment is carried out, because continuous debugging is needed, OPC correction hot spot check is continuously operated to confirm whether the OPC result meets the publishing requirement.

Therefore, when an OPC program is developed, the traditional method for checking the OPC correction hot spot consumes large computing resources, the number of errors reported after computing is usually tens of thousands, and data files are huge, so that the method is very unfavorable for the timeliness of development and optimization of the OPC program.

Disclosure of Invention

The invention aims to solve the technical problem of providing an OPC correction hot spot pattern inspection method, which does not need to use an OPC model for simulation operation, can save the retrieval time of OPC hot spot patterns, is convenient and quick for positioning the problems and carrying out optimization solution, and can obviously improve the efficiency of OPC development and optimization in the OPC development and optimization.

In order to solve the technical problem, the method for checking the hot spot graph for OPC correction provided by the invention comprises the following steps:

firstly, performing OPC correction on an original layout for N + M times to obtain a first corrected layout; and N is the expected convergence times, M is the additional cycle times, and the first corrected layout is used as a convergence target layout.

And secondly, performing OPC correction on the original layout for N times to obtain a second corrected layout.

And thirdly, carrying out difference check on the first corrected layout and the second corrected layout to obtain the layout graph difference.

And fourthly, classifying the difference of the layout graphs and obtaining OPC correction hot spot graphs of corresponding types according to the classification.

The further improvement is that the method also comprises the following steps:

step five, if the hot spot graphs of the OPC correction completely disappear or are reduced to meet the requirement of mass production in the step four, taking the parameters of the OPC correction as the final parameters of the OPC correction;

if the OPC corrected hot spot graph does not meet the requirement of mass production in the fourth step, optimizing OPC corrected parameters according to the OPC corrected hot spot graph so as to reduce the difference of the layout graph as an optimization direction;

and step six, repeating the step two to the step five by using the optimized OPC corrected parameters.

The further improvement is that the method also comprises the following steps:

and seventhly, carrying out OPC verification (Verify) detection to confirm whether the final parameters of the OPC are in accordance with the correction requirements.

The further improvement is that the seventh step comprises the following sub-steps:

and step 71, simulating the second corrected layout obtained by adopting the final parameters of the OPC correction to obtain a simulated contour graph.

And step 72, comparing the simulation outline graph with a graph of a target layout to confirm whether the final parameters of the OPC correction meet the correction requirements or not.

In a further improvement, the target layout adopts the original layout.

The further improvement is that N is set according to the actual hierarchy and OPC correction difficulty during mass production, and the smaller the value of N is, the better the correction precision is.

A further improvement is that N is in the range of 4< = N < =30.

The further improvement is that the larger the value of M is, the better the correction result is, and the value range of M is 1< = M < =50.

A further improvement is that the discrepancy check in step three is implemented by performing an exclusive or logic (XOR) operation on the first corrected layout and the second corrected layout.

In a further improvement, the classification in step four includes:

dividing the Error reporting value of the one-dimensional graph EPE by a Mask Error Enhancement Factor (MEEF) of the one-dimensional graph Mask as a primary boundary value; EPE denotes edge placement error and MEEF denotes reticle error enhancement factor.

And dividing the EPE deviation error reporting value of the two-dimensional graph by the MEEF of the two-dimensional graph to serve as a secondary boundary value.

And comparing the difference of the layout graphs with the first-level boundary value and the second-level boundary value to classify the OPC corrected hot spot graphs.

The further improvement is that the range of the EPE deviation error reporting value of the one-dimensional graph is more than or equal to 0.1nm and less than or equal to 8nm.

In a further improvement, the EPE deviation error reporting value of the two-dimensional graph ranges from more than or equal to 0.5nm to less than or equal to 15nm.

The further improvement is that the OPC corrected hot spot graph corresponding to the layout graph difference is a one-dimensional hot spot graph when the layout graph difference is larger than the first-level boundary value and smaller than the second boundary value.

The further improvement is that the OPC corrected hot spot graph corresponding to the layout graph difference is a two-dimensional hot spot graph when the layout graph difference is larger than or equal to the second boundary value.

In a further improvement, each OPC correction in the first and second steps is a model-based OPC correction.

Compared with the existing method for finding the hot spot by adopting OPC verify, the method can realize the inspection of the OPC result without using an OPC model for simulation operation, and only carries out result inspection by comparing masks, namely the first corrected layout and the second corrected layout, so that OPC operation resources can be saved, the inspection time of the OPC hot spot graph is saved, the problem of rapid positioning is convenient and optimized, and the OPC development and optimization efficiency can be obviously improved in the OPC development and optimization.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a schematic diagram of layout graphs in each step of a conventional OPC correction hot spot graph inspection method;

FIG. 2 is a flowchart illustrating a hot spot pattern inspection method for OPC correction according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a layout graph in each step of the OPC corrected hot spot graph inspection method according to the embodiment of the invention;

FIG. 4 is a comparison of the runtime of an OPC corrected hotspot pattern inspection method of an embodiment of the present invention and the runtime of an existing OPC corrected hotspot pattern inspection method;

FIG. 5A is a layout graph difference diagram before optimization of parameters of OPC correction in the method for inspecting hot spot graphs for OPC correction according to the embodiment of the present invention;

fig. 5B is a layout graph difference diagram after optimization of parameters of OPC correction in the hot spot graph inspection method for OPC correction according to the embodiment of the present invention.

Detailed Description

FIG. 2 is a flow chart of a hot spot pattern inspection method for OPC correction according to an embodiment of the present invention; as shown in fig. 3, the method is a schematic diagram of a layout graph in each step of the OPC correction hot spot graph inspection method according to the embodiment of the present invention; the OPC correction hot spot pattern inspection method provided by the embodiment of the invention comprises the following steps:

firstly, performing OPC correction on an original layout 201 for N + M times to obtain a first corrected layout 202; n is the desired number of convergence times and M is the number of additional cycles. In fig. 3, the layouts are illustrated as a graph.

The first corrected layout 202 is used as a convergence target layout, and in fig. 2, the first corrected layout 202 is also represented by a convergence target Mask _ F.

In the embodiment of the present invention, the original layout 201 is a target layout, so that a target is also used to represent the original layout 201 in fig. 2.

Each time the OPC correction is a model-based (model) OPC correction. In fig. 2, N + M OPC corrections are also represented by Model corrections N + M times.

And step two, performing OPC correction on the original layout 201 for N times to obtain a second corrected layout 203.

In the embodiment of the invention, N is set according to the actual hierarchy and OPC correction difficulty during mass production, and the smaller the value of N is, the better the correction precision is. The second corrected layout 203 in fig. 3 is also represented by a number of mass production corrections Mask _ N.

In some preferred embodiments, the value of N ranges from 4< = N < =30.

The larger the value of M is, the better the correction result is, and the value range of M is 1< = M < =50.

And step three, carrying out difference check on the first corrected layout 202 and the second corrected layout 203 to obtain the layout graph difference.

In fig. 3, the overlay layout of the discrepancy check of said first corrected layout 202 and said second corrected layout 203 corresponding to a marker 204 is shown, wherein the layout pattern discrepancy is shown at block 205. The enlarged views of the layout pattern differences 205 are shown as

patterns

205a and 205b, respectively.

In the embodiment of the present invention, the difference check is implemented by performing an exclusive or logic operation on the first corrected layout 202 and the second corrected layout 203. In fig. 3, the disparity check is also represented by an XOR check.

In the embodiment of the present invention, the classification in step four includes:

dividing the error reporting value of the one-dimensional pattern EPE by the one-dimensional pattern MEEF to serve as a first-level boundary value; EPE represents the edge placement error and MEEF represents the reticle error enhancement factor.

In some embodiments, the OPC corrected hotspot pattern corresponding to the layout pattern difference is a one-dimensional hotspot pattern when the layout pattern difference is greater than the first-level boundary value and less than the second boundary value.

And when the difference of the layout graphs is greater than or equal to the second boundary value, the OPC corrected hot spot graph corresponding to the difference of the layout graphs is a two-dimensional hot spot graph.

In some embodiments, the range of the EPE deviation error reporting value of the one-dimensional pattern is greater than or equal to 0.1nm and less than or equal to 8nm.

The range of the EPE deviation error reporting value of the two-dimensional graph is more than or equal to 0.5nm and less than or equal to 15nm.

In some embodiments, further comprising:

and step five, if the hot spot graphs of the OPC correction completely disappear or are reduced to meet the requirement of mass production in the step four, taking the parameters of the OPC correction as the final parameters of the OPC correction. In the layout graph difference 205a in fig. 3, no difference or small difference is also shown, that is, the OPC correction hot spot patterns in the layout graph difference 205a completely disappear or are reduced to meet the requirement of mass production, that is, the OPC correction parameters meet the standard shown in fig. 3, that is, the OPC correction parameters meet the standard without further optimization, and can be directly used as the final parameters of the OPC correction.

If the OPC-corrected hot spot patterns in the fourth step do not meet the requirement of mass production, that is, the layout pattern difference 206 in the layout pattern difference 205b in fig. 3 is too large and does not meet the standard, at this time, parameters for OPC correction need to be optimized according to the OPC-corrected hot spot patterns, so that the layout pattern difference is reduced to an optimized direction. The optimization of the parameters for OPC corrections in fig. 3 is represented by an optimization correction script.

As shown in fig. 3, the first step is not repeated, that is, the first corrected layout 202 as the convergence target layout is not changed, and only the second corrected layout 202 is changed, that is, the optimized OPC corrected parameters are used to obtain the second corrected layout 202, so that the second corrected layout 202 and the first corrected layout 201 are closer to each other.

In some embodiments, after the above cycle step is completed, the method can further include:

and seventhly, performing OPC verification detection to confirm whether the final parameters of the OPC meet the correction requirements.

The seventh step comprises the following sub-steps:

and step 71, simulating the second corrected layout 203 obtained by adopting the final parameters of the OPC correction to obtain a simulated contour graph.

And step 72, comparing the simulation outline graph with the graph of the target layout to confirm whether the final parameters of the OPC correction meet the correction requirements or not.

Step seven is the same as the existing OPC correction hot spot pattern inspection method, a model is required to be adopted for simulation, and the step seven is an option or is only performed once or for a plurality of times. In addition, after the loop step before step six, even if step seven is selected, since the OPC-corrected hot spot pattern is substantially eliminated, the running time for performing step seven once is reduced.

Compared with the existing method for finding the hot spots by adopting the OPC verify, the embodiment of the invention can realize the detection of the OPC results without using an OPC model for simulation operation, and only compares masks, namely the first corrected layout 202 and the second corrected layout 203, to detect the results, thereby saving OPC operation resources, saving the OPC hot spot graph detection time, facilitating the rapid positioning and optimizing the problem, and obviously improving the OPC development and optimization efficiency in the OPC development and optimization.

FIG. 4 is a diagram illustrating a comparison between the running time of the hot-spot pattern inspection method for OPC correction according to the embodiment of the present invention and the running time of the existing hot-spot pattern inspection method for OPC correction, i.e. the existing OPC Verify inspection; in fig. 4, the running time of the OPC correction hot spot pattern inspection method is abbreviated as OPC inspection running time, and since OPC Verify adopts a plurality of CPUs for operation, in fig. 4, the OPC inspection running time is represented by OPC operation resources, which are the number of CPUs multiplied by the operation time, as shown by the column of the mark 301, and in fig. 4, the OPC operation resources of the existing OPC Verify are taken as a base number 1; as shown by the column labeled 302, the OPC computation resource of the method of the embodiment of the present invention is 2.07% of that of the conventional method, which can significantly save the OPC result checking computation time in the OPC development and optimization process and improve the efficiency.

The following further explains the embodiment of the present invention with reference to an OPC correction of an actual layout:

as shown in fig. 5A, the graph is a layout graph difference diagram before optimizing parameters of OPC correction in the hot spot graph inspection method for OPC correction according to the embodiment of the present invention; fig. 5A is an actual layout 204a corresponding to the layout 204 in fig. 3, where the layout 204a includes a plurality of layout pattern differences with different sizes, which are respectively marked with

marks

206a, 206b, and 206 c. Fig. 5B is a layout graph difference diagram after parameter optimization of OPC correction in the OPC correction hotspot graph inspection method according to the embodiment of the present invention.

The rationality of resources and time cost of OPC correction operation is considered, and the reasonable number range of OPC operation usually meeting the requirement of mass production is generally 4< = N < =30;

example (c): the Mask results of N =8 OPC operations and N + M =8+8=16 operations are XOR-compared.

The OPC hotspot graph searching and classifying are carried out according to the following steps:

step one, calculating N + M =8+8=16 times as an expected Mask correction result, and only calculating once and storing;

and step two, carrying out OPC operation for N =8 times.

And thirdly, performing exclusive OR (XOR) logic operation on the Mask result obtained by the N =8 times of OPC operation and the expected correction result.

Step four, as shown in fig. 5A, classifying the size of the Mask difference, classifying Mask differences of 3nm and-less XOR < =4nm as one-dimensional hot spot patterns, namely WP1, wherein XOR directly represents the size of the Mask difference; mask difference 4 nm-woven fabric XOR < =5nm is classified as a secondary hot spot pattern namely WPc, and Mask difference XOR >5nm is classified as a two-dimensional hot spot pattern namely WP2. In FIG. 5A, a one-dimensional hotspot pattern is represented by the mark 206a, a two-dimensional hotspot pattern is represented by the mark 206b, and a three-dimensional hotspot pattern is represented by the mark 206 c.

Step five, keeping the OPC operation times of N =8 times unchanged, and optimizing the operation parameters of OPC correction to continuously reduce the difference of expected Mask correction results as an optimization direction;

step six, as shown in fig. 5B, after continuously optimizing the correction configuration and details of the OPC, the XOR difference between the Mask result of N =8 OPC operations and the expected Mask correction result can be reduced to a low level. As shown in fig. 5B, after the parameter optimization of OPC, the hot spot patterns are reduced to only one type, and the number of the remaining three-dimensional hot spot patterns 206c is also greatly reduced to only a few.

And step seven, checking and confirming whether the correction requirements are met by using the traditional OPC Verify.

Therefore, the method provided by the embodiment of the invention can quickly locate the position of the hot spot graph by performing the difference check through the Mask, and classify the hot spot graph according to the XOR difference to obtain the hot spot graph classified according to the severity.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. An OPC correction hot spot pattern inspection method is characterized by comprising the following steps:

firstly, carrying out OPC correction on an original layout for N + M times to obtain a first corrected layout; n is the expected convergence time, M is the additional cycle time, and the first corrected layout is used as a convergence target layout;

step two, performing the OPC correction on the original layout for N times to obtain a second corrected layout;

thirdly, performing difference check on the first corrected layout and the second corrected layout to obtain a layout graph difference;

2. The OPC correction hotspot pattern inspection method of claim 1, further comprising:

3. The OPC correction hotspot pattern inspection method of claim 2, further comprising:

4. The OPC correction hotspot pattern inspection method of claim 3, wherein step seven comprises the substeps of:

step 71, simulating the second corrected layout obtained by adopting the final parameters of the OPC correction to obtain a simulated contour graph;

5. The OPC correction hotspot pattern inspection method of claim 4, wherein: the target layout adopts the original layout.

6. The OPC-corrected hot spot pattern inspection method of claim 1, wherein: and N is set according to the actual hierarchy and OPC correction difficulty during mass production, and the smaller the value of N is, the better the correction precision is.

7. The OPC correction hotspot pattern inspection method of claim 6, wherein: the value range of N is 4< = N < =30.

8. The OPC correction hotspot pattern inspection method of claim 7, wherein: the larger the value of M is, the better the correction result is, and the value range of M is 1< = M < =50.

9. The OPC correction hotspot pattern inspection method of claim 1, wherein: the difference check in step three is implemented by performing an exclusive or logic operation on the first corrected layout and the second corrected layout.

10. The OPC correction hotspot pattern inspection method of claim 1, wherein: the classification in step four includes:

dividing the error reporting value of the one-dimensional pattern EPE by the one-dimensional pattern MEEF to serve as a first-level boundary value; EPE represents edge placement error, MEEF represents reticle error enhancement factor;

dividing the EPE deviation error reporting value of the two-dimensional graph by the MEEF of the two-dimensional graph to serve as a secondary boundary value;

11. The OPC correction hotspot pattern inspection method of claim 10, wherein: the range of the EPE deviation error reporting value of the one-dimensional graph is more than or equal to 0.1nm and less than or equal to 8nm.

12. The OPC correction hotspot pattern inspection method of claim 10, wherein: the range of the EPE deviation error reporting value of the two-dimensional graph is more than or equal to 0.5nm and less than or equal to 15nm.

13. The OPC correction hotspot pattern inspection method of claim 10, wherein: and when the difference of the layout graphs is greater than the first-level boundary value and less than the second boundary value, the OPC corrected hot spot graph corresponding to the difference of the layout graphs is a one-dimensional hot spot graph.

14. The OPC correction hotspot pattern inspection method of claim 13, wherein: and when the difference of the layout graphs is greater than or equal to the second boundary value, the OPC corrected hot spot graph corresponding to the difference of the layout graphs is a two-dimensional hot spot graph.

15. The OPC correction hotspot pattern inspection method of claim 1, wherein: and each OPC correction in the first step and the second step is OPC correction based on a model.