CN115267504A

CN115267504A - System, method and device for detecting OC point of Efuse chip and readable medium

Info

Publication number: CN115267504A
Application number: CN202210919792.7A
Authority: CN
Inventors: 刘慧�
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-07-31
Filing date: 2022-07-31
Publication date: 2022-11-01

Abstract

The invention provides a system, a method, equipment and a readable medium for detecting OC points of an Efuse chip, wherein the system comprises: the first end of the switch chip is connected to a pull-down resistor of an OC point of the Efuse chip; the signal output end of the BMC chip is connected to the enabling end of the switch chip; the input end of the analog-digital converter is connected to the second end of the switch chip, and the output end of the analog-digital converter is connected to the BMC chip; and one end of the pull-up resistor is connected to the second end of the switch chip, and the other end of the pull-up resistor is connected to the power supply, wherein the switch chip is configured to communicate the first end with the second end by receiving an enable signal sent by the BMC chip. By using the scheme of the invention, the problem of abnormal functions caused by OC point setting after the board leaves the factory can be avoided, risks can be identified in advance, the automatic test coverage of the current board can be increased, and the quality of the board can be further improved.

Description

System, method and device for detecting OC point of Efuse chip and readable medium

Technical Field

The invention relates to the field of computers, in particular to a system, a method, equipment and a readable medium for detecting OC points of an Efuse chip.

Background

An Efuse (electronic fuse) chip is a power supply chip commonly used in a server system, and the output current of the chip can be limited by setting an OC point (over-current point) of the chip. A commonly used Efuse chip, such as MP5991, can set the OC point by configuring the resistance of the pull-down resistor of the corresponding pin.

The existing board card leaves the factory and has corresponding automatic test to detect the line or function on the board card, but the existing automatic test does not cover the detection of OC point setting of the eFuse chip, so that partial risks cannot be identified after the board card is manufactured. If the OC setting of the Efuse chip needs to be confirmed to be correct, the OC setting can be confirmed manually only by manually measuring the resistance value of the pull-down resistor. The manual measurement has errors and the test cannot be put into production line automation test. If the OC point of the Efuse chip is set to be in a problem, the output current of the chip is possibly insufficient, the power supply requirement of the functional module cannot be met, or the OC point is set to be too high, so that the current monitoring function of the Efuse cannot be achieved.

Disclosure of Invention

In view of this, embodiments of the present invention provide a system, a method, a device, and a readable medium for detecting an OC point of an Efuse chip, which can avoid a function abnormality and identify a risk in advance due to an OC point setting problem after a board leaves a factory, and increase a coverage of an automatic test of a current board, thereby further improving the quality of the board.

In view of the above object, an aspect of the embodiments of the present invention provides a system for detecting OC point of Efuse chip, including:

the first end of the switch chip is connected to a pull-down resistor of an OC point of the Efuse chip;

the signal output end of the BMC chip is connected to the enabling end of the switch chip;

the input end of the analog-digital converter is connected to the second end of the switch chip, and the output end of the analog-digital converter is connected to the BMC chip;

and one end of the pull-up resistor is connected to the second end of the switch chip, and the other end of the pull-up resistor is connected to the power supply, wherein the switch chip is configured to communicate the first end with the second end by receiving an enable signal sent by the BMC chip.

According to one embodiment of the invention, the voltage of the power supply is 3.3V.

According to an embodiment of the present invention, the pull-down resistor has a value range of 4 to 200K Ω, the value range of the pull-down resistor is calculated according to the voltage value of the power supply and the value range of the pull-down resistor, and the pull-up resistor is selected according to the calculated value range.

According to one embodiment of the present invention, the analog-to-digital converter is configured to acquire a voltage value and a current value of the pull-down resistor after the first terminal and the second terminal of the switch chip are connected, and calculate a resistance value of the pull-down resistor based on the acquired voltage value and current value.

In another aspect of the embodiments of the present invention, there is also provided a method for detecting OC point of Efuse chip, including the following steps:

sending an enabling signal to an enabling end of the switch chip through the BMC chip so as to enable the first end and the second end of the switch chip to be communicated;

acquiring a voltage value and a current value of a pull-down resistor at an OC point of the Efuse chip through an analog-digital converter, and transmitting the acquired voltage value and current value to the BMC chip;

the BMC chip calculates the resistance value of the pull-down resistor based on the received voltage value and current value, and judges whether the calculated resistance value of the pull-down resistor is correct or not;

and determining that the OC point of the Efuse chip is correctly set in response to the correct calculated resistance value of the pull-down resistor.

According to an embodiment of the present invention, further comprising:

and sending a corresponding warning to the mobile device of the administrator in response to the calculated resistance value of the pull-down resistor being incorrect.

According to an embodiment of the present invention, further comprising:

and setting a parameter comparison table of the pull-down resistor, wherein the comparison table comprises the resistance value, the divided voltage and the current value of the pull-down resistor under the preset voltage value and the preset dividing resistor.

According to an embodiment of the present invention, determining whether the calculated resistance value of the pull-down resistor is correct includes:

and matching the calculated resistance value of the pull-down resistor and the voltage value and the current value acquired by the analog-digital converter in a comparison table.

In another aspect of an embodiment of the present invention, there is also provided a computer apparatus including:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods described above.

In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program realizes the steps of any one of the above methods when executed by a processor.

The invention has the following beneficial technical effects: according to the system for detecting the OC point of the Efuse chip, provided by the embodiment of the invention, the first end of the switch chip is connected to the pull-down resistor of the OC point of the Efuse chip by arranging the switch chip; the signal output end of the BMC chip is connected to the enabling end of the switch chip; the input end of the analog-digital converter is connected to the second end of the switch chip, and the output end of the analog-digital converter is connected to the BMC chip; the pull-up resistor, the one end of pull-up resistor is connected to the second end of switch chip, and the other end is connected to the power, and wherein the switch chip configuration is received the enabling signal that the BMC chip sent and is held the technical scheme that communicates with first end and second, can avoid leading to the dysfunction at the integrated circuit board after dispatching from the factory because the OC point sets up the problem, discerns the risk in advance, can increase the automatic test coverage of current integrated circuit board to further promote the integrated circuit board quality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a system for OC point detection on an Efuse chip according to one embodiment of the invention;

FIG. 2 is a schematic flow chart of a method of Efuse chip OC point detection in accordance with one embodiment of the present invention;

FIG. 3 is a schematic diagram of a computer device according to one embodiment of the present invention;

FIG. 4 is a schematic diagram of a computer-readable storage medium according to one embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

In view of the above purpose, a first aspect of the embodiments of the present invention proposes an embodiment of a system for detecting an OC point of an Efuse chip, and fig. 1 shows a schematic diagram of the system.

As shown in fig. 1, the system may include:

and a first end of the switch chip is connected to a pull-down resistor at an OC point of the Efuse chip. When the test is not carried out, the switch chip is in a closed state, the eFuse chip is equivalently disconnected with the detection system, and the normal function of the eFuse chip cannot be influenced.

The signal output end of the BMC chip is connected to the enabling end of the switch chip. When the testing is needed, the signal output end of the BMC chip sends an enabling signal to the enabling end of the switch chip so as to conduct two ends of the switch chip, and therefore the pull-down resistor of the eFuse chip is connected to a testing system to be tested.

The voltage-dividing circuit further comprises an analog-digital converter (ADC), the input end of the ADC is connected to the second end of the switch chip, the output end of the ADC is connected to the BMC chip, and the ADC can acquire the voltage value and the current value of the pull-down resistor after voltage division of a voltage-dividing resistor arranged in the system and send the acquired voltage value and current value to the BMC chip.

The BMC chip is connected with the first end and the second end of the switch chip, and the pull-up resistor is connected with the second end of the switch chip and the other end of the switch chip. The pull-up resistor is a divider resistor, after the switch chip is switched on, the power supply is supplied to the circuit through the power supply, the power voltage is divided through the pull-up resistor and the pull-down resistor, and the voltage value and the current value of the pull-down resistor after voltage division are obtained through the analog-digital converter. At the beginning of the test, both terminals of the switch are turned on by calling the BMC related interface, i.e., the OC _ SW _ ENABLE signal shown in fig. 3 is asserted. After the switch is turned on, the pull-down resistor Roc for setting the OC point is connected to the detection system, the pull-down resistor Roc and the pull-up resistor Ru preset in the system divide the voltage of a power supply by 3.3V, wherein the resistance of the pull-up resistor Ru can be selected according to OC setting characteristics in an Efuse chip, for example, an MP5991 chip, the range of the resistance of the pull-down resistor which can be set is 4-200 kohm, and a proper pull-up resistor value is selected according to the range. The divided voltage is connected to an ADC voltage acquisition module, the module acquires the divided voltage and transmits voltage information to the BMC chip through an I2C bus. The corresponding relationship among the resistance, the current and the voltage set at the OC point of the chip also needs to be arranged in the form of the following table:

Roc	Ioc	divided voltage
			R1	I1	U1
R2	I2	U2
			R3	I3	U3
···	···	···

The BMC chip needs to write table information in advance, the information needs to include current limiting values corresponding to different pull-down resistance values and the number of divided voltage values after passing through preset divided resistors and voltages, meanwhile, a correct setting value in the table needs to be informed to the BMC to serve as a reference value, if an actual value is not within a reference range, fail is output according to a test result, meanwhile, roc resistance values set in the current state and corresponding currents are output, and if the actual value is within the set reference range, pass is output according to the test result.

By using the technical scheme provided by the invention, the problem of abnormal functions caused by OC point setting after the board boards leave the factory can be avoided, risks can be identified in advance, the automatic test coverage of the current board boards can be increased, and the quality of the board boards can be further improved.

In a preferred embodiment of the invention, the voltage of the power supply is 3.3V. Other voltage values may be used, but the reference values in the table need to be correspondingly modified.

In a preferred embodiment of the present invention, the value range of the pull-down resistor is 4 to 200K Ω, the value range of the pull-up resistor is calculated according to the voltage value of the power supply and the value range of the pull-down resistor, and the pull-up resistor is selected according to the calculated value range.

In a preferred embodiment of the present invention, the analog-to-digital converter is configured to acquire a voltage value and a current value of the pull-down resistor after the first terminal and the second terminal of the switch chip are connected, and calculate a resistance value of the pull-down resistor based on the acquired voltage value and current value. The resistance value of the pull-down resistor does not need to be calculated in the analog-digital converter, the acquired voltage value and the acquired current value can be sent to the BMC chip, and the resistance value of the pull-down resistor is calculated in the BMC chip.

The technical scheme of the invention has the following beneficial effects:

1. by adding a test for setting correctness of the OC point, the problem that the function is abnormal due to the setting problem after the board card leaves a factory is avoided, and risks are identified in advance;

2. configuration parameters in a test circuit can be flexibly set according to the characteristics of each chip;

3. in the automatic test of current integrated circuit board, can not test this setting, increase this test, can increase the automatic test coverage of current integrated circuit board to further promote the integrated circuit board quality.

It should be noted that, as can be understood by those skilled in the art, all or part of the processes in the methods of the embodiments described above can be implemented by instructing relevant hardware by a computer program, and the program may be stored in a computer-readable storage medium, and when executed, the program may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments corresponding thereto.

Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.

In view of the above object, according to a second aspect of the embodiments of the present invention, there is provided a method for detecting OC spot on an Efuse chip, as shown in fig. 2, the method includes the following steps:

sending an enabling signal to an enabling end of the switch chip through the BMC chip to enable the first end and the second end of the switch chip to be communicated;

In a preferred embodiment of the present invention, the method further comprises:

and setting a parameter comparison table of the pull-down resistor, wherein the parameter comparison table comprises the resistance value, the divided voltage and the current value of the pull-down resistor under the preset voltage value and the preset voltage dividing resistor.

In a preferred embodiment of the present invention, determining whether the calculated resistance value of the pull-down resistor is correct includes:

In view of the above object, a third aspect of the embodiments of the present invention provides a computer device. Fig. 3 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 3, an embodiment of the present invention includes the following means: at least one processor 21; and a memory 22, the memory 22 storing computer instructions 23 executable on the processor, the instructions when executed by the processor implementing the method of:

In a preferred embodiment of the present invention, the determining whether the calculated resistance value of the pull-down resistor is correct includes:

In view of the above object, a fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. FIG. 4 illustrates a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 4, the computer readable storage medium 31 stores a computer program 32 which, when executed by a processor, performs the method of:

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the above embodiments of the present invention are merely for description, and do not represent the advantages or disadvantages of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, where the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A system for detecting OC points of an eFuse chip comprises:

2. The system of claim 1, wherein the voltage of the power supply is 3.3V.

3. The system of claim 1, wherein the pull-down resistor has a value in a range of 4-200K Ω, the pull-up resistor is calculated based on the voltage value of the power supply and the value range of the pull-down resistor, and the pull-up resistor is selected based on the calculated value range.

4. The system of claim 1, wherein the analog-to-digital converter is configured to obtain a voltage value and a current value of the pull-down resistor after the first terminal and the second terminal of the switch chip are connected, and calculate the resistance value of the pull-down resistor based on the obtained voltage value and current value.

5. A method for detecting OC points of an Efuse chip is characterized by comprising the following steps:

acquiring a voltage value and a current value of a pull-down resistor at an OC point of the Efuse chip through an analog-digital converter, and transmitting the acquired voltage value and current value to a BMC chip;

6. The method of claim 5, further comprising:

7. The method of claim 5, further comprising:

8. The method of claim 7, wherein determining whether the calculated resistance of the pull-down resistor is correct comprises:

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 5 to 8.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 5 to 8.