CN1152583C - Reset controller and its implementation method - Google Patents

Abstract

The invention discloses a reset control circuit and a corresponding reset method, which are used for a main control board to reset and control a service board in a machine frame. The circuit at least includes: a backplane bus, a command sending circuit, a command receiving circuit and a dog circuit; The command sending circuit is set on the main control board and connected to the backplane bus, and is used to receive the reset command of the main control CPU and send it to the reset bus; the command receiving circuit and the dog circuit are set on each service board, and the command receiving circuit and the It is connected to the backplane bus, receives the reset command from the reset bus, and controls the dog circuit to perform the reset operation. The circuit enables the main control board to easily and reliably control the reset of the specified service board, and simultaneously saves the occupation of signal resources of pins on the backplane of the main control board.

Description

Reset control circuit and its realization method

technical field

The invention relates to the technical field of reset control, in particular to a circuit for a main control board to reset control a service board in a subrack and an implementation method thereof.

Background technique

As we all know, in the hardware design of the system, since the main control board is connected with all the service boards in the subrack, the pin signal resources on the backplane of the main control board are the most precious. Normally, the main control board adopts a star mode to reset and control the service boards in the subrack. As many service boards as there are in the subrack, the corresponding backplane pin signals of the main control board are occupied. That is to say, the main control board The signal pins occupied by the reset control of the board's backplane pins are one-to-one with the service board, which greatly wastes the signal resources of the main control board's backplane pins.

At present, there are also many devices that adopt the method of unified control and reset, but they are all controlled by the system software. The software sends a message to the corresponding service board to perform the reset operation. This method is no problem under normal working conditions, but When a certain service board causes a communication error due to a fault, or the communication is interrupted due to an abnormality in the main control system program of the service board, at this time, the communication between the service board and the main control board is already abnormal, and then reset by software It is impossible, because the working state of the service board has been wrong, it is likely that it cannot receive the software command, and cannot be reset normally, so the service board can only work again through manual reset, which will not only delay time, but also affect the equipment communication quality.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a reset control circuit, so that the main control board can control the reset of the designated service board at any time through a backplane bus, and at the same time save the backplane pin signal resources of the main control board.

Another object of the present invention is to provide a method for realizing the reset control of the main control board on the service board in the machine frame through the backplane bus, so that the realization is simpler and more reliable.

Above-mentioned purpose of the present invention is achieved through the following technical solutions:

A reset control circuit for the main control board to reset and control the service boards in the frame, including: a command sending circuit, a backplane bus, a command receiving circuit and a dog circuit; wherein,

The command sending circuit is arranged on the main control board, is connected with the main control CPU on the main control board, receives the reset command of the main control CPU, and is connected with the backplane bus, and is used to send the reset command to the corresponding service board;

The command receiving circuit and the dog circuit are set on each service board, the command receiving circuit is connected to the backplane bus, receives the reset command sent by the main control board from the backplane bus, and controls the dog circuit connected to it to reset the board. Reset operation.

The described command transmission circuit at least includes a CPU interface circuit, a verification generation circuit and a parallel/serial conversion circuit; the CPU interface circuit receives the reset command sent by the main control CPU, and provides it to the verification generation circuit connected thereafter for data verification. After verification, the verified data is converted into serial data through the parallel/serial conversion circuit and sent to the backplane bus. The command sending circuit may further include a synchronization and clock circuit, respectively connected to the verification generation circuit and the parallel/serial conversion circuit, for providing clock or maintaining synchronization.

The command receiving circuit at least includes a serial/parallel conversion circuit and a command processing circuit; the serial/parallel conversion circuit receives and connects to the reset bus, receives a reset command on the reset bus, converts the received serial data into parallel data, and sends The reset command is processed by the command processing circuit. The command receiving circuit may further include a synchronization and clock circuit for providing a clock or maintaining synchronization; a sampling decision circuit for sampling data with a local clock.

The command processing circuit at least includes an address comparison circuit, a verification detection circuit and a command interpretation circuit, which are used to compare, verify and interpret the received reset command, and the signal output from the command interpretation circuit is sent to the After the dog circuit.

The backplane bus is composed of one or more signal lines.

In the present invention, a method for implementing the above-mentioned reset control circuit to realize the reset of the service board in the frame by the main control board comprises at least the following steps:

a. The command sending circuit receives the command sent by the main control board CPU, performs verification and parallel/serial conversion, and sends the command data to the backplane bus;

b. The command receiving circuit receives the command on the backplane bus, and after serial/parallel conversion, sends it to the command processing circuit for processing;

c. In the command processing circuit, first judge whether the command is for the service board, if not, then discard, if yes, then judge whether the received command is valid; if the command is invalid, then discard, if the command is valid, the command The explanation circuit parses out the specific command;

d. If the reset command is analyzed, the command receiving circuit outputs a signal to the subsequent dog circuit to control the reset operation of the service board; otherwise, no operation is performed or the corresponding command parsed by the command interpretation circuit is executed.

It can be seen from the above-mentioned scheme that the key of the present invention is that the reset control is realized by hardware completely without involving any software, and the sending, receiving and execution of all reset commands are completed by the bottom hardware circuit, and the transmission of commands is through Realized in the form of backplane bus. Moreover, in the circuit design of the hardware, the receiving circuit for receiving commands and the dog circuit for executing command processing in each service board are separated from the main control system of the service board, even if the main control program inside the service board dies, It is also possible to reset the board by hardware to restore normal operation.

It can be seen that the backplane bus reset control circuit and its implementation method provided by the present invention use the backplane bus method to enable the main control board to perform reset control on all service boards in the frame, thereby greatly reducing the need for the main control board. The tightness of the backplane pin signal resources. At the same time, the reset control method is completely realized by the underlying hardware, and the command transmitted by the hardware contains the address information of the service board, so that it is not restricted by receiving software commands, and can reset the specified business at any time and in a directional manner. Board, more convenient and flexible to control.

Description of drawings

FIG. 1 is a schematic structural diagram of a backplane bus reset control circuit;

Fig. 2 is the structural representation of the order sending circuit of the present invention;

Fig. 3 is a structural schematic diagram of the command receiving circuit of the present invention;

4 is a schematic structural diagram of a reset command sending circuit in an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a reset command receiving circuit in an embodiment of the present invention.

Detailed ways

Below in conjunction with accompanying drawing, detailed technical content of the present invention is further described as follows:

Referring to FIG. 1 , the backplane bus reset control circuit of the present invention at least includes a command sending circuit 10 , a command receiving circuit 20 , a dog circuit 30 and a backplane bus 40 . Wherein, the command sending circuit 10 is arranged on the main control board, and is directly controlled by the main control CPU to send a reset command to the corresponding service board; a command receiving circuit 20 is arranged on each service board, and is used to receive the main control board through the backplane bus 40 sends a reset command to itself, and then the control dog circuit 30 performs reset control on the board. The order sending and receiving circuit can adopt the logic device design of programmable logic circuit (PLD), and the order sent includes content such as address field, order field and parity bit at least, and order can be sent by the method of multiple resent sampling, with Improve reliability.

The command sending circuit 10 is arranged in the main control board, and its basic structure is shown in FIG. Wherein, after the CPU interface circuit 11 receives the command sent by the CPU, it transfers to the verification generation circuit 12 to verify the data signal, and then sends it to the backplane bus 40 through the parallel/serial conversion circuit 13 . The circuit also includes a synchronization and clock circuit 14 for providing a clock or maintaining synchronization.

The command receiving circuit 20 is located in the service board, and its basic structure is shown in FIG. 3 , including at least a serial/parallel conversion circuit 21 and a command processing circuit 22 . The serial/parallel conversion circuit 21 first receives the command sent by the reset bus 40, performs serial/parallel conversion and then sends it to the command processing circuit 22 for processing, and then the command receiving circuit 20 controls the dog circuit 30 in the service board to perform a corresponding reset deal with. If the reset bus works in the asynchronous clock mode, a sampling decision circuit 23 needs to be added before the serial/parallel conversion to sample data using the local clock. The circuit also includes a synchronization and clock circuit 24 for providing a clock or maintaining synchronization.

The command processing circuit 22 includes three parts: an address comparison circuit 221 , a verification detection circuit 222 and a command interpretation circuit 223 . The address comparison circuit 221 judges according to the address information in the command whether it is the reset control of the board, if yes, checks; if not, discards. The verification detection circuit 222 is used to judge whether the received command is valid. If the verification is correct, it indicates that the command is valid, then it is handed over to the command interpretation circuit 223 for processing; if the verification error indicates that the received command is invalid, it is directly discarded. Command interpreting circuit 223 explains order, if what receive is reset order, then output low level pulse and make dog circuit 30 actions in the board reset this board; Make any action; if an extended command is defined at this time, then execute the corresponding command action deciphered by the command interpretation circuit 223.

The clock mode of the reset bus 40 can be synchronous or asynchronous, and the definition of the signal is determined by the clock mode. When the reset bus adopts the synchronous mode, the backplane defines the clock signal, the clock is provided by the main control board, and the receiving circuits of all service boards use the clock provided by the main control board; when the reset bus adopts the asynchronous mode, since the clock signal, the command receiving circuit of the service board needs to add a detection circuit similar to the asynchronous serial port to sample and judge the data, and the corresponding command format definition also needs to add a start bit and an optional stop bit flag.

The format and length of the command sent can be flexibly defined, and the check form can also be selected arbitrarily, but it must include three parts: the service board address field, the command field and the check digit. If the asynchronous clock mode is used, it is necessary to increase the start bit flag, and whether to increase the stop bit is optional. The specific format of the command is shown in Table 1, and the undefined part of the command field can be extended and used. By defining the extended part of the command field, this bus can be extended to execute other similar commands, such as: instructing a certain service board to sleep and wake up commands.

Table 1 command format start bit Business board address field command field Check Digit stop bit

In summary, the design of the backplane bus control circuit mainly involves the following three parts:

1) Design of the backplane bus. The bus can be composed of 1, 2, 3, 4 or more signal lines, mainly based on the design complexity of the reset signal sending and receiving circuit and the tightness of the backplane signal resources; the clock synchronization method can also be based on the actual The needs are determined.

2) Reset command format definition. It includes at least an address field, a command field and a parity bit, and when the asynchronous clock mode is used, a start bit and a stop bit are added.

3) Structural design of command sending circuit and command receiving circuit.

Referring to Fig. 4 and Fig. 5, the present invention will be further described with a specific embodiment. This embodiment adopts synchronous reset control of two backplane buses.

The applied system environment is: each chassis has 16 slots, including 2 main control boards and 14 service boards. The two main control boards work in the dual-system backup mode. All service boards can only receive reset commands initiated by the active main control board, and the standby main control board is not allowed to send reset commands.

First, determine the signal definition of the backplane reset bus. Since this embodiment is a reset bus for synchronous clocks, the two signals are respectively defined as data (DAT) and clock (CLK), the main control board is the master, and the service board is the slave.

Then, determine the format of the reset command. Due to the synchronous clock mode, the start bit and end bit in the reset command are unnecessary; the addresses of the 14 service board slots only need to be represented by 4Bit; the command field is defined as 3Bit, where [000]B means the reset command, The rest of the command codes are reserved; the parity bit can use a simple 1Bit parity check. In this way, the format of the 2-wire synchronous reset bus command is shown in Table 2:

Table 2 2-wire synchronous reset bus command format Service board address field (4 bits) Command field (3 bits) Check digit (1 digit)

Finally, determine the design of the command sending circuit and receiving circuit. Since the two main control boards work in dual-machine backup mode, the reset command sending circuit of the main control board needs to introduce the main and standby status signals to control the output of the reset command, as shown in Figure 4. The command sending circuit 10 sends two signals of DAT and CLK to the backplane reset bus 40 at the same time, and the command receiving circuit 20 receives these two signals at the same time, wherein the DAT signal is converted in the serial/parallel conversion circuit 21, and the command processing circuit 22 After the post-command processing, the dog circuit 30 performs a reset operation on the service board; and the CLK signal is sent to the synchronization and clock circuit 24 to synchronize the clock, as shown in FIG. 5 .

The backplane reset bus control circuit and its implementation method can alleviate the tension of the backplane pin signal resources of the main control board, and its specific implementation can be synthesized according to the design complexity of the sending and receiving circuits and the tension of the backplane signal resources. Evaluate and give an appropriate design.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (12)

1. A reset control circuit, which is used for the main control board to reset the service boards in the frame, and is characterized in that the circuit at least includes: a command sending circuit, a backplane bus, a command receiving circuit and a dog circuit; wherein, The command sending circuit is arranged on the main control board, is connected with the main control CPU on the main control board, receives the reset command of the main control CPU, and is connected with the backplane bus, and is used to send the reset command to the corresponding service board; The command receiving circuit and the dog circuit are set on each service board, the command receiving circuit is connected to the backplane bus, receives the reset command sent by the main control board from the backplane bus, and controls the dog circuit connected to it to reset the board. Reset operation. 2. The reset control circuit according to claim 1, wherein said backplane bus is composed of one or more signal lines. 3. The reset control circuit according to claim 1, characterized in that: the command sending circuit at least includes a CPU interface circuit, a verification generation circuit and a parallel/serial conversion circuit; the CPU interface circuit receives the command sent by the main control CPU The reset command is provided to the verification generation circuit connected thereafter for data verification, and the verified data is converted into serial data by the parallel/serial conversion circuit and sent to the backplane bus. 4. The reset control circuit according to claim 3, characterized in that: said command sending circuit further includes a synchronization and clock circuit, respectively connected to the verification generation circuit and the parallel/serial conversion circuit, for providing clock or keep in sync. 5. The reset control circuit according to claim 1, characterized in that: the command receiving circuit at least includes a serial/parallel conversion circuit and a command processing circuit; the serial/parallel conversion circuit is connected to the reset bus for receiving The reset command of the received serial data is converted into parallel data and sent to the command processing circuit to process the reset command. 6. The reset control circuit according to claim 5, wherein the command receiving circuit further comprises a synchronization and clock circuit for providing a clock or maintaining synchronization. 7. The reset control circuit according to claim 5, characterized in that: said command processing circuit at least includes an address comparison circuit, a verification detection circuit and a command interpretation circuit for comparing and correcting the received reset command. Checking and interpretation processing, the signal output from the command interpretation circuit is sent into the dog circuit connected thereafter. 8. The reset control circuit according to claim 5 or 6, characterized in that the command receiving circuit further includes a sampling decision circuit for sampling data with a local clock. 9. The reset control circuit according to claim 1, wherein the clock mode of the backplane bus is a synchronous mode or an asynchronous mode. 10. A method for using a reset control circuit to realize that the main control board resets the service boards in the machine frame. The reset control circuit at least includes: a command sending circuit, a backplane bus, a command receiving circuit and a dog circuit, characterized in that the The method at least includes the following steps: a. The command sending circuit receives the command sent by the main control board CPU, performs verification and parallel/serial conversion, and sends the command data to the backplane bus; b. The command receiving circuit receives the command on the backplane bus, and after serial/parallel conversion, sends it to the command processing circuit for processing; c. In the command processing circuit, first judge whether the command is for the service board, if not, then discard, if yes, then judge whether the received command is valid; if the command is invalid, then discard, if the command is valid, the command The explanation circuit parses out the specific command; d. If the reset command is analyzed, the command receiving circuit outputs a signal to the subsequent dog circuit to control the reset operation of the service board; otherwise, no operation is performed or the corresponding command parsed by the command interpretation circuit is executed. 11. The implementation method according to claim 10, wherein the command at least consists of an address field, a command field and a check digit, and the address field is the address of the service board to be reset. 12. The implementation method according to claim 11, characterized in that the command further includes a start bit, or a start bit and a stop bit.

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