CN1152583C - Reset controller and its implementation method - Google Patents
Reset controller and its implementation method Download PDFInfo
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- CN1152583C CN1152583C CNB011296313A CN01129631A CN1152583C CN 1152583 C CN1152583 C CN 1152583C CN B011296313 A CNB011296313 A CN B011296313A CN 01129631 A CN01129631 A CN 01129631A CN 1152583 C CN1152583 C CN 1152583C
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Abstract
The present invention discloses a reset control circuit and a relevant reset method, which is used for a master control board to control the reset of service boards in a machine frame. The circuit at least comprises a backboard bus, a command sending circuit, command receiving circuits and watchdog circuits, wherein the command sending circuit is arranged on the master control board, is connected with the backboard bus, and is used for receiving a reset command of a main control CPU and for sending the reset command to a reset bus; the command receiving circuits and the watchdog circuits are arranged on all the service boards, and the command receiving circuits are connected with the backboard bus and are used for receiving the reset command transmitted from the reset bus and for controlling the watchdog circuits to execute reset operation. The circuit can enable the master control board to control the reset of the specified service boards simply, conveniently and reliably, and a signal resource occupied by backboard pins of the master control board is saved at the same time.
Description
Technical Field
The invention relates to the technical field of reset control, in particular to a circuit for performing reset control on a service board in a plug-in box by a main control board and an implementation method thereof.
Background
As is well known, in the hardware design of the system, since the main control board is connected to all the service boards in the plug frame, the backplane pin signal resources of the main control board are the most valuable. Under the general condition, the main control board adopts a star-shaped mode to carry out reset control on the service boards in the plug-in frame, and the number of the back board contact pins corresponding to the main control board is occupied when the number of the service boards is in the frame, that is to say, the signal pins occupied by the reset control in the back board contact pins of the main control board are one-to-one with the service boards, so that the back board contact pin signal resources of the main control board are greatly wasted.
At present, a plurality of devices adopt a unified control reset mode, but are controlled by system software, and the software sends a message to a corresponding service board for reset operation, the method has no problem under the normal working condition, but when a certain service board causes communication error due to failure or communication interruption due to the abnormal program of a main control system of the service board, at the moment, the communication between the service board and the main control board is already abnormal, and the software reset is impossible, because the working state of the service board has been wrong, the software command can not be received possibly, and the normal reset can not be carried out, so that the service board can only be reset manually, the time is delayed, and the communication quality of the devices is influenced.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a reset control circuit, so that a main control board can control a designated service board to reset through a backplane bus at any time, and simultaneously, backplane pin signal resources of the main control board are saved.
Another objective of the present invention is to provide a method for implementing the reset control of the main control board to the service board in the machine frame through the backplane bus, so that the implementation is simpler and more reliable.
The above purpose of the invention is realized by the following technical scheme:
a reset control circuit for a main control board to reset and control a service board in a machine frame comprises: the device comprises a command sending circuit, a backboard bus, a command receiving circuit and a dog circuit; wherein,
the command sending circuit is arranged on the main control board, is connected with the main control CPU on the main control board, receives the reset command of the main control CPU, is connected with the back board bus and is used for sending the reset command to the corresponding service board;
the command receiving circuit and the dog circuit are arranged on each service board, the command receiving circuit is connected with the back board bus, receives the reset command sent by the main control board from the back board bus, and controls the dog circuit connected behind the command receiving circuit to reset the local board.
The command transmitting circuit at least comprises a CPU interface circuit, a verification generating circuit and a parallel/serial conversion circuit; the CPU interface circuit receives the reset command sent by the main control CPU, provides the reset command for the verification generating circuit connected behind the CPU interface circuit to carry out data verification, and the verified data is converted into serial data through the parallel/serial conversion circuit and sent to the backboard bus. The command transmitting circuit may further include a synchronization and clock circuit connected to the verification generating circuit and the parallel/serial conversion circuit, respectively, for providing a clock or maintaining synchronization.
The command receiving circuit at least comprises a serial/parallel conversion circuit and a command processing circuit; the serial/parallel conversion circuit receives a reset command connected with the reset bus, receives the reset command on the reset bus, converts the received serial data into parallel data and sends the parallel data to the command processing circuit to process the reset command. The command receiving circuit can further comprise a synchronization and clock circuit for providing a clock or maintaining synchronization; and the sampling decision circuit is used for sampling data by using a local clock.
The command processing circuit at least comprises an address comparison circuit, a verification detection circuit and a command interpretation circuit, and is used for carrying out comparison, verification and interpretation processing on the received reset command, and a signal output from the command interpretation circuit is sent to a subsequent dog circuit.
The backboard bus consists of one or more signal lines.
The invention relates to a method for realizing the reset of a service board in a machine frame by a main control board by applying the reset control circuit, which at least comprises the following steps:
a. the command sending circuit receives a command sent by the main control board CPU, checks and carries out parallel/serial conversion, and then sends the command data to the back board bus;
b. the command receiving circuit receives the command on the backboard bus, and after serial/parallel conversion, the command is sent to the command processing circuit for processing;
c. in the command processing circuit, firstly, judging whether the command is a business board, if not, discarding, and if so, judging whether the received command is effective; if the command is invalid, discarding, if the command is valid, analyzing the specific command by the command interpretation circuit;
d. if the analyzed reset command is the reset command, the command receiving circuit outputs a signal to a subsequent dog circuit to control the reset operation of the service board; otherwise, no operation is performed or the corresponding command parsed by the command interpretation circuit is executed.
The key point of the invention is that: the reset control is realized completely by adopting a hardware mode, no software is involved, all the sending, receiving and execution of the reset command are completed by the hardware circuit at the bottommost layer, and the transmission of the command is realized by a backboard bus form. In addition, in the circuit design of hardware, a receiving circuit for receiving the command and a dog circuit for executing the command processing in each service board are separated from a main control system of the service board, and even if a main control program in the service board is dead, the board can be reset in a hardware mode to enable the board to recover the normal operation.
Therefore, the backboard bus reset control circuit and the realization method thereof provided by the invention have the advantages that the main control board carries out reset control on all the service boards in the frame in a backboard bus mode, so that the tension degree of the signal resources of the backboard contact pins of the main control board is greatly relieved. Meanwhile, the reset control method is completely realized by bottom hardware, and the command transmitted by the hardware is provided with the address information of the service board, so that the reset control method is not limited by the received software command, and the appointed service board can be reset at any time and directionally, and the control is more convenient and flexible.
Drawings
FIG. 1 is a schematic structural diagram of a backplane bus reset control circuit;
FIG. 2 is a schematic diagram of a command transmitting circuit according to the present invention;
FIG. 3 is a schematic diagram of a command receiving circuit according to the present invention;
FIG. 4 is a schematic diagram of a reset command transmitting circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a reset command receiving circuit according to an embodiment of the invention.
Detailed Description
The detailed technical content of the invention is further explained by the following figures:
referring to fig. 1, the backplane bus reset control circuit of the present invention at least includes a command sending circuit 10, a command receiving circuit 20, a dog circuit 30, and a backplane bus 40. The command sending circuit 10 is arranged on the main control board, and the main control CPU directly controls to send a reset command to the corresponding service board; each service board is provided with a command receiving circuit 20 for receiving a reset command sent by the main control board to the service board through a backplane bus 40, and then controlling a dog circuit 30 to perform reset control on the service board. The command transmitting and receiving circuit can adopt the logic device design of a programmable logic circuit (PLD), the transmitted command at least comprises the contents of an address field, a command field, a check bit and the like, and the command can be transmitted by adopting a method of repeated sampling to improve the reliability.
The command transmitting circuit 10 is disposed in the main control board, and its basic structure is as shown in fig. 2, and includes at least a CPU interface circuit 11, a verification generating circuit 12, and a parallel/serial conversion circuit 13. After receiving the command sent by the CPU, the CPU interface circuit 11 forwards the command to the verification generating circuit 12 to verify the data signal, and then sends the data signal to the backplane bus 40 through the parallel/serial conversion circuit 13. Also included in the circuit is a synchronization and clock circuit 14 for providing a clock or maintaining synchronization.
The command receiving circuit 20 is located in the service board, and its basic structure is shown in fig. 3, and includes at least a serial/parallel conversion circuit 21 and a command processing circuit 22. The serial/parallel conversion circuit 21 first receives the command transmitted from the reset bus 40, performs serial/parallel conversion, and then transmits the command to the command processing circuit 22 for processing, and then the command receiving circuit 20 controls the dog circuit 30 in the service board to perform corresponding reset processing. If the reset bus is operating in asynchronous clock mode, a sampling decision circuit 23 is added to sample the data using the local clock before serial/parallel conversion. Also included in the circuit is a synchronization and clock circuit 24 for providing a clock or maintaining synchronization.
The command processing circuit 22 includes three parts, namely an address comparison circuit 221, a check detection circuit 222 and a command interpretation circuit 223. The address comparison circuit 221 judges whether the reset control is performed on the board according to the address information in the command, and if so, checks; if not, it is discarded. The check detecting circuit 222 is used to determine whether the received command is valid, and if the check indicates that the command is valid, the command is handed to the command interpreting circuit 223 for processing; if the check error indicates that the received command is invalid, it is discarded directly. The command interpretation circuit 223 interprets the command, and if the received command is a reset command, outputs a low level pulse to make the dog circuit 30 in the board act to reset the board; if the command is not a reset command and the extended command definition does not exist at the moment, no action is taken; if an extended command is defined at this time, the corresponding command operation decoded by the command interpreting circuit 223 is executed.
The clock mode of the reset bus 40 may be synchronous or asynchronous, with the definition of the signals being determined by the clock mode. When the reset bus adopts a synchronous mode, the back board defines a clock signal, the clock is provided by the main control board, and the receiving circuits of all the service boards use the clock provided by the main control board; when the reset bus adopts an asynchronous mode, because the back board does not define a clock signal, a detection circuit similar to an asynchronous serial port is needed to be added in a command receiving circuit of the service board to perform sampling judgment on data, and a start bit and an optional stop bit mark also need to be added in the corresponding command format definition.
The format and command length of the transmitted command can be flexibly defined, and the checking form can be arbitrarily selected, but the format and the checking form must include three parts, namely a service board address field, a command field and a checking bit. If asynchronous clock mode is used, it is also necessary to add a start bit flag, but whether to add a stop bit is optional. The specific format of the command is shown in table one, and the undefined part in the command field can be used in an extended way. By defining the extension of the command field, the bus can be extended to perform other similar commands, such as: a sleep command, a wake-up command, etc. indicating a certain service board.
Table-command format
| Start bit | Service board address field | Command field | Check bit | Stop position |
In summary, the design of the backplane bus control circuit mainly involves the following three parts:
1) design of backplane bus. The bus can be composed of 1, 2, 3, 4 or more signal lines, which is mainly determined according to the design complexity of the reset signal sending and receiving circuit and the tension degree of the backboard signal resources; the clock synchronization mode can also be determined according to actual requirements.
2) The reset command format definition. At least including address field, command field and check bit, when adopting asynchronous clock mode, adding start bit and selecting stop bit.
3) The structure design of the command transmitting circuit and the command receiving circuit.
Referring to fig. 4 and 5, the present invention will be further described with reference to an embodiment. This embodiment employs a synchronous reset control of 2 backplane buses.
The applied system environment is: each machine frame has 16 slots, wherein 2 slots are a master control board and 14 service boards. The 2 main control boards work in a dual-machine backup mode, all the service boards can only receive the reset command initiated by the main control board, and the standby main control board does not allow to send the reset command.
First, the signal definition of the backplane reset bus is determined. Since this embodiment is a reset bus that synchronizes clocks, 2 signals are defined as Data (DAT) and Clock (CLK), respectively, the master board is the master, and the service board is the slave.
Then, the format of the reset command is determined. Because of adopting the synchronous clock mode, the start bit and the end bit in the reset command are not needed; the addresses of the 14 service board slots can be represented by only 4 bits; the command field is defined as 3 bits, where [000] B represents a reset command, and the remaining command codes are reserved; the check bits may use a simple 1Bit parity check. Thus, the format of the 2-wire synchronous reset bus command is shown in table two:
TABLE 2 line synchronous reset bus Command Format
| Service board address field (4 bit) | Command field (3 bit) | Check digit (1 position) |
Finally, the design of the command transmitting circuit and the receiving circuit is determined. Since 2 main control boards work in the dual-host backup mode, the reset command sending circuit of the main control board needs to introduce the main/standby state signals to control the output of the reset command, as shown in fig. 4. The command transmitting circuit 10 simultaneously transmits two signals of DAT and CLK to the backplane reset bus 40, and the command receiving circuit 20 simultaneously receives the two signals, wherein the DAT signal is converted in the serial/parallel conversion circuit 21, and after the post command processing is performed in the command processing circuit 22, the dog circuit 30 performs the reset operation on the service board; the CLK signal is fed into synchronization and clock circuit 24 for synchronizing the clocks, as shown in FIG. 5.
The backboard reset bus control circuit and the realization method thereof can relieve the tension degree of backboard contact pin signal resources of the main control board, and during the concrete realization, the comprehensive evaluation can be carried out according to the design complexity degree of the sending and receiving circuit and the tension degree of the backboard signal resources, and the proper design is given.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (12)
1. A reset control circuit is used for a main control board to reset and control a service board in a machine frame, and is characterized by at least comprising: the device comprises a command sending circuit, a backboard bus, a command receiving circuit and a dog circuit; wherein,
the command sending circuit is arranged on the main control board, is connected with the main control CPU on the main control board, receives the reset command of the main control CPU, is connected with the back board bus and is used for sending the reset command to the corresponding service board;
the command receiving circuit and the dog circuit are arranged on each service board, the command receiving circuit is connected with the back board bus, receives the reset command sent by the main control board from the back board bus, and controls the dog circuit connected behind the command receiving circuit to reset the local board.
2. The reset control circuit of claim 1, wherein: the backboard bus consists of one or more signal lines.
3. The reset control circuit of claim 1, wherein: the command transmitting circuit at least comprises a CPU interface circuit, a verification generating circuit and a parallel/serial conversion circuit; the CPU interface circuit receives the reset command sent by the main control CPU, provides the reset command for the verification generating circuit connected behind the CPU interface circuit to carry out data verification, and the verified data is converted into serial data through the parallel/serial conversion circuit and sent to the backboard bus.
4. The reset control circuit of claim 3, wherein: the command transmitting circuit further comprises a synchronization and clock circuit which is respectively connected with the verification generating circuit and the parallel/serial conversion circuit and used for providing a clock or keeping synchronization.
5. The reset control circuit of claim 1, wherein: the command receiving circuit at least comprises a serial/parallel conversion circuit and a command processing circuit; the serial/parallel conversion circuit receives a reset command connected with the reset bus, receives the reset command on the reset bus, converts the received serial data into parallel data and sends the parallel data to the command processing circuit to process the reset command.
6. The reset control circuit of claim 5, wherein: the command receiving circuit further comprises a synchronization and clock circuit for providing a clock or maintaining synchronization.
7. The reset control circuit of claim 5, wherein: the command processing circuit at least comprises an address comparison circuit, a verification detection circuit and a command interpretation circuit, and is used for carrying out comparison, verification and interpretation processing on the received reset command, and a signal output from the command interpretation circuit is sent to a subsequent dog circuit.
8. The reset control circuit according to claim 5 or 6, wherein: the command receiving circuit may further include a sampling decision circuit for sampling data with a local clock.
9. The reset control circuit of claim 1, wherein: the clock mode of the backplane bus is either synchronous mode or asynchronous mode.
10. A method for implementing a main control board to reset a service board in a machine frame by applying a reset control circuit, wherein the reset control circuit at least comprises: the method comprises a command sending circuit, a backboard bus, a command receiving circuit and a dog circuit, and is characterized by at least comprising the following steps:
a. the command sending circuit receives a command sent by the main control board CPU, checks and carries out parallel/serial conversion, and then sends the command data to the back board bus;
b. the command receiving circuit receives the command on the backboard bus, and after serial/parallel conversion, the command is sent to the command processing circuit for processing;
c. in the command processing circuit, firstly, judging whether the command is a business board, if not, discarding, and if so, judging whether the received command is effective; if the command is invalid, discarding, if the command is valid, analyzing the specific command by the command interpretation circuit;
d. if the analyzed reset command is the reset command, the command receiving circuit outputs a signal to a subsequent dog circuit to control the reset operation of the service board; otherwise, no operation is performed or the corresponding command parsed by the command interpretation circuit is executed.
11. The implementation method of claim 10, wherein: the command at least comprises an address field, a command field and a check bit, wherein the address field is the address of the service board needing to be reset.
12. The implementation method of claim 11, wherein: the command may further include a start bit, or a start bit and a stop bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011296313A CN1152583C (en) | 2001-06-25 | 2001-06-25 | Reset controller and its implementation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011296313A CN1152583C (en) | 2001-06-25 | 2001-06-25 | Reset controller and its implementation method |
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| CN1394085A CN1394085A (en) | 2003-01-29 |
| CN1152583C true CN1152583C (en) | 2004-06-02 |
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| CNB011296313A Expired - Fee Related CN1152583C (en) | 2001-06-25 | 2001-06-25 | Reset controller and its implementation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645981B (en) * | 2008-08-05 | 2011-11-30 | 中兴通讯股份有限公司 | Intelligent platform management interface resetting system and method thereof |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361047C (en) * | 2004-08-29 | 2008-01-09 | 华为技术有限公司 | Method and apparatus for raising reliability of bus transmission |
| CN101197851B (en) * | 2008-01-08 | 2010-12-08 | 杭州华三通信技术有限公司 | Method and system for implementing control of plane centralized type data plane distribution |
| CN101997815B (en) * | 2009-08-20 | 2013-01-02 | 华为技术有限公司 | Exception recovery device and method of serial and parallel conversion interface |
| CN105488010B (en) * | 2016-01-06 | 2018-11-23 | 东阳市前途工业设计有限公司 | A kind of backboard real-time synchronization interface protocol |
| CN112051913A (en) * | 2020-09-11 | 2020-12-08 | 深圳市信锐网科技术有限公司 | Device resetting method and device on board card, logic device and storage medium |
| CN112910590B (en) * | 2021-01-28 | 2022-10-21 | 广州广哈通信股份有限公司 | Clock synchronization system and method |
-
2001
- 2001-06-25 CN CNB011296313A patent/CN1152583C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645981B (en) * | 2008-08-05 | 2011-11-30 | 中兴通讯股份有限公司 | Intelligent platform management interface resetting system and method thereof |
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| CN1394085A (en) | 2003-01-29 |
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Granted publication date: 20040602 Termination date: 20170625 |