CN1152580C - Digital convergence correcting device and display device - Google Patents

Digital convergence correcting device and display device Download PDF

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Publication number
CN1152580C
CN1152580C CNB971824002A CN97182400A CN1152580C CN 1152580 C CN1152580 C CN 1152580C CN B971824002 A CNB971824002 A CN B971824002A CN 97182400 A CN97182400 A CN 97182400A CN 1152580 C CN1152580 C CN 1152580C
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display area
vertical
signal
horizontal
picture
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CN1276128A (en
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中l雄史
中條雄史
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Enyixi Mitsubishi Electric Video Co., Ltd.
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Enyixi Mitsubishi Electric Video Co Ltd
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Abstract

The present invention solves the problem that the correction accuracy of a digital convergence correcting device can not be prevented from being reduced when the relationship between the effective area of an optical grating of a screen and the effective area of a picture varies. A vertical display area detecting signal corresponding to the position of the display area of the picture on the screen in the vertical direction is generated according to a vertical deflection current. An address counter for generating an address for reading out corrected data is controlled according to the signal.

Description

Digital convegence correcting device and display unit
Technical field
The present invention relates to a kind of convergence correction technology, particularly a kind of digital convegence correcting device.
Background technology
In general, in digital convegence correcting device, a plurality of points on the CRT screen are created as the convergence correction point, and obtain the convergence correction amount of each convergence correction point in advance, and be stored in the memory as correction data.Then, synchronously read correction data, and the data transaction of reading is become an analog signal from memory with screen scanning.Then, pass through to insert convergence correction signal of (smoothly) analogue signal generating, and drive the convergence yoke coil (CY coil) of CRT by means of a low pass filter.
The convergence correction amount is a value of determining according to a position on the CRT screen.In other words, the position on convergence correction amount and the CRT screen is with 1 pair 1 relation corresponding (interrelating).Therefore, predetermined a plurality of convergence correction points, so as corresponding with 1 pair 1 relation with the position on the CRT screen, and with respect to each convergence correction point, the convergence correction amount that obtains in advance is stored in the memory as correction data.
Thereby, if be the picture of the effective viewing area on the CRT screen effective area, and be that relation between the screen grating of the scanning area on the CRT screen changes, then produce such problem here: with the correction data that screen scanning is read synchronously can not be corresponding with the convergence correction point on the CRT screen.
For example, even a kind of like this problem is also producing under the following situation: the screen grating amplifies on the overscanning direction and reduces on the underdevelopment direction; Perhaps the aspect ratio of screen grating changes; Perhaps the screen grating is horizontal or vertical mobile in the effective area of picture.Particularly, in the display unit of the picture signal that can import the different scanning frequency, because the variation of deflection frequency, the relation between the effective area of screen grating and CRT picture may change.Under such a case, can not suitably carry out convergence correction.
Japan's publication publication (not examination) is even No.33791/1985 discloses the digital convegence correcting device that also can carry out convergence correction when a kind of relation between the effective area of screen grating and CRT picture changes.This convegence correcting device comprises the memory and the low pass filter that is used for each scanning frequency that are used for storing the correction data that is used for each scanning frequency, and the scanning frequency of the picture signal by detecting input and use with the corresponding memory of scanning frequency and a low pass filter of detecting by selecting.
Yet,, must on the CRT screen, provide a large amount of convergence correction points in order suitably to carry out convergence correction.In order to store the correction data that is used for each convergence correction point, need a mass storage.Thereby such problem is arranged: the convegence correcting device that such memory that is used for each scanning frequency is housed is expensive, and display unit is also expensive.
The another one problem is arranged: as the result who provides with the corresponding low pass filter of each scanning frequency, circuit complicated, and therefore convegence correcting device is expensive, and display unit is more expensive.
Moreover, in a kind of so conventional convegence correcting device, because the relation between screen grating and picture effective area is stipulated by scanning frequency, if so when importing the picture signal of a same scan frequency, relation between the effective area of screen grating and CRT picture is different, the another one problem is then arranged: can not suitably carry out any convergence correction.
On the other hand, Japanese public publication (not examination) No.20809/1995 discloses a kind of picture signal to the different scanning frequency and has carried out digital convegence correcting device convergence correction, that cost is more suitable.In this convegence correcting device, need not be synchronous with screen scanning, read correction data by means of some cycles from a memory.Thereby even any picture signal of input different scanning frequency, the time interval that is used for reading correction data also can be a constant, and need not change any low pass filter, might be corresponding to the picture signal of different frequency.In other words, because this convegence correcting device only comprises a low pass filter, can be so might provide corresponding to the convegence correcting device different scanning frequency, that cost is more suitable.Yet, need the problems referred to above of a mass storage still unresolved.Moreover, under the different situation of the relation between the effective area of screen grating and picture, can not suitably carry out any convergence correction.
Summary of the invention
According to a kind of digital convegence correcting device of the present invention, comprising: one be used for for screen on a position store the memory of correction data and one with 1 pair 1 corresponding each the convergence correction point of relation and be used for synchronously producing the address counter of reading the address with respect to memory with screen scanning; And wherein produce the convergence correction signal according to the correction data of reading; It is characterized in that described digital convegence correcting device comprises: a vertical yoke current testing circuit is used for the current value of detection of vertical deflection current and generates detection signal; A vertical display area testing circuit is used for according to described detection signal, produce with export one with screen on the corresponding vertical display area detection signal in picture display area position in vertical direction; With an address control circuit, be used for according to address counter of described vertical display area detection signal control.
In the digital convegence correcting device of above layout, by according to screen on the corresponding vertical display area detection signal control address counter in picture display area position in vertical direction, might from memory read with screen on the corresponding correction data of picture display area.As a result, even the relation between screen grating and picture effective area changes with respect to vertical direction, also can carry out convergence correction with high accuracy.In other words,, also might synchronously read correction data from memory in such a way with screen scanning even under the situation of overscanning, so as corresponding to screen on the position with 1 pair 1 the relation corresponding each convergence correction point.
In digital convegence correcting device according to the present invention, vertical display area testing circuit comprises that is used for the comparator that the current value of vertical yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in vertical direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in vertical direction is used as a comparison reference.
The result, even the relation between screen grating and picture effective area changes with respect to vertical direction, also might produce one with the corresponding vertical display area detection signal in picture display area position in vertical direction, thereby the convergence correction that can wish.
In digital convegence correcting device according to the present invention, address circuit under the situation of overscanning in advance vertical display area detection signal, be stored as the signal of the vertical effective area of picture, and under the situation of underdevelopment, obtain at the vertical effective area signal of picture the variation timing, with the variation timing of vertical display area detection signal between time lag, and this time lag is converted to one read the address and output to address counter.
As a result, even the relation between screen grating and picture effective area changes with respect to vertical direction, the also convergence correction that can wish.In other words,, also might synchronously read correction data from memory in such a way with screen scanning even under the situation of underdevelopment, so as corresponding to screen on the position with 1 pair 1 the relation corresponding each convergence correction point.
Digital convegence correcting circuit according to the present invention comprises an index signal generation circuit, and this circuit is used for exporting a display area index signal according to the picture display area of vertical display area detection signal on indication vertical direction on the screen.
As a result, might show a display area index signal, and, obtain a vertical display area detection signal easily when screen during in vertical direction position consistency of the position of vertical direction and picture effective area with respect to vertical direction.
According to a kind of display unit of the present invention, comprise described digital convegence correcting device, this means for correcting has: an index signal generation circuit is used for according to display area index signal of vertical display area detection signal output; With a picture display circuit, be used for according to picture of display area indication signal from the digital convegence correcting circuit.
The result, might on screen, show a display area index signal with respect to vertical direction, and, obtain a vertical display area detection signal easily when screen grating during in vertical direction position consistency of the position of vertical direction and picture effective area.
In digital convegence correcting device according to the present invention, under the situation of underdevelopment, address control circuit is according to vertical synchronizing signal and vertical display area detection signal, time from the extremely vertical display area change in detection signal of time that vertical synchronizing signal changes, the address of reading during one first horizontal scanning period is outputed to the address counter that is used for each horizontal scanning period.
As a result, under the situation of overscanning, the convergence correction signal can prevent the display frame disorder thus changing suddenly on the screen on the upper end of picture display area and on every side.
In digital convegence correcting device according to the present invention, under the situation of underdevelopment, address control circuit is according to vertical synchronizing signal and vertical display area detection signal, time from the extremely vertical display area change in detection signal of time that vertical synchronizing signal changes, the address of reading during a terminal level scan period is outputed to the address counter that is used for each horizontal scanning period.
As a result, under the situation of overscanning, the convergence correction signal can prevent the display frame disorder thus changing suddenly on the screen on the lower end of picture display area and on every side.
Display unit according to the present invention comprises described digital convegence correcting device.
As a result, the relation between screen grating and picture effective area changes with respect to vertical direction, does not also have the reduction of convergence correction precision, and can carry out high-quality picture demonstration.
According to a kind of digital convegence correcting device of the present invention, comprising: one be used for for screen on a position store the memory of correction data and one with 1 pair 1 corresponding each the convergence correction point of relation and be used for synchronously producing the address counter of reading the address with respect to memory with screen scanning; And wherein produce the convergence correction signal according to the correction data of reading; It is characterized in that described digital convegence correcting device comprises: a horizontal yoke current testing circuit is used for the current value of detection level deflection current and generates detection signal; A horizontal display area testing circuit is used for according to described detection signal, produce and export one with screen on the corresponding horizontal display area detection signal in picture display area position in the horizontal direction; With an address control circuit, be used for according to address counter of horizontal display area detection signal control.
In the digital convegence correcting device of above layout, by according to screen on the corresponding horizontal display area detection signal control address counter in picture display area position in the horizontal direction, might from memory read with screen on the corresponding correction data of picture display area.As a result, even the relation between screen grating and picture effective area changes with respect to vertical direction, also can carry out convergence correction with high accuracy.In other words,, also might synchronously read correction data from memory in such a way with screen scanning even under the situation of overscanning, so as corresponding to screen on the position with 1 pair 1 the relation corresponding each convergence correction point.
In digital convegence correcting device according to the present invention, horizontal display area testing circuit comprises that is used for the comparator that the current value of horizontal yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in the horizontal direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in the horizontal direction is used as a comparison reference.
The result, even the relation between screen grating and picture effective area changes with respect to horizontal direction, also might produce one with the corresponding horizontal display area detection signal in picture display area position in the horizontal direction, thereby the convergence correction that can wish.
In digital convegence correcting device according to the present invention, address control circuit under the situation of overscanning in advance horizontal display area detection signal, be stored as the signal of the horizontal effective area of picture, and under the situation of underdevelopment, obtain at the horizontal effective area signal of picture the variation timing, and the variation timing of horizontal display area detection signal between time lag, and this time lag is converted to one read the address and output to address counter.
As a result, even the relation between screen grating and picture effective area changes with respect to horizontal direction, the also convergence correction that can wish.In other words,, also might synchronously read correction data from memory in such a way with screen scanning even under the situation of underdevelopment, so as corresponding to screen on the position with 1 pair 1 the relation corresponding each convergence correction point.
Display unit according to the present invention comprises described digital convegence correcting device.
As a result, the relation between screen grating and picture effective area changes with respect to horizontal direction, does not also have the reduction of convergence correction precision, and can carry out high-quality picture demonstration.
Digital convegence correcting circuit according to the present invention comprises an index signal generation circuit, and this circuit is used for exporting a display area index signal according to the picture display area of horizontal display area detection signal on indication horizontal direction on the screen.
As a result, might show a display area index signal with respect to horizontal direction, and when the screen grating in the horizontal direction the position and during in the horizontal direction position consistency of picture effective area, obtain a horizontal display area detection signal easily.
According to a kind of display unit of the present invention, comprise described digital convegence correcting device, this means for correcting has: an index signal generation circuit is used for according to display area index signal of horizontal display area detection signal output; With a picture display circuit, be used for according to picture of display area indication signal from the digital convegence correcting circuit.
The result, might on screen, show a display area index signal with respect to horizontal direction, and when the screen grating in the horizontal direction the position and during in the horizontal direction position consistency of picture effective area, obtain a horizontal display area detection signal easily.
According to a kind of digital convegence correcting device of the present invention, comprising: one be used for for screen on a position store the memory of correction data and one with 1 pair 1 corresponding each the convergence correction point of relation and be used for synchronously producing the address counter of reading the address with respect to memory with screen scanning; And wherein produce the convergence correction signal according to the correction data of reading;
Described digital convegence correcting device is characterised in that and comprises: a vertical display area testing circuit, be used for according to vertical yoke current produce with export one with screen on the corresponding vertical display area detection signal in picture display area position in vertical direction; A horizontal display area testing circuit, be used for according to horizontal yoke current produce and export one with screen on the corresponding horizontal display area detection signal in picture display area position in the horizontal direction; With an address control circuit, be used for according to vertical display area detection signal and address counter of horizontal display area detection signal control.
In the digital convegence correcting device of above layout, by producing vertical display area detection signal and horizontal display area detection signal and by according to these signal controlling address counters, might from memory read with screen on the corresponding correction data of picture display area.As a result, even the relation between screen grating and picture effective area also can be carried out convergence correction with high accuracy with respect to vertical and any change of horizontal direction.In other words,, also might synchronously read correction data from memory in such a way with screen scanning even under the situation of overscanning, so as corresponding to screen on the position with 1 pair 1 the relation corresponding each convergence correction point.
In digital convegence correcting device according to the present invention, vertical display area testing circuit comprises that is used for the comparator that the current value of vertical yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in vertical direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in vertical direction is used as a comparison reference; And horizontal display area testing circuit comprises that is used for the comparator that the current value of horizontal yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in the horizontal direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in the horizontal direction is used as a comparison reference.
The result, even the relation between screen grating and picture effective area is with respect to vertical and any change horizontal direction, also might produce one with the corresponding vertical display area detection signal in picture display area position in vertical direction and produce one with the corresponding horizontal display area detection signal in picture display area position in the horizontal direction, thereby the convergence correction that can wish.
In digital convegence correcting device according to the present invention, address control circuit under the situation of overscanning in advance vertical display area detection signal, be stored as the signal of the vertical effective area of picture, and address control circuit under the situation of overscanning in advance horizontal display area detection signal, be stored as the signal of the horizontal effective area of picture, and under the situation of underdevelopment, obtain variation timing at the vertical effective area signal of picture, with the time lag between the variation timing of vertical display area detection signal, and obtain variation timing at the horizontal effective area signal of picture, and the time lag between the variation timing of horizontal display area detection signal, and this time lag is converted to one read the address and output to address counter.
As a result, even the relation between screen grating and picture effective area changes with respect to any of vertical and horizontal direction, the also convergence correction that can wish.In other words,, also might synchronously read correction data from memory in such a way with screen scanning even under the situation of underdevelopment, so as corresponding to screen on the position with 1 pair 1 the relation corresponding each convergence correction point.
Display unit according to the present invention comprises described digital convegence correcting device.
As a result, even the relation between screen grating and picture effective area does not have the reduction of convergence correction precision with respect to any change of vertical direction and horizontal direction yet, and can carry out high-quality picture demonstration.
Digital convegence correcting circuit according to the present invention comprises an index signal generation circuit, this circuit be used for exporting one according to vertical display area detection signal and horizontal display area detection signal the display area index signal of the picture display area on indication vertical direction on the screen.
As a result, might show a display area index signal, and obtain easily and the corresponding to vertical display area detection signal of picture effective area and a horizontal display area detection signal with respect to vertical and horizontal direction.
According to a kind of display unit of the present invention, comprise described digital convegence correcting device, this means for correcting has: an index signal generation circuit is used for according to vertical display area detection signal and display area index signal of horizontal display area detection signal output; With a picture display circuit, be used for according to picture of display area indication signal from the digital convegence correcting circuit.
As a result, might on screen, show a display area index signal, and obtain easily and the corresponding to vertical display area detection signal of picture effective area and a horizontal display area detection signal with respect to vertical and horizontal direction.
Description of drawings
Fig. 1 is a calcspar, schematically illustrates the layout according to a kind of display unit of example 1.
Fig. 2 is a calcspar, the layout of convergence correction circuit B1 example shown in the presentation graphs 1.
Fig. 3 (a) and (b) and (c) be key-drawing are to explain the operation of a memory 6 and 1 latch 7.The concrete layout of 1 latch 7 of Fig. 3 (a) expression.Fig. 3 (b) expression is that read and convert the data of serial data to from memory 6 in order.Each of Fig. 3 (c) expression serial data is corresponding with the position on the CRT screen with 1 pair 1 relation.
Fig. 4 is a calcspar, an example of the layout of 1 DAC (8) shown in the presentation graphs 2.
Fig. 5 is a time diagram, and expression is when the variation of gate pulse main signal in 1 DAC (8) shown in Fig. 4 when all are high level constantly.
Fig. 6 (a) and (b) be time diagram, each is illustrated in the variation of the main signal of 1 DAC (8) shown in Fig. 2 under the situation of different two horizontal deflection frequencies.Fig. 6 (b) expression is the blanking pulse H_BLK of the frequency of the frequency 1/2 among input Fig. 6 (a).
Fig. 7 represents an example according to the essential part of the digital convegence correcting device of example 2, and is circuit diagram, the layout of gate pulse circuit 13 shown in the presentation graphs 1.
Fig. 8 is a time diagram, is illustrated in the variation of the main signal in the gate pulse circuit shown in Fig. 7.
Fig. 9 is the calcspar of expression according to an example of the essential part of the display unit of example 3, and is the calcspar of the another kind layout of digital convegence correcting device shown in the presentation graphs 1.
Figure 10 is a calcspar, an example of a kind of layout of 1 DAC (8A) shown in the presentation graphs 9.
Figure 11 is a time diagram, is illustrated under the situation that scanning frequency changes shown in Figure 10 the variation of the main signal among 1 DAC.
Figure 12 (a) and (b) each the expression display area an example.Figure 12 (a) represents wherein the screen grating greater than the overscanning of CRT picture effective area, and Figure 12 (b) represents that wherein the screen grating is less than the underdevelopment of CRT picture effective area.
Figure 13 is a calcspar, schematically illustrates a kind of layout according to a kind of display unit of example 4.
Figure 14 represents an example of a kind of layout of testing circuit E1 of deflection current shown in Figure 13 and E2.
Figure 15 represents another example of a kind of layout of testing circuit E1 of deflection current shown in Figure 13 and E2.
Figure 16 is a calcspar, an example of a kind of layout of convergence correction circuit B2 shown in expression Figure 13.
Figure 17 represents an example of a kind of layout of a vertical display area testing circuit 17 shown in Figure 16.
Figure 18 is illustrated in an example of the variation of each signal of vertical display area testing circuit 17 shown in Figure 17.
Figure 19 represents an example of a kind of layout of a horizontal display area testing circuit 18 shown in Figure 16.
Figure 20 represents an example of the variation of each signal of horizontal display area testing circuit 18 shown in Figure 19.
Figure 21 (a) to (c) is the key-drawing of vertical display area detection signal V_DIS and horizontal display area detection signal H DIS.Figure 21 (a) represents overscanning, and Figure 21 (b) represents underdevelopment, and Figure 21 (c) expression screen grating is consistent with the effective area of picture.
Figure 22 (a) and (b) be key-drawing is to explain the operation of address control circuit 19 under the underdevelopment state.Figure 22 (a) is illustrated in the time lag of vertical direction, and Figure 22 (b) is illustrated in the time lag of horizontal direction.
Figure 23 (a) and (b) each is illustrated in an example of the relation (storage address reflection) between the correction data in display area and the memory 6.Figure 23 (a) is illustrated in the storage address reflection under the overscanning state, and Figure 23 (b) is illustrated in the storage address reflection under the underdevelopment state.
Figure 24 is a calcspar, an example of the layout of 1 DAC (8B) shown in expression Figure 16.
Figure 25 is a calcspar, schematically illustrates a kind of layout according to the display unit of example 5.
Figure 26 is a calcspar, an example of a kind of layout of digital convegence correcting circuit B3 shown in expression Figure 25.
Figure 27 is a calcspar, an example of a kind of layout of index signal generation circuit 20 shown in expression Figure 26.
Figure 28 represents that the display circuit of picture shown in Figure 25 A2 shows a display area index signal HV_CSL and main signal on the CRT screen.
Figure 29 represents an example according to the essential part of a kind of display unit of example 6, and is calcspar, another example of a kind of layout of digital convegence correcting device B3 shown in expression Figure 25.
Figure 30 is a calcspar, an example of the layout of 1 DAC (8C) shown in expression Figure 29.
Figure 31 represents an example according to the essential part of a kind of display unit of example 7, and is calcspar, another example of a kind of layout of digital convegence correcting device B3 shown in expression Figure 25.
Figure 32 is a time diagram, explaining an example of the operation of address control circuit 19A shown in Figure 31, and represent the variation of the last transition of main signal from first transition (forward position) of vertical blanking pulse V_BLK to vertical display area detection signal V_DIS (back along).
Figure 33 is a time diagram, explaining an example of the operation of address control circuit 19A shown in Figure 31, and represent the variation of first transition (forward position) of main signal from the last transition of vertical display area detection signal V_DIS (back along) to vertical blanking signal pulse V_BLK.
Figure 34 is a key-drawing, schematically illustrates the operating result of address control circuit 19A shown in Figure 32 and 33 on screen.
Figure 35 represents an example according to a kind of layout of a kind of display unit of example 8.
Figure 36 is a calcspar, an example of a kind of layout of digital convegence correcting device B4 shown in expression Figure 35.
Figure 37 is illustrated on the screen example of a check point indicator diagram L_CSL who is shown by picture display circuit A3 and vertical display area detection signal V_DIS and horizontal display area detection signal H_DIS.
Figure 38 represents an example with respect to the adjusting order of each convergence correction point of 25 points shown in Figure 37.
Figure 39 is a calcspar, schematically illustrates an example according to a kind of layout of the display unit of example 9.
Figure 40 is a calcspar, an example of a kind of layout of convegence correcting device B5 shown in expression Figure 39.
Embodiment
Example 1
Fig. 1 is a calcspar, schematically illustrates the layout according to a kind of display unit of example 1.In the figure, label A1 indicates a picture display circuit, number convergence correction circuit of B1 indication, number CRT of C indication, number deflecting coil of C1 indication, and number convergence coil of C2 indication.Picture display circuit A1 is a circuit that is used for according to input picture signal display frame on the CRT screen.Picture display circuit A1 supplies with a vertical yoke current iDYV and a horizontal yoke current iDYH to deflecting coil C1, and supplies with a color signal to the negative electrode of CRT.Convergence correction circuit B1 supplies with a convergence correction current i CY according to a horizontal blanking impulse H_BLK and the vertical blanking pulse V_BLK from picture display circuit A1 to convergence coil C2, and the deflection angle of correcting electronic bundle.
Fig. 2 is a calcspar, convergence correction circuit B1 example shown in the presentation graphs 1.In the figure, the input terminal of label 1 indication horizontal blanking impulse H_BLK, the input terminal of number 2 indication vertical blanking pulse V_BLK, and number 3 indication phase-locked loop circuits (PLL).Calibration counter of numbers 4 indications, number address counter of 5 indications, and number memory of 6 indications.1 latch of numbers 7 indications, number 1 DAC of 8 indications, and number low pass filter of 9 indications.Amplifier of numbers 10 indications, the outlet terminals of number 11 indication convergence correction current i CY, and number gate pulse circuit of 13 indications.
[1] at first, the element shown in Fig. 2 is hereinafter described.The frequency f synchronous with the raster scan on the CRT HHorizontal blanking impulse H_BLK be input to H_BLK input terminal 1, and PLL 3 produces a reference clock by multiply by horizontal blanking impulse H_BLK.And count device 4 of protractor is divided reference clocks, and produces a system clock.As a result, system clock constantly is controlled to constant to the division of horizontal direction at all.
Address counter 5 is synchronous with system clock, and the address of reading that produces memory 6 in order.These addresses respectively with raster scan in the horizontal direction with vertical direction on time phase, promptly with the screen grating in relative position, corresponding.Be input to V_BLK input terminal 2 with the vertical blanking pulse V_BLK of the synchronous frequency f v of the raster scan on the CRT, and vertical blanking pulse V_BLK reseting address counter 5.
Memory 6 in advance with the CRT screen on the position with 1 pair 1 the relation corresponding each convergence correction point correcting value be stored as correction data.These correction datas are the up/down information (change information) when the correcting value of adjacent convergence correction point on the correcting value of corresponding convergence correction point and the horizontal direction is compared.Each of correction data comprises 1, and " increase " of " 1 " indication correcting value, and " 0 " indication correcting value " reducing ".By this way, and wherein compare with the conventional convegence correcting device that keeps correcting value, reduced to be used for storing the memory span of correction data widely for the storage of each convergence correction point.
1 correction data can connect pattern as 2 with adjacent correction data.More particularly, in the up/down information at convergence correction point place by handle and assemble corresponding 1 correction data of check point and put corresponding 1 bit correction data and combine with adjacent convergence correction, with the form of two up/down information, can represent " increase ", " reducing ", " constant " three kinds of states.As 2 connection patterns, four types combination " 00 ", " 01 ", " 10 " and " 11 " are arranged.In the middle of them, " 01 " or " 10 " represents " constant " of correcting value, and " 00 " represents " reducing " of correcting value, and " 11 " represent " increase " of correcting value.In general, there is not the sudden change of convergence correction amount, as not from " increase " to " reducing " or variation from " reducing " to " increase ".Thereby, by the convergence correction point of predetermined fixed sufficient amount on the CRT screen, correction data is used as the convergence correction that described connection pattern can carry out any hope.
Read correction data according to address from memory 6 from address counter 5.In other words, owing to synchronously carry out from the reading of memory 6 with raster scan on the CRT, so as long as the relation between picture effective area and screen grating remains unchanged, the correction data of reading is just corresponding with the convergence check point.
Because each of correction data has 1, thus when the bit wide of memory 6 is 8, in an address, can store the correction data that is used for eight convergence correction points, and can synchronously read 8 correction datas.1 latch 7 is to be used for the data transaction of reading from memory 6 is become the circuit of serial data, and comprises a displacement transistor.For example, when the data of reading 8 from memory 6, for each convergence correction point data are divided into 1 bit correction data, and synchronously export as serial data and system clock in order from the MSB side.
Fig. 3 (a) and (b) and (c) be key-drawing are to explain the operation of a memory 6 and 1 latch 7.The concrete layout of 1 latch 7 of Fig. 3 (a) expression.Fig. 3 (b) expression is that read and convert the data of serial data to from memory 6 in order.Each of Fig. 3 (c) expression serial data is corresponding with the position on the CRT screen with 1 pair 1 relation.As Fig. 3 (b) with (c), press for the convergence correction on first horizontal scanning line on the screen and to call over correction data, and convert serial data to.
Fig. 4 is a calcspar, an example of the layout of 1 DAC (8) shown in the presentation graphs 2.In the figure, label 80 one of indication are used for serial data is converted to upwards signal and the decoding circuit of signal downwards.Numbers 81 one of indication be used for signal upwards and downwards the output time of signal be controlled to be gate circuit with the irrelevant constant of scanning frequency.Numbers 82 one of indication be used on upwards signal and downward conversion of signals become-subtraction circuit of following signal.Numbers 83 one of indication are used on the integration-integrating circuit of following signal.
Decoding circuit 80 comprises D circuits for triggering 801 to 803 and NOR (or non-) computing circuit 804 and 805.The phase gate signal g1 and the g2 of the first transition sync inversion of circuits for triggering 801 generations and system clock.These phase gate signal g1 and g2 are reversed phase signals respect to one another.Phase gate signal g1 and g2 become timing signal CLK1 and CLK2 through the NOR computing with system clock respectively in NOR computing circuit 804 and 805.Store 1 Bits Serial data respectively with the synchronous circuits for triggering 802 of timing signal CLK1 with the synchronous circuits for triggering 803 of timing signal CLK2.Then, the data of circuits for triggering 802 output storage are as a signal upwards, and circuits for triggering 803 are the data paraphase of storage, and as signal output upwards it.
Gate circuit 81 comprise AND (with) computing circuit 810 and 811.The gate pulse AND computing of describing after upwards signal and downward signal stand in AND computing circuit 810 and 811 respectively, and be input to subtraction circuit 82.In other words, have only when gate pulse is high level, upwards signal and downward signal could pass through gate circuit 81.
Subtraction circuit 82 comprises an operational amplifier and all resistors, and by means of deduct from downward signal by gate circuit 81 upwards signal by gate circuit produce one on-following signal.Thereby, on this-following signal is one and comprises that representative " increase "-1 level, representative " reduce "+1 level, and three kinds of voltage levels of representative " constant " ± 0 level.
Integrating circuit 83 is mirror image integrating circuit that use operational amplifier, and export one by on the integration-analog signal that following signal obtains.This analog signal becomes a continuous convergence correction signal in low pass filter 9, and after amplifying in amplifier 10, supplies to convergence yoke coil C2.By using a kind of like this 1 DAC (8), might convert 2 connection pattern to upwards-information downwards, and obtain hope correcting value at each convergence correction point place.
[2] present, the operation as the convergence correction circuit B1 of gate pulse when all are high level is constantly hereinafter described.Fig. 5 is a time diagram, and expression is when the variation of gate pulse main signal in 1 DAC (8) shown in Fig. 4 when all are high level constantly.In the figure, label (a) indication serial data, (b) system clock of indication, (c) phase gate signal g1 of indication reaches (d) phase gate signal g2 of indication.Timing signal CLK1 of symbol (e) indication, (f) timing signal CLK2 of indication (g) indicates a upwards signal, reaches (h) downward signal of indication.Gate pulse of symbol (i) indication, (j) in one of the indication-following signal, and (k) analog output signal of indication.
Timing signal CLK1 and CLK2 alternately and with system clock synchronously export pulse.Upwards signal and timing signal CLK1 synchronously upgrade, and downward signal and timing signal CLK2 synchronously upgrade.
In this case because gate pulse constantly all is in high level at all, so upwards signal and downwards signal constantly all pass through gate circuit 81 at all, and the result of these signal subtractions become original on-following signal.Therefore, during the connection pattern when serial data was the cycle of " 01 " or " 10 ", the output level of analog output signal was constant and not variation.During the cycle of " 00 ", output level reduces continuously, and during the cycle of " 11 ", output level increases continuously.
[3] present, the operation of display unit when horizontal deflection frequency changes is hereinafter described.Fig. 6 (a) and (b) be time diagram, each is illustrated in the variation of the main signal of 1 DAC (8) shown in Fig. 2 under the situation of different two horizontal deflection frequencies.Fig. 6 (b) expression input is the blanking pulse H_BLK of the frequency of the frequency 1/2 among Fig. 6 (a).Attention is at Fig. 6 (a) with (b), and axis of abscissas is public, and in other words, it is illustrated on the identical time scale.
System clock be one by multiply by input horizontal blanking impulse and divide the signal that it obtains, and its frequency and a horizontal deflection frequency f HChange pro rata.Thereby, as horizontal deflection frequency f HWhen becoming 1/2 (half), horizontal address counter 6 produces an address by 1/2 frequency, and also carries out reading from the correction data of memory 12 by 1/2 frequency.As a result, under Fig. 6 (b) situation, system clock and serial data all change by the cycle that is the twice among Fig. 6 (a).
On the other hand, gate pulse circuit 13 is the monostable multivibrators with the synchronous generator gate pulse of system clock, and the pulse duration of gate pulse constantly all is a constant and irrelevant with system clock at all.Thereby although the gate pulse among Fig. 6 (a) constantly all is in high level at all, the duty ratio of gate pulse is 50% in Fig. 6 (b).Therefore, cycle when downward signal is in " reducing " level and the cycle when it is in " increase " level all equate at Fig. 6 (a) with (b), and the integration period in integrating circuit 83 also equates.As a result, though analog output signal the time base direction on extend, peak value W constantly also can keep equal at all.
In other words, in this convegence correcting device, the frequency of system clock changes pro rata with horizontal deflection frequency by PLL 3 and changes, and system clock keeps the division of horizontal direction constant at all constantly.Thereby, do not produce time lag reading in the corresponding relation between timing and the convergence correction point that should be corresponding to its correction data of correction data.Even under the situation that horizontal deflection frequency changes, the pulse duration of gate pulse also can keep constant, and ignores horizontal deflection frequency, it is constant that the output time of the system clock cycle of the output signal of gate circuit 81 keeps.Thereby the level (being peak value) that prevents and assemble the corresponding analog output signal of check point changes.As a result, even horizontal deflection frequency changes, also might be relatively and the position on the CRT screen with 1 pair 1 convergence correction that concerns that corresponding each convergence correction point is wished.
By using above-mentioned convegence correcting device, might reduce to be used for storing and keeping the memory span of correction data widely.And, by determining correcting value with respect to each convergence correction point of a horizontal deflection frequency, the convergence correction that might wish, and need not determine other correcting value with respect to other varying level deflection frequencies.
Although having described one of them horizontal deflection frequency in this example 1 is the example of the twice of another horizontal deflection frequency, convegence correcting device according to the present invention is not limited to such example.In other words, in convegence correcting device according to the present invention, when the load factor of gate pulse is 100%, reach available peak frequency.Therefore, this convegence correcting device can be applied to not depart from the interior any horizontal deflection frequency of area of 100% load factor.
Although in this example, use 1 bit correction data, might use 2 bit correction data.For example, by using 2 bit data, for each convergence correction point can be stored and keep every kind of state of " increase ", " reducing " or " constant ", and need not be data as connecting pattern.Also might use 2 bit data storages and keep changing is that " increases " and the variation of two-stage is two-stage " reducing ".
Example 2
Fig. 7 represents an example according to the essential part of the digital convegence correcting device of example 2, and is circuit diagram, the layout of gate pulse circuit 13 shown in the presentation graphs 1.Gate pulse circuit 13 is combinational circuits of circuits for triggering.In the figure, label 130 indication has the D circuits for triggering of a reseting terminal, the tristate buffer that one of label 131 indication can output high impedance, and number 132 an indication paraphase Schmitt (Schmidt) buffers.R indicates a resistor, and capacitor of C indication.Fig. 8 is a time diagram, is illustrated in the variation of the main signal in the gate pulse circuit.In the figure, (a) system clock of indication, (b) gate pulse of indication, (c) end voltage Vc of indication capacitor reaches (d) reset signal of indication circuits for triggering.
In circuits for triggering 130, import a high level from a power source voltage Vcc 1 to an input terminal D, and a system clock is input to a trigger input terminal.Thereby high level is synchronously arrived in first transition of outlet terminal Q and system clock, and this high level is exported as gate pulse, and an outlet terminal of tristate buffer 131 changes to high impedance status from low level.
When the outlet terminal of tristate buffer 131 during to high impedance status, a current i flows to capacitor C through resistor R from power Vcc 2, and charging capacitor C.Then, when the end voltage Vc of capacitor C arrived the threshold level Vth of paraphase Schmitt buffer 132, the outlet terminal of paraphase Schmitt buffer 132 changed to low level, and reset trigger circuit 130.
When reset trigger circuit 130, its outlet terminal Q changes to low level, and this low level exports as a gate pulse, and the outlet terminal of tristate buffer 131 is to low level.As a result, current i ' flow to tristate buffer 131, and capacitor C discharge from capacitor C, the output of paraphase Schmitt buffer 132 changes to high level thus.By repeating aforesaid operations, might synchronously produce the gate pulse of forming by the pulse of isopulse duration with system clock.In other words, might with scanning frequency synchronously output pulse width constant and with the irrelevant pulse of scanning frequency.
The duration of each pulse of formation gate pulse is corresponding with the charging interval of capacitor C, and therefore by the magnitude of voltage of selecting power Vcc 2, the resistance value and the electric capacity of resistor R, can be created as the pulse duration with any hope to gate pulse.In addition, by adopting a variable power supply to control its output voltage as power Vcc 2 with by means of the microcomputer (not shown), the duration of regulating impulse easily.
Example 3
When scanning frequency was constant, calibration counter 4 can be supplied with stable system clock.On the contrary, when scanning frequency changes,, and supply to the address disorder of memory 6 from address counter 5 because that the reset system clock of PLL 3 becomes is unsettled.As a result, with screen on the position with 1 pair 1 the relation corresponding each convergence correction point not corresponding with the correction data of reading.Thereby, supply to the convergence correction signal iCY disorder of convergence yoke coil C2, and picture shows disorderly.What describe in this example is a kind of under the situation that the scanning frequency of input picture signal changes, and is used for preventing that any picture by the convergence correction signal causes from showing disorderly display unit.
Fig. 9 is the calcspar of expression according to an example of the essential part of the display unit of example 3, and is the calcspar of a kind of layout of digital convegence correcting device shown in the presentation graphs 1.This convegence correcting device comprises the convegence correcting device shown in Fig. 2, to its add a frequency detection circuit 12 with one with different 1 DAC (8A) shown in Fig. 2.Figure 10 is a calcspar, an example of a kind of layout of 1 DAC (8A) shown in the presentation graphs 9.This 1 DAC (A) comprises 1 DAC shown in Fig. 4, it is added an inhibit circuit 84, and in the figure, label 840 indication phase inverters (paraphase computing circuit), numbers 841 indication AND computing circuits, and number OR of 842 indications (or) computing circuit.
Frequency detection circuit 12 be one be used for the variation of monitor scans frequency, the PLL 3 that under the situation of frequency change, resets, and an inhibit signal is outputed to the circuit of 1 DAC (8A).This circuit can be formed by for example microcomputer.In this circuit, import a horizontal blanking impulse H_BLK and a vertical blanking pulse V_BLK, and under the situation of horizontal frequency and vertical frequency variation, PLL_3 resets.And, after horizontal frequency and vertical frequency variation, only for certain low level inhibit signal of cycle output.
When inhibit signal was in high level, serial data was in statu quo by AND computing circuit 841 and OR computing circuit 842, and with Fig. 4 in 1 DAC mode about the same operate.When inhibit signal arrived low level, the output of AND computing circuit 841 and OR computing circuit 842 was respectively fixed to low level and high level, and upwards signal all is fixed to low level with downward signal.The level of analog output signal becomes constant.
Under the situation that scanning frequency changes, the inhibit signal of frequency detection circuit 12 output low levels, up to the PLL 3 that resets, and the systems stabilisation clock.As a result, it is constant that the level of convergence correction signal can keep, and might prevent the disorder that picture shows.
Figure 11 is a time diagram, is illustrated under the situation that scanning frequency changes shown in Figure 10 the variation of the main signal among 1 DAC.When inhibit signal since the variation of scanning frequency when high level changes to low level, upwards signal and downwards signal all be fixed to low level, and analog output signal is controlled to constant.Then, after the systems stabilisation clock, frequency detection circuit 12 is controlled to the inhibit signal of exporting a high level once more and exports the analog signal of a hope.
Although in this example 3, described an example wherein controlling the convergence correction signal, also might only control according to the variation of level or vertical frequency according to the variation of horizontal frequency and vertical frequency.
Example 4
What describe in this example is, even a kind of, also can make the display unit of each convergence correction point corresponding to the correction data of reading from memory 6 being the picture effective area of the effective display area on the CRT screen and being under the situation of the relationship change between the screen grating of the scanning area on the CRT screen.
At first, according to the relation between screen grating and the picture effective area, it is that area on the screen is with the picture display area of display frame that a kind of situation of hereinafter a kind of situation ground is described.In this respect, in this example, be noted that it is that to be used for carrying out the corrected area of area of convergence correction on screen consistent with the picture display area.Figure 12 (a) and (b) each the expression display area an example.Figure 12 (a) represents wherein the screen grating greater than the overscanning of CRT picture effective area, and Figure 12 (b) represents that wherein the screen grating is less than the underdevelopment of CRT picture effective area.In these figure, the effective area of solid line indication picture, dotted line instruction screen grating, and dash area indicated number area.As shown in these figures, under the situation of underdevelopment, make display area consistent, and under the situation of overscanning, make display area consistent with the effective area of picture with the screen grating.In order to carry out convergence correction, under the situation of underdevelopment, must carry out convergence correction with respect to a picture effective area part with respect to a kind of like this display area.
Figure 13 is a calcspar, schematically illustrates a kind of layout according to a kind of display unit of example 4.This display unit comprises the display unit shown in Fig. 1, and its interpolation is used for detecting the deflection current testing circuit E1 and the E2 of the current value of deflection current, and digital convergence correction circuit B2 is different from the circuit among Fig. 1.Deflection current testing circuit E1 exports a detection signal DYV by detecting a vertical yoke current iDYV, and deflection current testing circuit E2 is by detecting detection signal DYH of a horizontal yoke current iDYH output.Then, convergence correction circuit B2 is according to detection signal DYV and convergence correction signal iCY of DYH output.
Figure 14 represents an example of a kind of layout of deflection current testing circuit E1 and E2.In each of deflection current testing circuit, series connection is inserted one and is detected resistor R L for deflecting coil C1, and to make the voltage between the terminal that detects resistor R L be to detect voltage V 0By using sort circuit, can be the electric current that flows to resistor R L, the current i DYV and the iDYH of the deflecting coil of promptly flowing through convert magnitude of voltage DYV and DYH to.Figure 15 represents another example of a kind of layout of deflection current testing circuit E1 and E2.In this deflection current testing circuit, be connected in series to deflecting coil C1 at the coil of the primary side of a current transformer L who is used to detect, and be connected to primary side detecting a resistor R L.Make the voltage between the terminal that detects resistor R L become a detection voltage V 0By this way, can convert deflection current iDYV and iDYH to magnitude of voltage DYV and DYH.
Figure 16 is a calcspar, an example of a kind of layout of convergence correction circuit B2 shown in expression Figure 13.This convergence correction circuit comprises the convergence correction circuit shown in Fig. 2, it is added a vertical display area testing circuit that is used for exporting vertical display area detection signal V_DIS 17, one be used for horizontal display area testing circuit 18, and address control circuit 19 that is used for control address counter 5 of the horizontal display area detection signal of output H_DIS, and one 1 DAC (8B) is different among Fig. 2.
Vertical display area testing circuit 17 produces a corresponding vertical display area detection signal V_DIS of the display area with vertical direction according to the detection signal DYV of vertical yoke current.Horizontal display area testing circuit 18 produces a corresponding horizontal display area detection signal H_DIS of the display area with horizontal direction according to the detection signal DYH of horizontal yoke current.Figure 17 represents an example of a kind of layout of a vertical display area testing circuit 17.In the figure, label 170 and 171 indication comparators, and circuit takes place in number V_DIS of 172 indications.Figure 18 represents an example of the variation of each signal.In the figure, (a) indication detection signal DYV, (b) output of indication comparator 170, (c) output of indication comparator 171 reaches (d) the vertical display area detection signal V_DIS of indication.In comparator 170, the detection signal DYV of vertical yoke current is compared with a level VT corresponding to the display area top edge, and in comparator 171, compare with a level VB corresponding to the display area lower limb.Then, according to comparative result, circuit takes place and produces and the corresponding vertical display area detection signal V_DIS of the display area of vertical direction in V_DIS.Figure 19 represents an example of a kind of layout of horizontal display area testing circuit 18.In the figure, label 180 and 181 indication comparators, and circuit takes place in number H_DIS of 182 indications.Figure 20 represents an example of the variation of each signal.In the figure, (a) indication detection signal DYH, (b) output of indication comparator 180, (c) output of indication comparator 181 reaches (d) the horizontal display area detection signal H_DIS of indication.In comparator 180, the detection signal DYH of horizontal yoke current is compared with a level VL corresponding to the display area left hand edge, and in comparator 181, compare with a level VR corresponding to the display area right hand edge.Then, according to comparative result, the corresponding horizontal display area detection signal H_DIS of display area of circuit generation and horizontal direction takes place in H_DIS.Each of these comparative levels VT, VB, VR and VL is by the not microcomputer control and a setting of expression.
Figure 21 (a) to (c) is the key-drawing of vertical display area detection signal V_DIS and horizontal display area detection signal H_DIS.Figure 21 (a) represents overscanning, and Figure 21 (b) represents underdevelopment, and Figure 21 (c) expression screen grating is consistent with the effective area of picture.In every figure, with respect to vertical display area detection signal V_DIS, the time base consistent with the vertical scanning scale indicated in vertical direction.And with respect to horizontal display area detection signal H_DIS, the time base consistent with the horizontal sweep scale indicated in the horizontal direction.Under Figure 21 (b) and situation (c), the microcomputer that is used for controlling each comparative level is established as comparative level VT and VB the maximum of detection signal DYV and minimum value and respectively comparative level VL and VR is established as maximum and the minimum value of detection signal DYH just enough respectively.On the other hand, under the situation of Figure 21 (a), must produce and the corresponding vertical active area area of signal V_DIS of picture effective area in vertical direction 0As vertical display area detection signal V_DIS.Also must produce and the corresponding horizontal active area area of signal H_DIS of picture effective area in the horizontal direction 0As horizontal display area detection signal H_DIS.For this purpose, under the situation of screen grating Figure 21 (c) consistent with the effective area of picture, microcomputer is stored vertical active area area of signal V_DIS in advance therein 0Data and horizontal active area area of signal H_DIS 0Data.Then, use these data, microcomputer carries out the control of each comparative level under the state of overscanning.In other words, under the situation of overscanning, control the comparative level VT and the VB of vertical display area testing circuit 17, thus vertical display area detection signal V_DIS and vertical active area area of signal V_DIS 0Data consistent.And the comparative level VL and the VR of controlling level display area testing circuit 18, thereby horizontal display area detection signal H_DIS and horizontal active area area of signal H_DIS 0Data consistent.
Address control circuit 19 control address counters 5, thus under the situation of underdevelopment the correction data of the part of readout memory 6.According to the vertical active area area of signal V_DIS that stores in advance 0Data, in advance the storage horizontal active area area of signal H_DIS 0Data, from the vertical display area detection signal V_DIS of vertical display area testing circuit 17, and, carry out this control from the horizontal display area detection signal H_DIS of horizontal display area testing circuit 18.At first, address control circuit 19 obtains first transition and vertical active area area of signal V_DIS at vertical display area detection signal V_DIS 0First transition between time lag, and the time lag that obtains is converted to the interval quantity nV of convergence correction point on the vertical direction.Address control circuit 19 also obtains at first transition of horizontal display area detection signal H_DIS and horizontal active area area of signal H_DIS 0First transition between time lag, and the time lag that obtains is converted to the interval quantity nH (being the quantity of system clock) of convergence correction point on the horizontal direction.Figure 22 (a) and (b) be each the expression a kind of like this state figure.
According to this result, address control circuit 19 supplies to address counter 5 reading the address.With one be that (nV+1) is individual and be that the address that (nH+1) individual convergence correction is put corresponding correction data outputs to address counter 5 in the horizontal direction in vertical direction.Also on the left hand edge of screen grating, by skipping the address OPADD counter 5 that nH convergence correction point obtains in the horizontal direction.After by address control circuit 19 address being set, address counter 5 synchronously increases the address with system clock in order, changes to low level up to horizontal display area detection signal H_DIS.Under the situation of overscanning, because all correction datas of readout memory 6, so needn't allow address control circuit 19 control address counters 5.
Figure 23 (a) and (b) each is illustrated in an example of the relation (storage address reflection) between the correction data of described when operation in display area and memory 6.Figure 23 (a) is illustrated in the storage address reflection under the overscanning state, and Figure 23 (b) is illustrated in the storage address reflection under the underdevelopment state.Under the state of overscanning, go up the whole effective area of picture with respect to CRT, carry out convergence correction, and utilize all correction datas that are stored in the memory 6.On the other hand, under the state of underdevelopment,, promptly, carry out convergence correction, and only utilize a part that is stored in the correction data in the memory 6 with respect to the part of picture effective area with respect to whole screen grating.In these figure, expression memory 6 is used for the correction data of all the convergence correction points on the picture effective area with address 0000h to FFFFh storage, and under the state of underdevelopment, only uses the data of address 8888h to CCCCh.
Figure 24 is a calcspar, represents an example of the layout of a kind of 1 DAC (8B).This 1 DAC comprises 1 DAC (8) shown in Fig. 4, and it is added an initial value generation circuit 85, a DAC (86) and a current adder circuit 87, and supplies with addresses from address counter 5.Initial value generation circuit 85 is according to the address from address counter, in the convergence correction amount or the convergence correction amount on the left hand edge that is created in the picture effective area under the overscanning state that produce under the underdevelopment state on the screen grating left hand edge, as initial value data.This convergence correction amount is a value that every kind of variation of scanning frequency is obtained, and is the integrated value of the correction data between the left hand edge of the left hand edge of the effective area of picture and screen grating.The convergence correction amount is stored in the memory of an initial value generation circuit 85.Initial value data from initial value generation circuit 85 converts an analog signal to, adds in add circuit 87 in the output of integrating circuit 83, becomes an analog output signal.
Thereby, under the situation of overscanning, the effective area of picture is built up a display area, and carry out convergence correction with respect to the picture effective area according to the display unit of this example.Therefore, each convergence correction point can be corresponding to the correction data of reading from memory.
Under the situation of underdevelopment, according to the part of the correction data in the display unit use memory of this example, promptly only use is put corresponding correction data with the convergence correction in the screen grating, carries out convergence correction.Therefore, each convergence correction point can be corresponding to the correction data of reading from memory.
Because the initial value of storage and maintenance correcting value, so, under the state of underdevelopment, also can export one and proofread and correct analog output signal even correction data is the variable data of convergence correction amount.
As described in example 1, even under the situation that scanning frequency changes, this convegence correcting device also can carry out with respect to the hope convergence correction with corresponding each the convergence correction point in position on 1 pair 1 relation and the CRT screen.As a result, even under the situation that the relation between screen grating and the picture effective area changes owing to the variation of scanning frequency, the also convergence correction that might wish.And, not only under the situation that the relation between screen grating and the picture effective area changes owing to the variation of scanning frequency, and under the situation of same scan frequency, the relation between screen grating and picture effective area not simultaneously, the also convergence correction that can wish.
Although described the convergence correction under the situation of typical overscanning and underdevelopment in this example 4, in the horizontal direction or vertical direction is in the overscanning state and another is under the situation of underdevelopment state, this convegence correcting device also is available.
Example 5
In this example, a kind of convegence correcting device can easily obtain vertical active area area of signal V_DIS 0Data and horizontal active area area of signal H_DIS 0Data.
Figure 25 is a calcspar, schematically illustrates a kind of layout according to the display unit of example 5.This display unit comprises the display unit shown in Figure 13, to its add with Figure 13 in those a different picture display circuit A2 and digital convergence correction circuit B3.Be input to a picture display circuit A1 from a display area index signal HV_CSL of convergence correction circuit B3 output.And picture display circuit A2 shows according to the picture that an input picture signal or display area index signal HV_CSL carry out on CRT (C).
Figure 26 is a calcspar, an example of a kind of layout of digital convegence correcting circuit B3 shown in expression Figure 25.This convergence correction circuit B3 comprises the convergence correction circuit shown in Figure 16, and it is added an index signal generation circuit 20.Index signal generation circuit 20 produces the display area index signal HV_CSL that is used for showing a display area on screen according to vertical display area detection signal V_DIS and horizontal display area detection signal H_DIS.
Figure 27 is a calcspar, an example of a kind of layout of expression index signal generation circuit 20.In the figure, circuit takes place in V_CSL of label 200 indications, and circuit takes place number H_CSL of 201 indications, and number OR computing circuit of 202 indications.
Circuit 200 takes place when vertical display area detection signal V_DIS changes in V_CSL, and output comprises and two edges, i.e. display area top edge and lower limb in vertical direction, the vertical display area index signal V_CSL of corresponding pulse.Each pulse that is included among this vertical display area index signal V_CSL has the pulse duration of comparing enough weak points with the field duration.Particularly, preferably each pulse has the pulse duration that is equivalent to horizontal scanning period.
Circuit 201 takes place when horizontal display area detection signal H_DIS changes in H_CSL, and output comprises and two edges, i.e. display area left hand edge and right hand edge in the horizontal direction, the horizontal display area index signal H_CSL of corresponding pulse.Each pulse that is included among this horizontal display area index signal H_CSL has the pulse duration of comparing enough weak points with horizontal scanning period.Particularly, preferably each pulse has the pulse duration that is equivalent to system clock cycle.
OR computing circuit 202 mixes vertical display area index signal V_CSL and horizontal display area index signal H_CSL, and the corresponding display area index signal HV_CSL of the periphery edge of output and display area.Picture display circuit A2 shows this display area index signal HV_CSL as picture on the CRT screen.In other words, the picture of the rectangular frame shape of the periphery edge of expression display area is shown.Figure 28 represents the relation between these signals, and expression picture display circuit A2 shows a kind of mode of this display area index signal HV_CSL on the CRT screen.
Described below is a kind of vertical active area area of signal V_DIS that is used for obtaining being stored in the address control circuit 19 0Data and horizontal active area area of signal H_DIS 0The method of data.At first, by changing the screen size of display unit etc., import picture signal to one and put under the overscanning state.At this moment, being arranged to an all or part of value that is suitable for the rectangular frame of demonstration display area index signal HV_CSL on screen by microcomputer-controlled each comparative level VT, VB, VL and VR.As a result, rectangular frame is presented on the CRT screen by picture display circuit A2.By this way, observation is presented at the operator of the rectangular frame on the screen, carry out in vertical display area testing circuit 17 comparative level VT and VB's and comparative level VL in horizontal display area testing circuit 18 and the control of VR, thereby rectangular frame is consistent with the periphery edge of picture effective area.This control does not have the microcomputer of expression to carry out through one.
Consistent by the periphery edge that makes display area with the periphery edge of picture effective area, might be from the vertical active area area of signal V_DIS of vertical display area testing circuit 17 outputs 0With from the horizontal active area area of signal H_DIS of horizontal display area testing circuit 18 outputs 0Thereby, only by the output signal of the vertical display area testing circuit 17 that at this moment obtains being stored as vertical active area area of signal V_DIS 0Data and by the output signal of horizontal display area testing circuit 18 being stored as horizontal active area area of signal H_DIS 0Data, just can obtain data.
By adopting above layout, can easily obtain vertical active area area of signal V_DIS according to the convegence correcting device of this example 0Data and horizontal active area area of signal H_DIS 0Data.
Although 20 outputs of indication signal generating circuit are by mixing the display area index signal HV_CSL that vertical display area index signal V_CSL and horizontal display area index signal H_CSL obtain in this example, but best also has, optionally export vertical display area index signal V_CSL or horizontal display area index signal H_CSL, to obtain vertical active area area of signal V_DIS in proper order by this 0Data and horizontal active area area of signal H_DIS 0Data.
Example 6
What describe in this example is, a kind of comprise according to example 5 (Figure 25) even display unit and the scanning frequency of the input picture signal display unit that changes any disorder that can prevent that also picture that the disorder by the convergence correction signal causes from showing.
Figure 29 represents an example according to the essential part of the display unit of this example, and is calcspar, another example of a kind of layout of digital convegence correcting device shown in expression Figure 25.
This convegence correcting device comprises the convegence correcting device shown in Figure 26, it is added a frequency detection circuit 12, and one 1 DAC (8C) is different among Figure 26.This frequency detection circuit 12 is and the identical circuit shown in Fig. 9.Figure 30 is a calcspar, an example of the layout of 1 DAC (8C) shown in expression Figure 29.This 1 DAC (8C) comprises 1 DAC (8B) shown in Figure 24, and it is added an inhibit circuit 84.This inhibit circuit 84 is and the identical circuit shown in Figure 10.
Under the situation that scanning frequency changes, low level inhibit signal of frequency detection circuit 12 outputs, up to PLL 3 reset and system clock stable.As a result, inhibit circuit 84 is fixed to low level to make progress signal and downward signal, and becomes constant from the analog signal of integrating circuit 83.On the other hand, DAC (86) is according to the constant analog signal of initial value data output by 85 outputs of an initial value generation circuit.As a result, the level from the analog output signal of an add circuit 87 output keeps constant.
Therefore, also in the display unit according to example 4 or 5, if scanning frequency changes, then the level of convergence correction signal can keep constant, resets and system clock is stablized up to PLL 3, and becomes and might prevent the disorder of picture demonstration.
Example 7
What describe in this example is, a kind of display unit of any disorder in the display frame that can prevent under the underdevelopment state to be caused in the top edge and the sudden change on the lower limb of screen grating by the convergence correction signal.
This convegence correcting device comprises vertical display area testing circuit 17, horizontal display area testing circuit 18, reaches address control circuit 19.As a result, with example 4 in identical mode, address counter 5 produces an address that is used for the picture effective area under the situation of overscanning, and under the situation of underdevelopment, produce one with the screen grating in each convergence correction put corresponding address.Thereby, might all carry out constantly and screen grating and picture effective area between the corresponding convergence correction of relation.
Figure 31 represents an example according to the essential part of a kind of display unit of example 7, and is calcspar, another example of a kind of layout of digital convegence correcting device B3 shown in expression Figure 25.This convegence correcting device comprises the convegence correcting device shown in Figure 29, to its add one with the different address control circuit 19A shown in Figure 29.
Figure 32 and 33 is time diagrams, explaining an example of the operation of address control circuit 19A shown in Figure 31, and is illustrated in the variation under the underdevelopment situation.In these figure, (a) vertical blanking pulse V_BLK of indication, (b) vertical display area detection signal V_DIS of indication, (c) horizontal blanking impulse H_BLK of indication, (d) horizontal display area detection signal H_DIS of indication, reaching (e), one of indication is the conventional correction signal iCY of the drive signal of convergence yoke coil C2.
For each horizontal scanning period, address control circuit 19A outputs to address counter 5 to identical address, thereby, carry out identical convergence correction in each horizontal scanning period of first transition of the vertical display area detection signal V_DIS of transitting at last of vertical blanking pulse V_BLK.This address is an address that at first outputs to address counter 5 after first transition of vertical display area detection signal V_DIS.Thereby, also during each horizontal scanning period after first transition of vertical display area detection signal V_DIS, read each of the correction data of reading during the initial horizontal scanning period on the scene.Figure 32 represents state at this moment.Before first transition change of vertical display area detection signal V_DIS with afterwards state between, promptly with between the initial horizontal scanning period of field and the previous horizontal scanning period compare, the convergence correction signal is variation not.Thereby, might prevent to cause display frame in the top edge of picture effective area or near the disorder it by the sudden change of convergence correction signal.
For each horizontal scanning period, address control circuit 19A outputs to address counter to identical address, thereby in each horizontal scanning period, carry out identical convergence correction, up to the last transition of vertical display area detection signal V_DIS and first transition of vertical blanking pulse V_BLK.This address is an address that outputed to address counter 5 before the last transition of vertical display area detection signal V_DIS at last.Thereby, also during each horizontal scanning period after the last transition of vertical display area detection signal V_DIS, read each of the correction data of reading during the initial horizontal scanning period on the scene.Figure 33 represents state at this moment.Before the last transition change of vertical display area detection signal V_DIS with afterwards state between, promptly with between the initial horizontal scanning period of field and the previous horizontal scanning period compare, the convergence correction signal is variation not.Thereby, might prevent to cause display frame in the lower limb of picture effective area or near the disorder it by the sudden change of convergence correction signal.
Figure 34 is a key-drawing, schematically illustrates a kind of like this state on screen.Top edge from the top edge of screen grating to the picture effective area and the lower limb from the lower limb of picture effective area to the screen grating carry out identical and convergence correction that be equal on the vertical direction at it separately.Thereby, can on the top edge of picture display area and lower limb, not change at convergence correction signal under the state of underdevelopment.As a result, might prevent that sudden change by the convergence correction signal from causing the disorder of picture.
Although in this example 7, described wherein convergence correction before first transition of vertical blanking pulse and an example that changes afterwards, but best also has, in other timing place, for example, before the last transition of vertical blanking pulse and afterwards, change convergence correction.
Example 8
What describe in this example is, a kind ofly can be easily correction data be stored in display unit in the memory 6.
Figure 35 represents an example according to a kind of layout of the display unit of example 8.This display unit comprises the display unit shown in Figure 25, to its add one with Figure 25 in those a different picture display circuit 42 and digital convergence correction circuit B4.Be input to picture display circuit A3 from a display area index signal HV_CSL and a check point indicator diagram L_CSL of convergence correction circuit B4 output.And picture display circuit A3 goes up display frame according to any of input picture signal, picture area index signal HV_CSL or check point indicator diagram L_CSL at a CRT (C).
Figure 36 is a calcspar, an example of a kind of layout of convegence correcting device B4 shown in expression Figure 35.This convergence correction circuit B4 comprises the convergence correction circuit shown in Figure 31, and it is added a pattern generating circuit 21.Pattern generating circuit 21 synchronously is created in the check point indicator diagram L_CSL that horizontal direction has preset width according to vertical display area detection signal V_DIS and horizontal display area detection signal H_DIS with system clock.The position of each pattern and width optionally are provided with by a microcomputer of not representing.
Figure 37 is illustrated on the screen example of the check point indicator diagram L_CSL that is shown by picture display circuit A3 and vertical display area detection signal V_DIS and horizontal display area detection signal H_DIS.Under the state of overscanning, must obtain correction data with respect to the whole effective area of picture.In other words, the display area of expression is consistent with the effective area of picture in the drawings.In the figure, the effective area of picture is divided into 25 * 25 points equably, and supposes that left upper end is origin (0,0), specify 25 convergence correction point in order, up to the coordinate (4,4) of bottom righthand side.
Figure 38 represents an example with respect to the adjusting order of each convergence correction point of 25 points shown in Figure 37.At first, the operator of check point given pattern on the view screen is for example by (0,0) → (0,1) → (0,2) → (0,3) → (0,4) → (1,0) → (2,0) → (3,0) → (4,0) → (1,1) → (2,1) → (3,1) → (4,1) → (1,2) → (2,2) → (3,2) → (4,2) → (1,3) → (2,3) → (3,3) → (4,3) → (1,4) → (2,4) order → (3,4) → (4,4), the adjusting of the amount of convergence.Thereby, obtain best convergence correction amount.The convergence correction amount that obtains directly is stored in the convergence correction of memory 6 and puts in the corresponding address as correction data.
Linearity by the correction data in described convergence correction point is inserted, and can obtain the point outside these convergence correction points.In other words, an area that is surrounded by 4 adjacent convergence correction is divided into quarter.Then, for example, with respect to each the convergence correction point that is positioned between coordinate (0,0) and (0,1), use in the coordinate (0,0) and the convergence correction amount in coordinate (0,1) obtain a convergence correction amount.Then, with respect to each the convergence correction point that is positioned between coordinate (0,0) and (1,0), use in the coordinate (0,0) and the convergence correction amount in coordinate (1,0) obtain a convergence correction amount.At this moment, even under the situation that scanning frequency, picture effective area (picture dimension) etc. change, vertical display area detection signal V_DIS is also consistent with the picture effective area with horizontal display area detection signal H_DIS.Therefore, only, just can obtain the convergence correction amount an of the best by being used as variable the time and utilizing vertical yoke current iDYV and the insertion of the linearity of the correlation of horizontal yoke current iDYH between the position on the screen.
By this way, when handle inserts operation with corresponding vertical yoke current iDYV of picture area and horizontal yoke current iDYH as time parameter, might guarantee the precision of convergence correction, and the influence that not changed by scanning frequency and picture dimension.
Although expression wherein is divided into the example that 5 * 5=25 is ordered to the picture effective area equably in Figure 38, might be by the check point given pattern being increased to for example 5 * 9=45 point or, further improving the precision of convergence correction to 9 * 9=81 point.
Example 9
What describe in this example is, a kind ofly comprises that one is used for the display unit of storing and remaining the digital convegence correcting device of correction data with respect to the convergence correction amount of each convergence correction point.Even this display unit under the situation that the corresponding relation between screen grating and the picture effective area changes, the also convergence correction that can wish.
Figure 39 is a calcspar, schematically illustrates an example according to a kind of layout of the display unit of example 9.This display unit comprises the display unit shown in Figure 35, to its add with Figure 35 in different digital convergence correction circuit B5.
Figure 40 is a calcspar, an example of a kind of layout of digital convegence correcting device B5 shown in expression Figure 39.This convergence correction circuit comprises the convergence correction circuit shown in Figure 36, it is added different memory portion 6X, a DAC (8X) and a low-pass filtering part 9X, and do not comprise 1 latch and gate pulse circuit.
Memory portion 6 comprise with the corresponding memory of different frequency 60 to 6n, low pass filter part 9X comprise with the corresponding low pass filter of different frequency 90 to 9n.Frequency detection circuit 12 is selected signal according to horizontal blanking impulse H_BLK and one of vertical blanking pulse V_BLK output, select those memory 6i who forms memory portion 6X, and select those to form the low pass filter 9i of low-pass filtering part 9X.DAC (8X) is one and is used for correction data is converted to the D/A switch circuit of an analog signal, and comprises if the width of correction data is 8 then has the DAC of 8 bit widths.According to the address of reading, synchronously read correction data with screen scanning, and the correction data of reading is converted to an analog signal by DAC (8X) from the memory 6i that selects from address counter 5.Level and smooth this analog signal, and by producing a convergence correction signal with the corresponding low pass filter 9i of the scanning frequency of importing picture signal.
This convegence correcting device comprises a vertical display area testing circuit 17, horizontal display area testing circuit 18, and address control circuit 19A.As a result, with example 4 in identical mode, address counter 5 produces under the situation of overscanning with each convergence correction that is arranged in the picture effective area and puts corresponding address.Under the situation of underdevelopment, produce with each convergence correction that is arranged in the screen grating and put corresponding address.Thereby, all constantly can both carry out and screen grating and picture effective area between the corresponding convergence correction of relation.
On the other hand, under the situation that scanning frequency changes, might be by selecting to handle this variation with the corresponding memory 6i of scanning frequency with the corresponding low pass filter 9i of scanning frequency.As a result, even under the situation that the relation between screen grating and the picture effective area changes owing to scanning frequency, the convergence scanning that also might wish.And, not only under the situation that the relation between screen grating and the picture effective area changes owing to the variation of scanning frequency, and under the situation of same scan frequency, the relation between screen grating and picture effective area not simultaneously, the also convergence correction that can wish.
In the mode identical,, might export a display area index signal HV_CSL according to vertical display area detection signal V_DIS and horizontal display area detection signal H_DIS by index signal generation circuit 20 is provided with example 5.As a result, might on screen, show expression display area periphery edge part rectangular frame picture with obtain vertical active area area of signal V_DIS easily 0Data and horizontal active area area of signal H_DIS 0Data.
And, with example 7 in identical mode, by address control circuit 19A is provided, under the situation of underdevelopment, might prevent the disorder of the display frame that causes in the top edge and the sudden change on the lower limb of grating by the convergence correction signal.

Claims (28)

1. digital convegence correcting device comprises: one be used for for screen on the position memory, of storing correction data with 1 pair 1 corresponding each the convergence correction point of relation be used for synchronously producing the address counter of reading the address with respect to memory with screen scanning; And wherein produce the convergence correction signal according to the correction data of reading;
It is characterized in that described digital convegence correcting device comprises: a vertical yoke current testing circuit is used for the current value of detection of vertical deflection current and generates detection signal;
A vertical display area testing circuit is used for according to described detection signal, produce with export one with screen on the corresponding vertical display area detection signal in picture display area position in vertical direction; With
An address control circuit is used for according to address counter of described vertical display area detection signal control.
2. digital convegence correcting device according to claim 1 is characterized in that: vertical display area testing circuit comprises that is used for the comparator that the current value of vertical yoke current is compared with a predetermined comparison reference, and
Under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in vertical direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in vertical direction is used as a comparison reference.
3. digital convegence correcting device according to claim 2, it is characterized in that: address control circuit under the situation of overscanning in advance vertical display area detection signal, be stored as the signal of the vertical effective area of picture, and under the situation of underdevelopment, obtain the time lag between the variation timing of the variation timing at the vertical effective area signal of picture, vertical display area detection signal, and this time lag is converted to one read the address and output to address counter.
4. digital convegence correcting device according to claim 1, it is characterized in that: comprise an index signal generation circuit, this circuit is used for exporting a display area index signal according to the picture display area of vertical display area detection signal on indication vertical direction on the screen.
5. display unit is characterized in that comprising:
Digital convegence correcting device according to claim 4, and
A picture display circuit is used for according to the picture of display area indication signal from described digital convegence correcting circuit.
6. digital convegence correcting device according to claim 1, it is characterized in that: under the situation of underdevelopment, address control circuit is according to vertical synchronizing signal and vertical display area detection signal, time from the extremely vertical display area change in detection signal of time that vertical synchronizing signal changes, the address of reading during one first horizontal scanning period is outputed to the address counter that is used for each horizontal scanning period.
7. digital convegence correcting device according to claim 1, it is characterized in that: under the situation of underdevelopment, address control circuit is according to vertical synchronizing signal and vertical display area detection signal, time from the extremely vertical display area change in detection signal of time that vertical synchronizing signal changes, the address of reading during a terminal level scan period is outputed to the address counter that is used for each horizontal scanning period.
8. a display unit is characterized in that: comprise digital convegence correcting device according to claim 1.
9. display unit as claimed in claim 8 is characterized in that described vertical display area testing circuit comprises that is used for the comparator that the current value of vertical yoke current is compared with a predetermined comparison reference, and
Under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in vertical direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in vertical direction is used as a comparison reference.
10. display unit as claimed in claim 8, it is characterized in that described address control circuit under the situation of overscanning in advance vertical display area detection signal, be stored as the signal of the vertical effective area of picture, and under the situation of underdevelopment, obtain the time lag between the variation timing of the variation timing at the vertical effective area signal of picture, vertical display area detection signal, and this time lag is converted to one read the address and output to address counter.
11. display unit as claimed in claim 8, it is characterized in that described under the situation of underdevelopment, address control circuit is according to vertical synchronizing signal and vertical display area detection signal, time from the extremely vertical display area change in detection signal of time that vertical synchronizing signal changes, the address of reading during one first horizontal scanning period is outputed to the address counter that is used for each horizontal scanning period.
12. display unit as claimed in claim 8, it is characterized in that described under the situation of underdevelopment, address control circuit is according to vertical synchronizing signal and vertical display area detection signal, time from the extremely vertical display area change in detection signal of time that vertical synchronizing signal changes, the address of reading during a terminal level scan period is outputed to the address counter that is used for each horizontal scanning period.
13. a digital convegence correcting device comprises: one be used for for screen on the position memory, of storing correction data with 1 pair 1 corresponding each the convergence correction point of relation be used for synchronously producing the address counter of reading the address with respect to memory with screen scanning; And wherein produce the convergence correction signal according to the correction data of reading;
It is characterized in that described digital convegence correcting device comprises:
A horizontal yoke current testing circuit is used for the current value of detection level deflection current and generates detection signal;
A horizontal display area testing circuit is used for according to described detection signal, produce and export one with screen on the corresponding horizontal display area detection signal in picture display area position in the horizontal direction; With
An address control circuit is used for according to address counter of horizontal display area detection signal control.
14. digital convegence correcting device according to claim 13 is characterized in that: horizontal display area testing circuit comprises that is used for the comparator that the current value of horizontal yoke current is compared with a predetermined comparison reference, and
Under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in the horizontal direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in the horizontal direction is used as a comparison reference.
15. digital convegence correcting device according to claim 13, it is characterized in that: address control circuit under the situation of overscanning in advance horizontal display area detection signal, be stored as the signal of the horizontal effective area of picture, and under the situation of underdevelopment, obtain the time lag between the variation timing of the variation timing of the horizontal effective area signal of picture, horizontal display area detection signal, and this time lag is converted to one read the address and output to address counter.
16. digital convegence correcting device according to claim 13, it is characterized in that: comprise an index signal generation circuit, this circuit is used for exporting a display area index signal according to the picture display area of horizontal display area detection signal on indication horizontal direction on the screen.
17. a display unit is characterized in that comprising digital convegence correcting device according to claim 13.
18. display unit as claimed in claim 17 is characterized in that described horizontal display area testing circuit comprises that is used for the comparator that the current value of horizontal yoke current is compared with a predetermined comparison reference, and
Under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in the horizontal direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in the horizontal direction is used as a comparison reference.
19. display unit as claimed in claim 17, it is characterized in that address control circuit under the situation of overscanning in advance horizontal display area detection signal, be stored as the signal of the horizontal effective area of picture, and under the situation of underdevelopment, obtain the time lag between the variation timing of the variation timing of the horizontal effective area signal of picture, horizontal display area detection signal, and this time lag is converted to one read the address and output to address counter.
20. a display unit is characterized in that comprising:
Digital convegence correcting device according to claim 16 and
A picture display circuit is used for according to the picture of display area indication signal from described digital convegence correcting circuit.
21. a digital convegence correcting device comprises: one be used for for screen on the position memory, of storing correction data with 1 pair 1 corresponding each the convergence correction point of relation be used for synchronously producing the address counter of reading the address with respect to memory with screen scanning; And wherein produce the convergence correction signal according to the correction data of reading;
It is characterized in that described digital convegence correcting device comprises:
A vertical display area testing circuit, be used for according to vertical yoke current produce with export one with screen on the corresponding vertical display area detection signal in picture display area position in vertical direction;
A horizontal display area testing circuit, be used for according to horizontal yoke current produce and export one with screen on the corresponding horizontal display area detection signal in picture display area position in the horizontal direction; And
An address control circuit is used for according to vertical display area detection signal and address counter of horizontal display area detection signal control.
22. digital convegence correcting device according to claim 21, it is characterized in that: vertical display area testing circuit comprises that is used for the comparator that the current value of vertical yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in vertical direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in vertical direction is used as a comparison reference; And
Horizontal display area testing circuit comprises that is used for the comparator that the current value of horizontal yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in the horizontal direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in the horizontal direction is used as a comparison reference.
23. digital convegence correcting device according to claim 21, it is characterized in that: address control circuit under the situation of overscanning in advance vertical display area detection signal, be stored as the signal of the vertical effective area of picture, and address control circuit under the situation of overscanning in advance horizontal display area detection signal, be stored as the signal of the horizontal effective area of picture, and
Under the situation of underdevelopment, obtain at the vertical effective area signal of picture the variation timing,
Time lag between the variation timing of vertical display area detection signal, and obtain the time lag between the variation timing of the variation timing of the horizontal effective area signal of picture, horizontal display area detection signal, and this time lag is converted to one read the address and output to address counter.
24. digital convegence correcting device according to claim 21, it is characterized in that: comprise an index signal generation circuit, this circuit be used for exporting one according to vertical display area detection signal and horizontal display area detection signal the display area index signal of the picture display area on indication vertical direction on the screen.
25. a display unit is characterized in that comprising digital convegence correcting device according to claim 21.
26. display unit as claimed in claim 25, it is characterized in that described vertical display area testing circuit comprises that is used for the comparator that the current value of vertical yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in vertical direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in vertical direction is used as a comparison reference; And
Horizontal display area testing circuit comprises that is used for the comparator that the current value of horizontal yoke current is compared with a predetermined comparison reference, and under the situation of underdevelopment, the corresponding current value in position with screen grating two ends in the horizontal direction is used as a comparison reference, and under the situation of overscanning, the corresponding current value in position with picture effective area two ends in the horizontal direction is used as a comparison reference.
27. display unit as claimed in claim 25, it is characterized in that described address control circuit under the situation of overscanning in advance vertical display area detection signal, be stored as the signal of the vertical effective area of picture, and address control circuit under the situation of overscanning in advance horizontal display area detection signal, be stored as the signal of the horizontal effective area of picture, and
Under the situation of underdevelopment, obtain the time lag between the variation timing of the variation timing at the vertical effective area signal of picture, vertical display area detection signal, and obtain the time lag between the variation timing of the variation timing of the horizontal effective area signal of picture, horizontal display area detection signal, and this time lag is converted to one read the address and output to address counter.
28. a display unit is characterized in that comprising:
Digital convegence correcting device according to claim 24 and
A picture display circuit is used for according to the picture of display area indication signal from the digital convegence correcting circuit.
CNB971824002A 1997-10-09 1997-10-09 Digital convergence correcting device and display device Expired - Fee Related CN1152580C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB971824002A CN1152580C (en) 1997-10-09 1997-10-09 Digital convergence correcting device and display device

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Application Number Priority Date Filing Date Title
CNB971824002A CN1152580C (en) 1997-10-09 1997-10-09 Digital convergence correcting device and display device

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CN1276128A CN1276128A (en) 2000-12-06
CN1152580C true CN1152580C (en) 2004-06-02

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