CN115250160A

CN115250160A - Signal processing method and device

Info

Publication number: CN115250160A
Application number: CN202110454655.6A
Authority: CN
Inventors: 潘伟; 李建康
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-04-26
Filing date: 2021-04-26
Publication date: 2022-10-28

Abstract

The present application relates to the field of communications technologies, and in particular, to a signal processing method and apparatus. Wherein, the method comprises the following steps: a receiving end receives N continuous NRZ signals from a transmitting end, wherein each NRZ signal in the N continuous NRZ signals is used for bearing a first bit, and N is an integer greater than 1; the receiving end sequentially samples N continuous NRZ signals for N times; and when N is larger than 2, the receiving end determines the value of the first bit according to the sampling results of the Mth sampling to the (N-M + 1) th sampling in the N times of sampling, wherein M is an integer larger than 1 and smaller than N. In the method, the receiving end can utilize the level sampling value of the middle area of N continuous NRZ signals corresponding to the same bit to determine the value of the bit, thereby avoiding or reducing the generation of error bits and reducing the bit error rate.

Description

Signal processing method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a signal processing method and apparatus.

Background

During data transmission, bits in the link may be altered by noise, interference, attenuation or bit synchronization errors, resulting in bit errors (bit errors). Bit errors, also referred to as error bits, refer to bits that are inconsistent between data transmitted by a transmitting end and data received by a receiving end. The ratio of error bits to the total number of transmitted bits per unit time is referred to as a Bit Error Rate (BER).

The bit error rate affects the reliability of data communication. Also, for the maximum transmission capacity of the transmission link, it means that the bit error rate is tolerable (usually, the bit error rate is 10) ^-12 To 10 ^-9 In between, the bit error rate is tolerable), and the transmission rate is increased as much as possible.

Therefore, the bit error rate is reduced, and the reliability of data communication and the maximum transmission capacity of a link are improved.

Disclosure of Invention

The embodiment of the application provides a signal processing method and device, which can reduce the bit error rate of non-return-to-zero (NRZ) signals.

In a first aspect, an embodiment of the present application provides a signal processing method, where a sending end may send N consecutive NRZ signals to a receiving end, where each NRZ signal of the N consecutive NRZ signals is used to carry a first bit, and N is an integer greater than 1; the receiving end sequentially samples the N continuous NRZ signals for N times; and when N is larger than 2, the receiving end determines the value of the first bit according to the sampling results of the Mth to (N-M + 1) th sampling in the N times of sampling, wherein M is an integer larger than 1 and smaller than N.

In the method, the NRZ signal carrying the first bit can be repeated for N times to obtain N continuous NRZ signals, and the receiving end can determine the value of the first bit by using the level sampling result of the middle area of the N continuous NRZ signals, so that the error bit caused by the attenuation of the NRZ signals can be reduced or avoided, and the bit error rate of the NRZ signals is reduced.

In a possible implementation manner, N is an odd number greater than 2, and the determining, by the receiving end, the value of the first bit according to the sampling result of the mth to (N-M + 1) th samples of the N samples includes: and the receiving end determines the value of the first bit according to the sampling result of the (N + 1)/2 th sampling in the N times of sampling.

That is, in this implementation, the first bit value can be determined based on the sampling result of the NRZ signal at the middle position of the signal sequence composed of N consecutive NRZ signals, and the error bit due to the attenuation of the NRZ signal can be reduced.

In a possible implementation manner, N is an even number greater than 2, and the determining, by the receiving end, the value of the first bit according to the sampling result of the mth to (N-M + 1) th samples of the N samples includes: and the receiving end determines the value of the first bit according to the sampling result of the (N/2) th and/or (N + 2)/2 nd sampling in the N times of sampling.

That is, in this implementation, the first bit value may be determined based on the sampling results of two NRZ signals at the middle position of a signal sequence composed of N consecutive NRZ signals, and error bits due to attenuation of the NRZ signals may be reduced.

In one possible implementation, the receiving end sequentially sampling N consecutive NRZ signals by N times includes: the receiving end samples N times in sequence for N continuous NRZ signals according to a first rate, wherein the first rate is equal to the rate of receiving the N continuous NRZ signals by the receiving end.

That is, in this implementation, the receiving end may perform sampling according to the original sampling speed, and does not need to change the sampling speed or mode, thereby reducing the requirements on the device and the power consumption overhead.

In one possible implementation, N is an even number greater than 2; the receiving end sequentially samples N continuous NRZ signals for N times, and the sampling comprises the following steps: for each NRZ signal in N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal by sampling the level of the junction of the NRZ signal and the NRZ signal which is one of the NRZ signals after the NRZ signal; the receiving end determines the value of the first bit according to the sampling result of the (M) th to (N-M + 1) th sampling in the N times of sampling, and the method comprises the following steps: and the receiving end determines the value of the first bit according to the sampling result corresponding to the N/2 th NRZ signal in the N continuous NRZ signals.

That is, in this implementation, in the case where the NRZ signal is repeated or the number of redundancy times is an even number, the level at which adjacent signals meet may be acquired, so that the level of the most middle region in an even number of consecutive NRZ signals may be acquired, and the value of the first bit may be determined accordingly, and the erroneous bit due to the attenuation of the NRZ signal may be reduced.

In one possible implementation, N is an even number greater than 2; the receiving end sequentially samples N continuous NRZ signals for N times, and the sampling comprises the following steps: for each NRZ signal in N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal through the level of the joint of the sampled NRZ signal and the NRZ signal which is previous to the sampled NRZ signal; the receiving end determines the value of the first bit according to the sampling result of the (M) th to (N-M + 1) th sampling in the N times of sampling, and the method comprises the following steps: the receiving end determines the value of the first bit according to the sampling result corresponding to the (N + 2)/2 th NRZ signal in the N continuous NRZ signals.

In one possible implementation, N is equal to 2; the receiving end sequentially samples N continuous NRZ signals for N times, and the sampling comprises the following steps: for each NRZ signal in N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal by sampling the level of the junction of the NRZ signal and the NRZ signal which is one of the NRZ signals after the NRZ signal; the method further comprises the following steps: and the receiving end determines the value of the first bit according to the sampling result corresponding to the N/2 th NRZ signal in the N continuous NRZ signals.

In one possible implementation, N is equal to 2; the receiving end sequentially samples N continuous NRZ signals for N times, and the sampling comprises the following steps: for each NRZ signal in N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal by sampling the level of the junction of the NRZ signal and the NRZ signal which is previous to the NRZ signal; the method further comprises the following steps: the receiving end determines the value of the first bit according to the sampling result corresponding to the (N + 2)/2 th NRZ signal in the N continuous NRZ signals.

That is, in this implementation, in the case where the NRZ signal is repeated or redundant an even number of times, the level at which adjacent signals meet may be acquired, and thus the level of the most central region in an even number of consecutive NRZ signals may be acquired, and the value of the first bit may be determined accordingly to reduce erroneous bits due to attenuation of the NRZ signal.

In a second aspect, an embodiment of the present application provides a signal processing method, including: a receiving end receives N continuous NRZ signals from a transmitting end, wherein each NRZ signal in the N continuous NRZ signals is used for bearing a first bit, and N is an integer larger than 1; the receiving end sequentially samples N continuous NRZ signals for M times, wherein M is a positive integer smaller than N; and the receiving end determines the value of the first bit according to the sampling result of the M times of sampling.

In this method, the receiving end can reduce the error bits by reducing the frequency of sampling.

In one possible implementation, the sequentially sampling, by the receiving end, M times the N consecutive NRZ signals includes: the receiving end sequentially carries out M times of sampling on the N continuous NRZ signals according to a first rate, and the ratio of the first rate to the rate of receiving the N continuous NRZ signals by the receiving end is M: N.

That is, in this implementation, down-sampling may be implemented by reducing the sampling rate to reduce the error bits.

In one possible implementation, M is an odd number; the receiving end determines the value of the first bit according to the sampling result of the M times of sampling, and the determining comprises the following steps: and the receiving end determines the value of the first bit according to the sampling result of the (M + 1)/2 th sampling in the M times of sampling.

That is, in this implementation, the value of the first bit may be determined according to the result of sampling, of the M samples, at a sampling position closer to the middle region of N consecutive NRZ signals, and the error bits due to attenuation of the NRZ signals may be reduced.

In one possible implementation, M is an even number; the receiving end determines the value of the first bit according to the sampling result of the M times of sampling, and the determining comprises the following steps: and the receiving end determines the value of the first bit according to the sampling result of the (M/2) th and/or (M + 2)/2 nd sampling in the M times of sampling.

That is, in this implementation, the value of the first bit may be determined according to the result of sampling, of M samples, at a sampling position closer to the middle region of N consecutive NRZ signals, and the error bit due to the attenuation of the NRZ signal may be reduced.

In one possible implementation, the receiving end sequentially sampling N consecutive NRZ signals M times includes: the receiving end sequentially samples the K-th to (N-K + 1) -th NRZ signals in the N continuous NRZ signals for M times; k is an integer greater than 1 and less than N.

That is, in this implementation, the NRZ signal at the middle position of the signal sequence of N consecutive NRZ signals may be sampled, and the value of the first bit may be determined based on the result of the sampling, and the error bits due to the attenuation of the NRZ signal may be reduced.

In a third aspect, an embodiment of the present application provides a signal processing apparatus, including: a communication unit, configured to receive N consecutive NRZ signals from a transmitting end, where each of the N consecutive NRZ signals is used to carry a first bit, and N is an integer greater than 1; a sampling unit for sequentially sampling N consecutive NRZ signals for N times; and a determining unit, configured to determine a value of the first bit according to sampling results of an mth sampling to an (N-M + 1) th sampling among the N samplings when N is greater than 2, where M is an integer greater than 1 and less than N.

In a possible implementation manner, N is an odd number greater than 2, and the determining unit is further configured to determine the value of the first bit according to a sampling result of (N + 1)/2 samples in the N samples.

In a possible implementation manner, N is an even number greater than 2, and the determining unit is further configured to determine the value of the first bit according to a sampling result of the (N/2) th and/or (N + 2)/2 nd sampling of the N samples.

In a possible implementation manner, the sampling unit is further configured to sample N consecutive NRZ signals sequentially at a first rate, where the first rate is equal to a rate at which the receiving end receives the N consecutive NRZ signals.

In one possible implementation, N is an even number greater than 2; the sampling unit is further used for obtaining a sampling result corresponding to each NRZ signal in the N continuous NRZ signals by sampling the level of the junction of the NRZ signal and the NRZ signal which is next to the NRZ signal; the determining unit is further configured to determine, by the receiving end, a value of the first bit according to a sampling result corresponding to an N/2 th NRZ signal of the N consecutive NRZ signals.

In one possible implementation, N is an even number greater than 2; the sampling unit is further used for obtaining a sampling result corresponding to each NRZ signal in N continuous NRZ signals by sampling the level of the junction of the NRZ signal and the NRZ signal which is previous to the NRZ signal; the determining unit is further configured to, at the receiving end, determine a value of the first bit according to a sampling result corresponding to the (N + 2)/2 nd NRZ signal of the N consecutive NRZ signals.

In one possible implementation, N is equal to 2; the sampling unit is further used for obtaining a sampling result corresponding to each NRZ signal in the N continuous NRZ signals by sampling the level of the junction of the NRZ signal and the NRZ signal which is one of the NRZ signals; the determining unit is further configured to determine a value of the first bit based on a sampling result corresponding to an N/2 th NRZ signal of the N consecutive NRZ signals.

In one possible implementation, N is equal to 2; the sampling unit is further used for obtaining a sampling result corresponding to each NRZ signal in N continuous NRZ signals by sampling the level of the junction of the NRZ signal and the NRZ signal which is previous to the NRZ signal; the determination unit is further configured to determine a value of the first bit based on a sampling result corresponding to (N + 2)/2 th NRZ signal of the N consecutive NRZ signals.

In a fourth aspect, an embodiment of the present application provides a signal processing apparatus, including: a communication unit, configured to receive N consecutive NRZ signals from a transmitting end, where each of the N consecutive NRZ signals is used to carry a first bit, and N is an integer greater than 1; a sampling unit, configured to sequentially sample N consecutive NRZ signals M times, where M is a positive integer smaller than N; and the determining unit is used for determining the value of the first bit according to the sampling result of the M times of sampling.

In a possible implementation manner, the sampling unit is further configured to sequentially sample N consecutive NRZ signals M times according to a first rate, where a ratio of the first rate to a rate at which the receiving end receives the N consecutive NRZ signals is M: N.

In one possible implementation, M is an odd number; the determining unit is further configured to determine a value of the first bit according to a sampling result of (M + 1)/2 th sampling of the M times of sampling.

In one possible implementation, M is an even number; the determining unit is further configured to determine a value of the first bit according to a sampling result of the (M/2) th and/or (M + 2)/2 nd sampling of the M samples.

In a possible implementation manner, the sampling unit is further configured to sequentially sample, for M times, the kth to (N-K + 1) th NRZ signals of the N consecutive NRZ signals; k is an integer greater than 1 and less than N.

In a fifth aspect, an embodiment of the present application provides a communication system, including a sending end and a receiving end, where the sending end is configured to send N consecutive NRZ signals to the receiving end, where each NRZ signal of the N consecutive NRZ signals is used to carry a first bit, and N is an integer greater than 1; the receiving end is used for sequentially carrying out N times of sampling on the N continuous NRZ signals; and when N is greater than 2, the receiving end is configured to determine a value of the first bit according to sampling results of an mth sampling to an (N-M + 1) th sampling in the N samplings, where M is an integer greater than 1 and less than N.

In a sixth aspect, an embodiment of the present application provides a communication system, including a sending end and a receiving end, where the sending end is configured to send N consecutive NRZ signals to the receiving end, where each NRZ signal of the N consecutive NRZ signals is used to carry a first bit, and N is an integer greater than 1; the receiving end is used for sequentially carrying out M times of sampling on the N continuous NRZ signals, wherein M is a positive integer smaller than N; and the receiving end is used for determining the value of the first bit according to the sampling result of the M times of sampling.

In a seventh aspect, an embodiment of the present application provides a chip system, which is characterized by including an interface circuit, configured to implement the method described in any one of the first aspect to the second aspect (or implement any one of possible implementations thereof).

By the signal processing method provided by the embodiment of the application, the receiving end can determine the value of the bit by using the level sampling value of the middle area of the N continuous NRZ signals corresponding to the same bit, thereby avoiding or reducing the generation of error bits and reducing the bit error rate.

Drawings

FIG. 1 is a schematic diagram of an NRZ signal;

FIG. 2 is a schematic diagram of NRZ signal attenuation;

fig. 3 is a schematic diagram of a communication system according to an embodiment of the present application;

fig. 4 is a flowchart of a signal processing method according to an embodiment of the present disclosure;

fig. 5A is a schematic diagram of a sample of an NRZ signal according to an embodiment of the present application;

fig. 5B is a schematic diagram of a sample of an NRZ signal according to an embodiment of the present application;

fig. 6A is a schematic diagram of a sample of an NRZ signal according to an embodiment of the present application;

fig. 6B is a schematic diagram of a sample of an NRZ signal according to an embodiment of the present application;

fig. 7 is a flowchart of a signal processing method according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a signal processing apparatus according to an embodiment of the present application.

Detailed Description

The technical solution in the embodiments of the present invention will be described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the specification. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise.

Wherein in the description of the present specification, "/" indicates a meaning, for example, a/B may indicate a or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present specification, "a plurality" means two or more.

In the description of the present specification, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

In a data transmission system, a transmitting end can use different level signals to carry different digital information. For example, a high level signal is used to carry a bit with a value of 1 and a low level signal is used to carry a bit with a value of 0. The sending end sends the level signal carrying the digital information to the receiving end, and the receiving end determines the digital information carried by the level signal by detecting the level of the level signal received by the receiving end.

The level signal may be attenuated when transmitted on a link between a transmitting end and a receiving end. Especially in case of long links, the attenuation will be severe. This makes it difficult for the receiving end to determine the digital information actually carried by the level signal. For example, for a high-level signal with attenuation, the receiving end may determine the high-level signal as a low-level signal, so that it is difficult for the receiving end to correctly analyze digital information carried by the level signal, thereby resulting in a high Bit Error Rate (BER).

In order to reduce the influence of the error rate on the data communication and improve the reliability of the data communication, a solution is to use a Forward Error Correction (FEC) technique. In this scheme, the transmitting end transmits additional or redundant information when transmitting data. When an error bit occurs, the receiving end can correct the error bit using the redundant information. In FEC technology, a common group package of multiple lanes (lane) in a link is generally required to uniformly protect data in the multiple lanes. Therefore, the FEC technique is not suitable for transmission protection of a small packet (e.g., a SKP (skip ordered set) type packet) transmitted on a single channel.

Where the bottom layer inserts packets for data from higher layers, such as the data link layer. These packets may be referred to as insert-type packets. The insert-type packets are transported through a single channel, i.e. one insert-type packet is transported through one channel. In the traditional scheme, the insertion type packet is only used for transmission between bottom layers, and after a receiving end receives data from a sending end, the insertion type packet in the data is discarded and then the data is transmitted to a high layer. Currently, there are proposals to utilize the insertion type packet to carry useful information to fully utilize the transmission resources of the data link. In this case, it is difficult to transport-protect the useful information carried by the insertion type packet using the FEC technique.

Another solution to reduce the impact of error rates on data communications is to employ Cyclic Redundancy Check (CRC) and data retransmission. The scheme corrects error bits by retransmitting data, and when the bit error rate is high, the link overhead is high.

Yet another solution to reduce the impact of error rates on data communication is to encode the data using a coding technique like hamming (hashing) coding, such as eBCH coding. The scheme is complex, the power consumption is large, and the required chip area is large.

Yet another solution to reduce the impact of error rates on data communication is to redundantly encode the data. Specifically, the transmitting end repeats each bit a plurality of times, and when the receiving end detects the value of the bit, if the two detection values are the same, the value of the bit is regarded as the detection value. The scheme has poor effect and low accuracy of detection results.

The embodiment of the present application provides a signal processing method, wherein when a sending end sends data, a NRZ signal of one bit may be repeated N times to obtain N consecutive NRZ signals, and then the N consecutive NRZ signals are sent. When receiving the N continuous NRZ signals, the receiving end sequentially performs N sampling on the N continuous NRZ signals to obtain N sampling values. Then, the bit value of the bit A1 is determined from the sample value at the middle position among the N sample values, that is, whether the value of the bit A1 is 1 or 0 is determined.

The sampling value may also be referred to as a sampling result. The sample value at the middle position in the above N sample values refers to the sample value at the middle position in the sample value sequence. The sampling value sequence is formed by the N sampling values according to the sequence of N times of sampling. The nth sample value in the N sample values refers to the nth sample value in the sample value sequence. In other words, the nth sample value in the sample value sequence, or the nth sample value in the N sample values, is the sampling result of the nth sample in the N samples. n takes the value in the interval [1, N ].

And the bit value of the corresponding bit is determined according to the sampling value in the middle position, so that error bits can be avoided or reduced, and the bit error rate is further reduced. The reason is specifically as follows.

NRZ signals are signals based on NRZ codes (non return zero codes) which carry or represent different bit values with levels of different sizes. For example, a high level (3V) represents 1, and a low level (e.g., -3V) represents 0.

Referring to fig. 1, unlike the RZ signal based on the RN code, the level of the NRZ signal does not need to be reset to zero, that is, the NRZ signal can be used to transmit data all in one signal period, or in other words, the level does not need to be changed (the level does not need to be reset to zero) in one signal period. In the bit A3 and the bit A4 shown in fig. 1, when the bit values of two adjacent bits are the same, the level does not need to be changed during two signal periods. That is, the level is kept constant in both signal periods without considering signal impairment factors such as interference, fading, etc.

It will be appreciated that the NRZ signal may be subject to attenuation during transmission over the link, and that significant attenuation of the NRZ signal may occur particularly when the link is long. The attenuated NRZ signal may be as shown in figure 2. Wherein, when two adjacent NRZ signals are different in level (i.e., the two NRZ signals represent different bit values), a portion of one of the NRZ signals close to the other NRZ signal is more affected by attenuation. That is, two adjacent different levels are susceptible to damage during link transmission. When two adjacent NRZ signals have the same level (i.e., represent the same bit value), the margin where the two NRZ signals meet is large, and the influence of attenuation is small. That is, the joint of two adjacent identical levels is not easily damaged during the link transmission process. When the three or more NRZ signals are the same in level, the margin of the NRZ signal at the middle position among the three or more NRZ signals is large, and the influence by attenuation is small. That is, the NRZ signal at the middle position among the three or more NRZ signals is not easily damaged during the link transmission.

Of N sample values obtained by sequentially sampling N consecutive NRZ signals, the sample value at the middle position is obtained by sampling the middle position (the middle NRZ signal or the contact portion between adjacent NRZ signals) of the N consecutive NRZ signals, and is less affected by attenuation. The bit value is determined according to the sampling value at the middle position, so that error bits can be avoided or reduced, and the bit error rate is further reduced.

Next, with reference to the accompanying drawings, an example of a signal processing method provided by the embodiment of the present application is described.

Fig. 3 illustrates a communication system provided in an embodiment of the present application, which includes a device (device) 100 and a device 200. The apparatus 100 or the apparatus 200 may be any device, apparatus or platform having a data processing function and a data transceiving function. In some embodiments, the device 100 or the device 200 may be a server, a base station, or other service-side or network-side device. In some embodiments, device 100 or device 200 may be a user-side device such as a cell phone, tablet, or the like. The embodiment of the present application does not limit the specific implementation form or form of the apparatus 100 or the apparatus 200.

The device 100 and the device 200 may exchange information or transmit data via a wired link or a wireless link.

In some embodiments, device 100 and device 200 may perform data transfer via a peripheral component interconnect express (PCIe) bus.

Referring to fig. 3, in some embodiments, device 100 may act as a data sender to send data to device 200 via send port 110. Device 200 may act as a data sink receiving data from device 100 via receive port 210. In some embodiments, device 200 may act as a data sender to send data to device 100 through a send port 220. Device 100 may act as a data sink to receive data from device 200 via receive port 120.

Next, taking the device 100 as a data sending end and the device 200 as a data receiving end as an example, the signal processing method provided in this embodiment of the present application is described.

The device 100 may use the NRZ signal to carry data that it needs to send out, which may be a bit sequence composed of a plurality of bits, such as bit A1, bit A2, bit A3, bit A4 shown in fig. 3. The apparatus 100 may map each bit in the bit sequence to an NRZ signal according to its bit value. A plurality of bits may be mapped into a plurality of NRZ signals. The plurality of NRZ signals constitute an initial NRZ signal sequence. As shown in fig. 3, bit A1, bit A2, bit A3, and bit A4 may be mapped to an initial NRZ signal sequence consisting of a high NRZ signal, a low NRZ signal, and two consecutive high NRZ signals.

The apparatus 100 may comprise a redundancy message generation module 130 which may convert the initial NRZ signal sequence into a redundant NRZ signal sequence. Each NRZ signal in the initial NRZ signal sequence may be repeated N times. Thus, each NRZ signal in the initial NRZ signal corresponds to N NRZ signals, or, in other words, each bit in the bit sequence corresponds to N NRZ signals. Wherein, the N NRZ signals corresponding to the same bit are connected in sequence. N NRZ signals corresponding to all bits in the bit sequence are connected in sequence according to the sequence of the bits in the bit sequence to form a redundant NRZ signal sequence. Specifically, as shown in fig. 3, N may be set to 3, and the redundant packet generating module 130 may repeat the NRZ signal corresponding to the bit A1 for 3 times to obtain 3 NRZ signals having the same level and being connected in sequence. Bit A1 may be referred to, and bit A2, bit A3, and bit A4 may be processed separately. The 3 NRZ signals corresponding to the bit A1, the 3 NRZ signals corresponding to the bit A2, the 3 NRZ signals corresponding to the bit A3, and the 3 NRZ signals corresponding to the bit A4 are connected in sequence to obtain a redundant NRZ signal sequence as shown in fig. 3.

In addition, the apparatus 100 may notify the apparatus 200 of the number of repetitions of each NRZ signal (i.e., N times). Alternatively, the device 100 and the device 200 may negotiate the number of repetitions of each NRZ signal, and the device 100 may repeat or redundantly process the NRZ signal according to the result of the negotiation (i.e., N times).

The apparatus 100 may sequentially transmit NRZ signals to the apparatus 200 through the transmission port 100 in the order of NRZ signals in the redundant NRZ signal sequence.

Referring to fig. 3, the device 200 may receive an NRZ signal from the device 100 through the receiving port 210, sample the received NRZ signal by using the sampling module 230, and determine a bit value corresponding to the NRZ signal, that is, determine a bit value of a bit carried by the NRZ signal according to a sampling result. The bit values are 0 and 1. The bit value of one bit is either 0 or 1. The bit value of a bit may be simply referred to as the value of the bit.

Next, referring to fig. 4, taking the NRZ signal corresponding to the bit A1 as an example, an example will be described of a value scheme in which the apparatus 200 determines the bit carried by the NRZ signal.

Referring to fig. 4, the apparatus 100 may receive N consecutive NRZ signals from the apparatus 100, the N NRZ signals corresponding to N bits A1 one-to-one, through step 401. I.e. the N signals are obtained by the device 100 redundantly coding or repetition coding the bit A1N times. The N consecutive NRZ signals mean that the N NRZ signals are sequentially connected, or that level pulses of N signal periods are sequentially connected.

With continued reference to fig. 4, the apparatus 200 may perform step 402, which may be performed N times in sequence for N consecutive NRZ signals. It is to be understood that one NRZ signal may be a level pulse lasting one signal period, and N consecutive NRZ signals may refer to a level pulse lasting N consecutive signal periods. Sequentially sampling N consecutive NRZ signals N times may refer to performing level sampling on N different positions on a level pulse lasting N consecutive signal periods, respectively, to obtain N level sampling values or measurement values.

The apparatus 200 may perform step 403 to determine the value of bit A1 based on the sample value at the middle position of the N sample values. The middle position is the middle position of the sequence of N sample values.

Next, the implementation procedure of step 402 and step 403 is described by way of example with reference to specific values of N.

In some embodiments, N may be an integer greater than 2, and the sample value at the middle position may refer to the M-th to (N-M + 1) -th sample values of the N sample values, where M is an integer greater than 1 and less than N.

In one illustrative example, the apparatus 200 may sample N consecutive NRZ signals in sequence, at a speed of B1. Where speed B1 is equal to the speed at which the apparatus 200 receives N consecutive NRZ signals. That is, in this example, the N consecutive NRZ signals may be sampled at the original sampling rate without changing the sampling rate of the device 200.

In one illustrative example, N may be an odd number greater than 2, and the sample value at the intermediate position is the (N + 1)/2 th sample value of the N sample values. In this example, each of N consecutive NRZ signals may be sampled, resulting in the N sample values. Then, the value of the bit A1 is determined from (N + 1)/2 sample values among the N sample values.

In one example, referring to fig. 5A, assuming that N is 3, the apparatus 200 may perform 1 st sampling on the 1 st NRZ signal of 3 consecutive NRZ signals received to obtain a1 st sampling value. The 2 nd sampling is performed on the 2 nd NRZ signal among the 3 consecutive NRZ signals to obtain the 2 nd sampling value. The 3 rd sampling is performed on the 3 rd NRZ signal of the 3 consecutive NRZ signals to obtain a3 rd sampling value. Thus, 3 sample values are obtained. The result of (3 + 1)/2 samples of the 3 samples is the 2 nd sample. The device 200 may determine the value of bit A1 based on the 2 nd sample value.

In one illustrative example, N may be an even number greater than 2, with the sample values in the middle being the nth/2 and (N + 2)/2 samples of the N sample values. In this example, each of N consecutive NRZ signals may be sampled, resulting in the N sample values. Then, the value of the bit A1 is determined based on the N/2 th and (N + 2)/2 th sample values among the N sample values. Specifically, it may be determined whether the bit value determined from the (N/2) th sample value is the same as the bit value determined from the (N + 2)/2 th sample value (i.e., is 1 or 0 at the same time), and if the bit values are the same, the same bit value is determined as the value of the bit A1.

In one example, referring to fig. 5B, assuming that N is 4, the apparatus 200 may perform 1 st sampling on the 1 st NRZ signal of 4 consecutive NRZ signals received to obtain a1 st sampling value. The 2 nd sampling is performed on the 2 nd NRZ signal among the 4 consecutive NRZ signals to obtain the 2 nd sampling value. The 3 rd sampling is performed on the 3 rd NRZ signal of the 4 consecutive NRZ signals to obtain a3 rd sampling value. The 4 th sampling is performed on the 4 th NRZ signal of the 4 consecutive NRZ signals to obtain a4 th sampling value. Thus, 4 sampling values are obtained. The 4/2 sample value of the 4 sample values results in the 2 nd sample value. The (4 + 2)/2 sampling value of the 4 sampling values is the 3 rd sampling value. The apparatus 200 may determine the value of bit A1 based on the 2 nd and 3 rd sample values. And if the bit value determined according to the 2 nd sampling value is equal to the bit value determined according to the 3 rd sampling value, determining that the bit value is the value of the bit A1.

In one illustrative example, N may be an even number greater than 2, with the sample value at the middle being the Nth/2 sample value of the N sample values. The value of bit A1 may be determined from the nth/2 sample value.

In one illustrative example, N may be an even number greater than 2, and the sample value at the middle position is the (N + 2)/2 th sample value of the N sample values. The value of bit A1 may be determined from the (N + 2)/2 th sample value.

In some embodiments, in the case where N is an even number, the level at the junction of two adjacent NRZ signals may be collected to obtain a sample value. N consecutive NRZ signals, N sample values can be obtained. Then, the value of bit A1 is determined based on the sample value at the middle position among the N sample values.

In one illustrative example, referring to fig. 6A, for each of N consecutive NRZ signals, a sample value corresponding to the NRZ signal is obtained by sampling a level at a junction of the NRZ signal and a subsequent NRZ signal of the NRZ signal. In this way, N sample values can be obtained, which correspond one-to-one to the N NRZ signals. It will be appreciated that N successive NRZ signals are level pulses that last N signal periods. The level of the middle region of the level pulse is acquired by the nth/2 sampling of the N samplings. The level in the middle region of the level pulse is less affected by the attenuation, and the actual bit value of the bit A1 can be obtained or is most likely obtained by determining the value of the bit A1 using its sampled or measured value.

For an NRZ signal, for example the NRZ signal C1, the following NRZ signal refers to the NRZ signal that is located after the NRZ signal C1 and adjacent or succeeding the NRZ signal C1 in the transmission link. That is, the receiving side receives the NRZ signal C1 first, and receives an NRZ signal immediately after the NRZ signal C1.

In one example, as shown in fig. 6A, N may be assumed to be 4. In the 1 st sampling, the level at the junction of the 1 st NRZ signal and the 2 nd NRZ signal of 4 consecutive NRZ signals may be sampled to obtain a1 st sampled value. In the 2 nd sampling, the level at the junction of the 2 nd NRZ signal and the 3 rd NRZ signal of 4 consecutive NRZ signals may be sampled to obtain a2 nd sampled value. In the 3 rd sampling, the level at the junction of the 3 rd NRZ signal and the 4 th NRZ signal among the 4 consecutive NRZ signals may be sampled to obtain a3 rd sampled value. In the 4 th sampling, the level at the junction of the 4 th NRZ signal and the subsequent NRZ signal (one NRZ signal of the bit after the bit A1) of the 4 consecutive NRZ signals may be sampled to obtain a sampling value of the 4 th sampling. Thus, 4 samples can be obtained. The value of bit A1 may be determined from the 2 nd of the 4 samples, i.e. the 2 nd of the 4 samples.

Illustratively, sampling where two adjacent NRZ signals meet may be achieved by shifting the phase of the sampling clock of the NRZ signals, as shown in fig. 6A. Specifically, as shown in fig. 6A, the rising edge of the clock signal may be set to correspond to the middle region of the NRZ signal, that is, the rising edge may correspond to the middle region of the level pulse lasting for one signal period. Accordingly, the falling edge of the clock signal corresponds to the junction of two adjacent NRZ signals. The sampling may be performed with a phase shifted backward by 180 °, so that the NRZ signal should be sampled at the rising edge of the clock signal, and the NRZ signal should be converted to be sampled at the falling edge of the clock signal, thereby realizing the sampling of the junction of two adjacent NRZ signals.

In one illustrative example, referring to fig. 6B, for each of N consecutive NRZ signals, a sample value corresponding to the NRZ signal is obtained by sampling a level at a junction of the NRZ signal and a previous NRZ signal of the NRZ signal. In this way, N sample values can be obtained, which correspond one-to-one to the N NRZ signals. It will be appreciated that N successive NRZ signals are level pulses that last N signal periods. The (N + 2)/2 samples of the N samples acquire the levels of the middle region of N consecutive NRZ signals. The level in the middle region of the level pulse is less affected by the attenuation, and the actual bit value of the bit A1 can be obtained or is most likely obtained by determining the value of the bit A1 using its sampled or measured value.

For an NRZ signal, for example the NRZ signal C1, the preceding NRZ signal thereof refers to the NRZ signal which precedes the NRZ signal C1 in the transmission link and is adjacent to or subsequent to the NRZ signal C1. That is, the receiving end receives the NRZ signal immediately before the NRZ signal C1 and then receives the NRZ signal C1.

In one example, as shown in fig. 6B, N may be assumed to be 4. In the first sampling, the level at the junction of the 1 st NRZ signal and the previous NRZ signal (one NRZ signal of a bit preceding bit A1) among 4 consecutive NRZ signals may be sampled to obtain a sampling value of the 1 st sampling. In the 2 nd sampling, the level at the junction of the 1 st NRZ signal and the 2 nd NRZ signal of 4 consecutive NRZ signals may be sampled to obtain a2 nd sampled sample value. In the 3 rd sampling, the level at the junction of the 2 nd NRZ signal and the 3 rd NRZ signal of 4 consecutive NRZ signals may be sampled to obtain a3 rd sampled value. In the 4 th sampling, the level at the junction of the 3 rd NRZ signal and the 4 th NRZ signal among the 4 consecutive NRZ signals may be sampled to obtain a4 th sampled value. Thus, 4 samples can be obtained. The value of bit A1 may be determined from the 3 rd sample value of the 4 sample values, i.e. the 3 rd sample value of the 4 samples.

Illustratively, sampling where two adjacent NRZ signals meet may be achieved by shifting the phase of the sampling clock of the NRZ signals, as shown in fig. 6B. Specifically, as shown in fig. 6B, the rising edge of the clock signal may be set to correspond to the middle region of the NRZ signal, that is, the rising edge may correspond to the middle region of the level pulse lasting for one signal period. Accordingly, the falling edge of the clock signal corresponds to the junction of two adjacent NRZ signals. The sampling can be performed with a phase shifted forward by 180 ° so that the NRZ signal should be sampled at the rising edge of the clock signal, and the NRZ signal should be sampled at the falling edge of the clock signal, whereby the sampling at the junction of two adjacent NRZ signals can be realized.

According to the signal processing method provided by the embodiment of the application, under the condition of carrying out repeated processing on the NRZ signal, the receiving end determines the value of the bit by using the level sampling value of the middle area of the repeated NRZ signal, so that the generation of error bits can be avoided or reduced, and the bit error rate is reduced. Moreover, the signal processing method provided by the embodiment of the present application may be applied to transmission protection of a bottom layer (for example, a physical layer) insertion type packet, and reduce a bit error rate of the insertion type packet in a transmission link, so that when the insertion type packet carries useful information, the useful information may be protected, and thus, the useful information may be effectively transmitted to a receiving end.

Referring to fig. 7, an embodiment of the present application provides a signal processing method, which may be applied to the communication system shown in fig. 3. The method may include the following steps.

The apparatus 100 may transmit N consecutive NRZ signals, which correspond one-to-one to the N bits A1, to the apparatus 200 through step 701. That is, each NRZ signal is used to carry a bit A1, N being an integer greater than 1.

The apparatus 200 may perform step 702 to sequentially sample M' times N consecutive NRZ signals. M' is a positive integer less than N. That is, the apparatus 200 may reduce the frequency of sampling the NRZ signal to reduce the bit error rate. The apparatus 200 may sample the levels of the middle regions of N consecutive NRZ signals, or the levels of the middle regions of a level pulse lasting N signal periods, by reducing the frequency at which the NRZ signal is sampled, so that the apparatus 200 may obtain M' sampling results or values.

In some embodiments, the apparatus 200 may reduce the sampling rate of the NRZ signal to achieve down-sampling. I.e., the device 200 samples the NRZ signal at a rate less than the rate at which the device 200 receives the NRZ signal. Illustratively, the apparatus 200 may sample the N consecutive NRZ signals at M'/N of the rate at which it receives the N consecutive NRZ signals. Thereby, M' sample values are obtained. The apparatus 200 may set a sampling rate of the NRZ signal, which may refer to the description of the prior art and will not be described herein.

The device 200 may perform step 703 to determine the value of bit A1 based on the sampling results of the M' samples.

In some embodiments, where M ' is an odd number, the apparatus 200 may determine the value of the bit A1 based on the (M ' + 1)/2 th sample value that is the middle sample value of the M ' sample values.

In one illustrative example, where M' is 1, the device 200 samples the middle region of N consecutive NRZ signals once and determines the value of bit A1 based on the result of the sampling. In other words, the device 200 may sample the middle region of the level pulse lasting N signal periods, resulting in a sampling result. And determines the value of bit A1 based on the sampling result. Illustratively, the middle region may be a middle region of the level pulse.

In one example of this example, where N is an odd number, the apparatus 200 may sample (N + 1)/2 th NRZ signals among N consecutive NRZ signals and determine the value of the bit A1 according to the result of the sampling.

In one example of this example, where N is an even number, the apparatus 200 may sample an nth/2 nd NRZ signal among N consecutive NRZ signals and determine a value of the bit A1 according to a result of the sampling.

In one example of this example, where N is an even number, the apparatus 200 may sample (N + 2)/2 th NRZ signal among N consecutive NRZ signals and determine the value of the bit A1 according to the result of the sampling.

In one example of this example, where N is an even number, the apparatus 200 may sample the N/2 th NRZ signal and the (N + 2)/2 nd NRZ signal, respectively, of the N consecutive NRZ signals, and determine the value of the bit A1 according to the result of the two-time sampling. For the scheme of determining the value of the bit A1 according to the result of two sampling, reference may be made to the above description of the embodiment shown in fig. 5B, and details thereof are not repeated here.

In one example of this example, where N is an even number, the apparatus 200 may sample at the junction of the (N/2) th NRZ signal and the (N + 2)/2 nd NRZ signal among the N consecutive NRZ signals and determine the value of the bit A1 according to the result of the sampling. For the sampling scheme at the joint of two adjacent NRZ signals, reference may be made to the above description of the embodiment shown in fig. 6A or fig. 6B, and details are not repeated here.

In some embodiments, where M 'is an even number, the apparatus 200 may determine the value of the bit A1 based on the M'/2 and the (M '+ 2)/2 samples of the M' samples. Specifically, when the bit value determined from the M '/2 th sample value and the bit value determined from the (M' + 2)/2 th sample value are the same, the same bit value may be taken as the value of the bit A1.

In some embodiments, where M 'is an even number, the apparatus 200 may determine the value of bit A1 based on the M/2 sample value of the M' sample values.

In some embodiments, where M 'is an even number, the apparatus 200 may determine the value of bit A1 based on the (M + 2)/2 samples of the M' samples.

In some embodiments, in step 703, the apparatus 200 may sequentially sample the K-th to (N-K + 1) -th NRZ signals of the N consecutive NRZ signals by M times. Wherein K is an integer greater than 1 and less than N. That is, the apparatus 200 may sample one or more of the N consecutive NRZ signals. The one or more NRZ signals are located at intermediate positions of the N consecutive NRZ signals.

Illustratively, the apparatus 200 may perform reception of the NRZ signal using a counter (counter), and may sample the most recently received NRZ signal when the counter counts to a preset value. Thus, the apparatus 200 may selectively sample the received NRZ signal. In addition, the selective sampling scheme of the NRZ signal by the apparatus 200 can refer to the description of the prior art, and will not be described herein.

According to the signal processing method provided by the embodiment of the application, under the condition of carrying out repeated processing on the NRZ signal, the receiving end determines the value of the bit by using the level sampling value of the middle area of the repeated NRZ signal, so that the generation of error bits can be avoided or reduced to the maximum extent, and the bit error rate is reduced. Moreover, the signal processing method provided by the embodiment of the present application may be applied to transmission protection of a bottom layer (for example, a physical layer) insertion type packet, and reduce a bit error rate of the insertion type packet in a transmission link, so that when the insertion type packet carries useful information, the useful information may be protected, and thus, the useful information may be effectively transmitted to a receiving end.

The embodiment of the application provides a signal processing device. Referring to fig. 8, the apparatus includes:

a communication unit 810 configured to receive N consecutive NRZ signals from a transmitting end, each of the N consecutive NRZ signals being used to carry a first bit, N being an integer greater than 1;

a sampling unit 820 for sequentially sampling the N consecutive NRZ signals N times;

a determining unit 830, configured to determine a value of the first bit according to sampling results of an mth sample to an (N-M + 1) th sample of the N samples, when N is greater than 2, where M is an integer greater than 1 and less than N.

The functions of the functional units of the signal processing apparatus provided in the embodiment of the present application may be implemented by referring to the embodiments shown in fig. 4, which are not described herein again.

The embodiment of the application provides a signal processing device. With continued reference to fig. 8, the apparatus includes:

a sampling unit 820, configured to sequentially perform M 'times of sampling on the N consecutive NRZ signals, where M' is a positive integer smaller than N;

a determining unit 830, configured to determine a value of the first bit according to the sampling result of the M' times of sampling.

The functions of the functional units of the signal processing apparatus provided in the embodiment of the present application may be implemented by referring to the embodiments shown in fig. 7, which are not described again here.

An embodiment of the present application provides a chip system, including: interface circuitry to perform the operations of the apparatus 200 in the embodiments described above, such as the operations of the apparatus 200 in the embodiments shown in fig. 4 or fig. 7.

The method steps in the embodiments of the present application may be implemented by hardware, or may be implemented by software instructions executed by a processor. The software instructions may consist of corresponding software modules that may be stored in Random Access Memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically Erasable PROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.

It is to be understood that the various numerical references referred to in the embodiments of the present application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of the present application.

Claims

1. A signal processing method, comprising:

a receiving end receives N continuous NRZ signals from a transmitting end, wherein each NRZ signal in the N continuous NRZ signals is used for bearing a first bit, and N is an integer greater than 1;

the receiving end sequentially samples the N continuous NRZ signals for N times;

and when N is larger than 2, the receiving end determines the value of the first bit according to the sampling results of the Mth sampling to the (N-M + 1) th sampling in the N times of sampling, wherein M is an integer larger than 1 and smaller than N.

2. The method of claim 1, wherein N is an odd number greater than 2, and wherein the determining, by the receiving end, the value of the first bit according to the sampling result of the mth sample to the (N-M + 1) th sample of the N samples comprises:

and the receiving end determines the value of the first bit according to the sampling result of the (N + 1)/2 th sampling in the N times of sampling.

3. The method of claim 1, wherein N is an even number greater than 2, and wherein the determining, by the receiving end, the value of the first bit according to the sampling result of the mth sample to the (N-M + 1) th sample of the N samples comprises:

and the receiving end determines the value of the first bit according to the sampling result of the (N/2) th and/or (N + 2)/2 nd sampling in the N times of sampling.

4. The method of any of claims 1-3, wherein the receiving end sequentially sampling the N consecutive NRZ signals N times comprises:

and the receiving end sequentially samples the N continuous NRZ signals for N times according to a first rate, wherein the first rate is equal to the rate of receiving the N continuous NRZ signals by the receiving end.

5. The method of claim 1, wherein N is an even number greater than 2;

the receiving end sequentially sampling the N continuous NRZ signals for N times by the receiving end comprises the following steps: for each NRZ signal in the N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal by sampling the level of the junction of the NRZ signal and the NRZ signal which is the next NRZ signal of the NRZ signals;

the determining, by the receiving end, a value of the first bit according to a sampling result of the mth to (N-M + 1) th samples of the N samples includes: and the receiving end determines the value of the first bit according to the sampling result corresponding to the N/2 th NRZ signal in the N continuous NRZ signals.

6. The method of claim 1, wherein N is an even number greater than 2;

the receiving end sequentially sampling the N continuous NRZ signals for N times by the receiving end comprises the following steps: for each NRZ signal in the N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal by sampling the level of the junction of the NRZ signal and the NRZ signal before the NRZ signal;

the determining, by the receiving end, a value of the first bit according to sampling results of an mth sampling to an (N-M + 1) th sampling of the N samplings includes: and the receiving end determines the value of the first bit according to the sampling result corresponding to the (N + 2)/2 th NRZ signal in the N continuous NRZ signals.

7. The method of claim 1, wherein N is equal to 2;

the receiving end sequentially sampling the N continuous NRZ signals for N times by the receiving end comprises: for each NRZ signal in the N continuous NRZ signals, obtaining a sampling result corresponding to the NRZ signal by sampling the level of the junction of the NRZ signal and the NRZ signal which is the next NRZ signal of the NRZ signals;

the method further comprises the following steps: and the receiving end determines the value of the first bit according to the sampling result corresponding to the N/2 th NRZ signal in the N continuous NRZ signals.

8. The method of claim 1, wherein N is equal to 2;

the method further comprises the following steps: and the receiving end determines the value of the first bit according to the sampling result corresponding to the (N + 2)/2 th NRZ signal in the N continuous NRZ signals.

9. A signal processing method, comprising:

a receiving end receives N continuous NRZ signals from a transmitting end, wherein each NRZ signal in the N continuous NRZ signals is used for bearing a first bit, and N is an integer larger than 1;

the receiving end sequentially samples the N continuous NRZ signals for M times, wherein M is a positive integer smaller than N;

and the receiving end determines the value of the first bit according to the sampling result of the M times of sampling.

10. The method of claim 9, wherein the receiving end sequentially samples the N consecutive NRZ signals M times, comprising:

and the receiving end sequentially carries out M times of sampling on the N continuous NRZ signals according to a first rate, and the ratio of the first rate to the rate of receiving the N continuous NRZ signals by the receiving end is M: N.

11. The method of claim 9, wherein M is an odd number;

the receiving end determines the value of the first bit according to the sampling result of the M times of sampling, including:

and the receiving end determines the value of the first bit according to the sampling result of the (M + 1)/2 th sampling in the M times of sampling.

12. The method of claim 9, wherein M is an even number;

and the receiving end determines the value of the first bit according to the sampling result of the (M/2) th and/or (M + 2)/2 nd sampling in the M times of sampling.

13. The method according to any of claims 9-12, wherein the receiving end sequentially samples the N consecutive NRZ signals M times, comprising: the receiving end sequentially samples the K-th to (N-K + 1) -th NRZ signals in the N continuous NRZ signals for M times; k is an integer greater than 1 and less than N.

14. A signal processing apparatus, characterized by comprising:

a communication unit, configured to receive N consecutive NRZ signals from a transmitting end, where each of the N consecutive NRZ signals is used to carry a first bit, and N is an integer greater than 1;

a sampling unit for sequentially sampling the N continuous NRZ signals for N times;

and the determining unit is used for determining the value of the first bit according to the sampling results of the Mth sampling to the (N-M + 1) th sampling in the N times of sampling when N is larger than 2, wherein M is an integer larger than 1 and smaller than N.

15. The apparatus of claim 14, wherein the N is an odd number greater than 2, and the determining unit is further configured to determine the value of the first bit according to a sampling result of (N + 1)/2 samples of the N samples.

16. The apparatus of claim 14, wherein N is an even number greater than 2, and the determining unit is further configured to determine the value of the first bit according to a sampling result of an nth/2 and/or an (N + 2)/2 th sampling of the N samples.

17. The apparatus according to any of claims 14-16, wherein said sampling unit is further configured to sample said N consecutive NRZ signals N times in sequence at a first rate, said first rate being equal to a rate at which said receiving end receives said N consecutive NRZ signals.

18. The apparatus of claim 14, wherein N is an even number greater than 2;

the sampling unit is further configured to, for each NRZ signal of the N consecutive NRZ signals, obtain a sampling result corresponding to the NRZ signal by sampling a level at a junction of the NRZ signal and a subsequent NRZ signal of the NRZ signal;

the determining unit is further configured to determine, by the receiving end, a value of the first bit according to a sampling result corresponding to an N/2 th NRZ signal of the N consecutive NRZ signals.

19. The apparatus of claim 14, wherein N is an even number greater than 2;

the sampling unit is further configured to, for each NRZ signal of the N consecutive NRZ signals, obtain a sampling result corresponding to the NRZ signal by sampling a level at a junction of the NRZ signal and a previous NRZ signal of the NRZ signal;

the determining unit is further configured to, by the receiving end, determine a value of the first bit according to a sampling result corresponding to an (N + 2)/2 th NRZ signal of the N consecutive NRZ signals.

20. The apparatus of claim 14, wherein N is equal to 2;

the determining unit is further configured to determine a value of the first bit according to a sampling result corresponding to an N/2 th NRZ signal of the N consecutive NRZ signals.

21. The apparatus of claim 14, wherein N is equal to 2;

the determining unit is further configured to determine a value of the first bit according to a sampling result corresponding to an (N + 2)/2 nd NRZ signal of the N consecutive NRZ signals.

22. A signal processing apparatus, characterized by comprising:

a sampling unit, configured to sequentially sample the N consecutive NRZ signals M times, where M is a positive integer smaller than N;

and the determining unit is used for determining the value of the first bit according to the sampling result of the M times of sampling.

23. The apparatus of claim 22, wherein the sampling unit is further configured to sequentially sample the N consecutive NRZ signals M times at a first rate, and a ratio of the first rate to a rate at which the N consecutive NRZ signals are received by the receiving end is M: N.

24. The apparatus of claim 23, wherein M is an odd number; the determining unit is further configured to determine a value of the first bit according to a sampling result of (M + 1)/2 th sampling of the M times of sampling.

25. The apparatus of claim 23, wherein M is an even number; the determining unit is further configured to determine a value of the first bit according to a sampling result of an M/2 th and/or (M + 2)/2 nd sampling of the M samples.

26. The apparatus according to any of claims 22-25, wherein said sampling unit is further configured to sequentially sample the kth to (N-K + 1) th NRZ signals of said N consecutive NRZ signals by M times; k is an integer greater than 1 and less than N.

27. A chip system, comprising interface circuitry for implementing the method of any one of claims 1 to 8 or the method of any one of claims 9 to 13.