CN115249499A

CN115249499A - Attack address acquisition method and circuit thereof, hammering refreshing method and memory

Info

Publication number: CN115249499A
Application number: CN202110466937.8A
Authority: CN
Inventors: 杨宇
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-04-28
Filing date: 2021-04-28
Publication date: 2022-10-28

Abstract

The embodiment of the application relates to an attack address acquisition method and a circuit thereof, a hammering refreshing method and a memory, wherein the attack address acquisition method comprises the following steps: receiving an activation signal carrying activation row address information, and updating an activation count value corresponding to an activation row address according to a first preset sequence; when the activation count value meets a preset condition, generating a signal in the ratio; latching the activated row address according to the signal in the ratio; at least one of the latched plurality of active row addresses is randomly selected as an attack address. In the embodiment of the application, by randomly selecting one of the multiple alternative activation row addresses as the attack address, risks of malicious cracking and targeted attack on the acquisition method can be effectively reduced, and safety of the acquisition method is further improved.

Description

Attack address acquisition method and circuit thereof, hammering refreshing method and memory

Technical Field

The embodiment of the application relates to the technical field of semiconductor memories, in particular to an attack address acquisition method and circuit, a hammering refreshing method and a memory.

Background

With the continuous development of semiconductor Memory technology, the volume of Synchronous Dynamic Random Access Memory (SDRAM) is continuously reduced. However, as the memory volume shrinks, the distance between adjacent rows also narrows, resulting in an increased risk of row hammer problems. The line hammer refers to a phenomenon in which repeated accesses to an attack line for a certain period of time cause a fault to occur in a victim line (victim line) adjacent to the attack line (aggressive line). Row hammering can cause data changes in the victim row, resulting in a significant reduction in the reliability of the memory.

Disclosure of Invention

The embodiment of the application provides an attack address acquisition method and circuit, a hammering refreshing method and a memory, which can effectively reduce the risk of row hammering, thereby improving the data reliability of the memory.

An attack address acquisition method comprises the following steps:

receiving an activation signal carrying activation row address information, and updating an activation count value corresponding to an activation row address according to a first preset sequence;

when the activation count value meets a preset condition, generating a signal in a ratio;

latching the activated row address in response to the in-ratio signal;

at least one of the latched plurality of activated row addresses is randomly selected as the attack address.

In one embodiment, the generating a signal in a ratio when the activation count value satisfies a preset condition includes:

generating a signal in a ratio when the activation count value equals a signal in ratio count value;

the acquisition method further comprises the following steps: and in response to the in-ratio signal, updating a signal count value in the ratio according to a second preset order.

In one embodiment, the randomly selecting at least one of the latched plurality of activated row addresses as the attack address includes:

at least one of the latched plurality of activated row addresses is randomly selected as the attack address in response to a refresh signal.

In one embodiment, the method further comprises:

and resetting the activation count value corresponding to each attack address in response to the rate signal.

In one embodiment, the updating the activation count value corresponding to the activation row address according to a first preset order includes: updating the activation count value corresponding to the activation row address in an ascending order of numerical values;

the resetting the activation count value corresponding to each attack address includes: and clearing the activation count value corresponding to each attack address.

In one embodiment, the updating the activation count value corresponding to the activation row address according to a first preset order includes:

and updating the activation count value according to the current activation count value corresponding to the activation row address and a first preset count step length.

In one embodiment, said updating the signal count value in said ratio according to a second preset order in response to said in-ratio signal comprises:

and updating the signal count value in the ratio according to the current signal count value in the ratio and a second preset counting step length.

In one embodiment, the first preset counting step and the second preset counting step are equal.

A hammering refresh method, comprising the steps of the above method for acquiring attack address, further comprising:

determining the adjacent row address of the attack address as a hammering refreshing address;

and performing hammering refreshing on the data line corresponding to the hammering refreshing address.

In one embodiment, the determining that the row address adjacent to the attack address is a hammer refresh address includes:

and respectively acquiring a first adjacent row address and a second adjacent row address of the attack address, wherein the attack address is positioned between the first adjacent row address and the second adjacent row address.

An attack address acquisition circuit comprising:

the activation counter is used for receiving an activation signal carrying activation row address information and updating an activation count value corresponding to the activation row address according to a first preset sequence;

the counting comparison unit is connected with the activation counter and used for generating a signal in a comparison when the activation count value meets a preset condition;

the address latch is connected with the counting comparison unit and used for responding to the comparison signal and latching the activated row address;

and the random selection unit is connected with the address latch and is used for randomly selecting at least one of the latched multiple activated row addresses as the attack address.

In one embodiment, the method further comprises the following steps:

and the sequence counter is used for responding to the signal in the ratio and updating the signal count value in the ratio according to a second preset sequence. The sequence counter is connected with the counting comparison unit to output a signal count value in the ratio to the counting comparison unit and update the signal count value in the ratio in response to the signal in the ratio, thereby realizing flexible latching of the activated row address. A second preset sequence for updating numerical values is built in the sequence counter, and an initial value of the second preset sequence can be set according to needs, so that risks of malicious cracking and targeted attack of the acquisition method are reduced.

In one embodiment, the count comparing unit includes:

and the value comparator is respectively connected with the activation counter and the sequence counter and used for generating a signal in the ratio when the activation count value is equal to a signal count value in the ratio.

In one embodiment, the random selection unit includes:

a random number generator for generating a random number, the random number being less than or equal to the number of active row addresses stored by the address latch;

and the multiplexer is respectively connected with the random number generator and the address latch and is used for selecting the activated row address of the random number corresponding sequence as the attack address.

A memory comprises the attack address acquisition circuit.

The method for acquiring the attack address comprises the following steps: receiving an activation signal carrying activation row address information, and updating an activation count value corresponding to an activation row address according to a first preset sequence; when the activation count value meets a preset condition, generating a signal in a ratio; latching the activated row address in response to the in-ratio signal; at least one of the latched plurality of activated row addresses is randomly selected as the attack address. In the embodiment of the application, the occurrence probability of the row hammering problem of each data row can be accurately evaluated by acquiring the activation count values of each row in the storage array, so that the storage can conveniently and respectively execute corresponding row hammering avoidance measures according to different occurrence probabilities, and the risk of malicious cracking and targeted attack of the acquisition method can be effectively reduced by randomly selecting one of a plurality of alternative activation row addresses as an attack address, so that the safety of the acquisition method is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is one of the structural block diagrams of an attack address acquisition circuit according to an embodiment;

FIG. 2 is a flowchart of a method for acquiring an attack address according to an embodiment;

FIG. 3 is a second flowchart of a method for acquiring an attack address according to an embodiment;

FIG. 4 is a third flowchart of a method for acquiring an attack address according to an embodiment;

FIG. 5 is a fourth flowchart of a method for obtaining an attack address according to an embodiment;

FIG. 6 is a fifth flowchart of a method for acquiring an attack address according to an embodiment;

FIG. 7 is a flow diagram of a hammer refresh method according to an embodiment;

FIG. 8 is a schematic diagram of an aggressor row and an adjacent row of an embodiment;

FIG. 9 is a second block diagram illustrating an exemplary circuit for address acquisition;

fig. 10 is a third block diagram of an attack address obtaining circuit according to an embodiment.

Description of the element reference numerals:

activating a counter: 100, respectively; a counting and comparing unit: 200; a numerical comparator: 210; an address latch: 300, respectively; a random selection unit: 400; a random number generator: 410; a multiplexer: 420; sequence counter: 500.

Detailed Description

To facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application belong. The terminology used herein in the description of the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The embodiment of the present application provides an attack address acquisition method, and the acquisition method in the embodiment of the present application is described by taking an acquisition circuit applied to an attack address shown in fig. 1 as an example. Specifically, the circuit for acquiring the attack address and the memory array in the embodiment of the present application are both disposed inside the memory and connected to each other. The circuit for acquiring the attack address is used for determining a data row (namely the attack address) which is frequently subjected to read-write operation in the storage array, so that corresponding counter measures are conveniently implemented, and the problem of data abnormity or loss caused by row hammering is avoided. The corresponding countermeasure includes but is not limited to refreshing the stored data of the adjacent row to the attack address, limiting the data read-write operation to the attack address, and the like.

The memory is also provided with a command decoder, the command decoder acquires command signals from the controller and decodes the command signals to acquire various internal command signals which can be executed by the internal circuit, such as an active signal ACT, a precharge signal Pre, a read-write signal R/W, a refresh signal REF and the like, and the acquisition circuit of the attack address receives the active signal ACT and the refresh signal REF and responds to the signals to execute the steps in the acquisition method of the attack address.

The active signal ACT is activated when the controller instructs the memory to perform row access, and when the active signal ACT is activated, a data row in the memory array, which needs to perform read and write operations, is opened. The read-write signal R/W is activated after the data line which needs to execute the read-write operation is opened, and when the read-write signal R/W is activated, data can be read and written on the corresponding data line. The precharge signal Pre is activated after completing the read/write operation on the data row, and when the precharge signal Pre is activated, the data row in the memory array that needs to perform the read/write operation is closed.

The refresh signal REF is activated when an auto-refresh command needs to be performed, and may be repeatedly activated at a certain period according to internal timing. It is understood that even if there is no row hammer problem, the charges stored in the storage capacitor of the memory cell are continuously lost over time, and therefore, the memory needs to perform a refresh operation at a certain period, so as to ensure the accuracy of the data stored in the memory cell. Specifically, when a refresh operation is performed, the current charge amount in the memory cell is acquired, whether the data stored in the memory cell is 1 or 0 is determined according to the current charge amount, and finally, the memory capacitor is charged or discharged again according to the determination result, so that the charge amount stored in the memory capacitor corresponds to the data to be stored.

Referring to fig. 1, an acquisition circuit of an attack address according to an embodiment of the present application includes an activation counter 100, a count comparison unit 200, an address latch 300, and a random selection unit 400, where each step of an acquisition method according to an embodiment of the present application is executed by each element in the acquisition circuit in a one-to-one correspondence manner, fig. 2 is one of flowcharts of an acquisition method of an attack address according to an embodiment, and referring to fig. 1 and fig. 2 in combination, the acquisition method according to the embodiment includes steps S100 to S400.

S100: receiving an activation signal carrying activation row address information, and updating an activation count value corresponding to the activation row address according to a first preset sequence.

The active row address refers to an active row address carried by an active signal received when the active counter 100 is updated, in other words, the active signal is used to activate a data row corresponding to the active row address. Specifically, the activation counter 100 has a first predetermined sequence of numerical updates embedded therein, which may be, for example, X1, X2, X3, X4 \8230. If the activation count value of the activation counter 100 is X2 before the activation signal of the current cycle is received, the activation count value of the activation counter 100 is updated to X3 after the activation signal of the current cycle is received. Alternatively, the first predetermined order may be an increasing sequence with a fixed law of variation, such as 11, 12, 13, 14 \8230. The first predetermined sequence may also be a decreasing sequence with a constant law of variation, such as 18, 16, 14, 12 \8230. The first predetermined sequence may also be a string of sequences without a fixed variation rule, such as 11, 13, 14, 15, 17, 8230. It should be clear that, the present embodiment does not specifically limit the setting manner of the first preset sequence, and only needs that the first preset sequence is a finite-length sequence, and the activation counter 100 can update the activation count value once according to the first preset sequence when receiving the activation signal each time, that is, other counters with regular changes except the random counter can be regarded as the activation counter 100 of the present embodiment.

S200: and when the activation count value meets a preset condition, generating a signal in the ratio.

Wherein, the comparison signal is an enable signal for selecting the activated row address through comparison. Specifically, when the activation count value satisfies a certain preset condition, the count comparing unit 200 may consider that the data row corresponding to the activation counter 100 is frequently activated, and there is a risk of row hammering, that is, a comparison signal may be sent to instruct the address latch 300 to latch the address of the data row corresponding to the activation counter 100 (i.e., the activation row address). For example, the count-up comparison unit 200 may be configured with a count threshold in advance, and when the activation count value reaches the count threshold, a corresponding signal in the comparison may be generated. It can be understood that the type of the count comparison unit 200 is not specifically limited in this embodiment, and the count comparison unit 200 may also be a comparator with more complex data processing or logic determination rules, rather than being used for comparing magnitude relations of numerical values, so as to improve the complexity of the acquisition method and the acquisition circuit of the attack address, thereby reducing the risk of malicious cracking and improving the reliability of the memory.

S300: latching the activated row address in response to the in-ratio signal.

Specifically, the address latch 300 latches the activated row address in response to the in-ratio signal, and the latched activated row address may be an alternative address to the attack address. Wherein the address latch 300 may latch a plurality of activated row addresses. Optionally, the address latch 300 may output all latched activated row addresses as attack addresses at a required time, or may output only part of latched activated row addresses as attack addresses, and specifically, the number of attack addresses may be determined according to parameters such as a refresh rate.

S400: at least one of the latched plurality of activated row addresses is randomly selected as the attack address.

The random selection unit 400 may generate at least one random number at a preset time interval, and the range of the generated random number corresponds to the number of addresses that the address latch 300 can latch, and the preset time interval may be determined by an externally input clock signal. For example, if the address latch 300 can latch 10 active row addresses, the random number generated by the random selection unit 400 may be any integer from 1 to 10, and the random selection unit 400 further selects and outputs one active row address in the corresponding order as an attack address according to the generated random number.

In this embodiment, the method for acquiring an attack address includes: receiving an activation signal carrying activation row address information, and updating an activation count value corresponding to an activation row address according to a first preset sequence; when the activation count value meets a preset condition, generating a signal in a ratio; latching the active row address in response to the in-ratio signal; at least one of the latched plurality of activated row addresses is randomly selected as the attack address. In the embodiment of the application, the occurrence probability of the row hammering problem of each data row can be accurately evaluated by acquiring the activation count values of each row in the storage array, so that the storage can conveniently and respectively execute corresponding row hammering avoidance measures according to different occurrence probabilities, and the risk of malicious cracking and targeted attack of the acquisition method can be effectively reduced by randomly selecting one of a plurality of alternative activation row addresses as an attack address, so that the safety of the acquisition method is further improved.

In one embodiment, a plurality of activation counters 100 are disposed in the memory, and each activation counter 100 corresponds to at least one data row to count the number of activations of the corresponding data row. It will be appreciated that a large number of memory cells are included in the memory, and accordingly, a large number of data lines must also exist, which takes a lot of time and space if the number of activations per data line is kept to count. Therefore, the activation counter 100 may be configured with a corresponding activation count list, and only the activation count value of the data row with a higher activated number is saved in the activation count list, that is, the data row stored in the activation count list is the data row with a higher risk of row hammer, so that the amount of data required to be stored may be reduced.

Further, the activation signal may also be sampled at a preset frequency. For example, the circuit for acquiring an attack address may sample one of the n activation signals and acquire the activation row address information carried by the activation signal for statistics every time the activation signals are received, but not perform statistics on the remaining n-1 activation signals. It can be understood that if a data line is frequently activated, the activation times of the data line are much larger than those of other data lines which are normally read and written when sampling is performed at fixed intervals. Therefore, this is also a more reliable counting manner for activating the counter 100, and the counting number of the activated counter 100 can be greatly reduced, so as to effectively reduce the counting pressure of the activated counter 100, reduce the time required by the method for acquiring the attack address, and further improve the efficiency of the method for acquiring the attack address.

Fig. 3 is a second flowchart of the method for acquiring an attack address according to the embodiment, and referring to fig. 3, in the embodiment, the method for acquiring an attack address includes steps S100 to S400.

S210: generating a signal-in-ratio when the activation count value equals a signal-in-ratio count value.

S300: latching the activated row address in response to the in-ratio signal.

S510: and in response to the in-ratio signal, updating a signal count value in the ratio according to a second preset order.

Steps S100, S300 to S400 are the same as those in the embodiment of fig. 2, so that reference may be made to the foregoing embodiment, which is not repeated herein. Specifically, the second predetermined order may be, for example, Y1, Y2, Y3, Y4 \8230, and if the signal count value in the ratio is Y2 before the signal in the ratio is received, the signal count value in the ratio is updated to Y3 after the signal in the ratio is received. Similarly to the first preset order, the second preset order may be an increasing sequence with a constant change rule, a decreasing sequence with a constant change rule, or a string sequence without a constant change rule. It should be clear that the first preset order may be the same as the second preset order, or may be different from the first preset order, and this embodiment is not particularly limited. In the present embodiment, the sequence counter updates the signal count value in the ratio in response to the signal in the ratio. By adopting the signal count value in the ratio based on the continuous update of the signal in the ratio, the risks of malicious cracking and targeted attack of the acquisition method can be effectively reduced, and the safety of the acquisition method is improved.

In one embodiment, the randomly selecting at least one of the latched activated row addresses as the attack address includes: at least one of the latched plurality of activated row addresses is randomly selected as the attack address in response to the refresh signal. Specifically, as described above, the refresh signal output by the controller is used to control the memory to perform auto-refresh, which is a refresh method adopted to avoid the charge loss problem due to time. In this embodiment, the address latch 300 outputs the attack address in response to the refresh signal, that is, the attack address can be simultaneously and correspondingly operated in the auto-refresh stage of the memory, so as to improve the processing efficiency of the corresponding operation and avoid affecting the working performance of the memory.

Further, the frequency of receiving the refresh signal by the random selector 400 is lower than the frequency of receiving the activation signal by the activation counter 100, but there is a positive correlation between the receiving frequencies of the two signals. It will be appreciated that the frequency with which data lines are activated in response to an activation signal is generally directly related to the read and write speed of the memory, and that the risk of line hammering is increased precisely because the attacked data lines are read and written continuously. Therefore, the frequency of the refresh signal sent by the controller is set according to the activated frequency of the data rows, so that the memory array can be better protected.

Specifically, description will be made taking as an example that the operation correspondingly performed based on the attack address is a hammer refresh operation. First, an auto-refresh operation may require refresh of multiple rows of data that need to be refreshed in response to a single refresh signal, the auto-refresh operation requiring an occupied row refresh cycle time (tRFC), and there is an average refresh interval of refresh interval times (tREFI) between auto-refresh operations. While the memory performs auto-refresh of a plurality of rows of data in response to a refresh command, it will be appreciated that in the present embodiment, since the number of attack addresses is typically less than the number of addresses required to perform the auto-refresh, the time required for a hammer refresh is also typically shorter than the row refresh cycle time tRFC, i.e., the row refresh cycle time tRFC is sufficient to complete the hammer refresh. Therefore, the hammering refreshing operation of the embodiment does not need to occupy the data reading and writing time of the memory unit corresponding to the adjacent row of the attack address, and can effectively strengthen the data security of the memory, i.e. a method with higher reliability and efficiency is provided.

The number of attack addresses to be output may be one, or may be plural, for example, 2 or 4. It will be appreciated that if the density of the wiring in the memory is high, meaning that there is a greater risk of row hammering occurring, then a greater number of rows of data may be hammered and refreshed at a time, and if the density of the wiring in the memory is low, then a lesser number of rows of data may be hammered and refreshed at a time. Therefore, the specific number may be determined according to the wiring density in the memory, and the present embodiment is not particularly limited.

Fig. 4 is a third flowchart of an attack address obtaining method according to an embodiment, and referring to fig. 4, in this embodiment, the attack address obtaining method includes steps S100 to S410.

S210: generating a ratio-in signal when the activation count value equals a ratio-in signal count value.

S300: latching the activated row address in response to the in-ratio signal.

S510: and responding to the signal in the ratio, and updating a signal counting value in the ratio according to a second preset order.

S520: and resetting the activation count value corresponding to each attack address in response to the rate signal.

S410: at least one of the latched plurality of activated row addresses is randomly selected as the attack address in response to a refresh signal.

In this embodiment, the activated row address is latched in step S300, the signal count value in the ratio is updated according to a second preset sequence in step S510, and the activation count values corresponding to the attack addresses are reset in step S520 in response to the execution of the same refresh signal, and by setting the execution in response to the same signal, the synchronization of the above three steps can be effectively improved, and the number of signals required by the method for acquiring the attack addresses can be reduced, thereby simplifying the logic of the acquisition method.

It is understood that the execution bodies of the above three steps are different, specifically, the address latch 300 latches the activated row address, the sequence counter updates the signal count value in the ratio according to a second preset order, and the activation counter 100 resets the activation count value corresponding to each of the attack addresses. Therefore, the embodiment of the present application does not specifically limit the execution sequence of the three steps, that is, the signal in the ratio may first instruct to execute one of the steps, and after the step is finished, instruct to execute another step, and the embodiment does not need to limit the execution sequence between the shanghai steps. Illustratively, the execution order of the three steps can be set by adding a delay unit in the circuit. It is understood that the above three steps can be executed simultaneously to improve the data processing and resetting efficiency of the acquisition method of the attack circuit.

Fig. 5 is a fourth flowchart of an attack address obtaining method according to an embodiment, and referring to fig. 5, in the present embodiment, the attack address obtaining method includes steps S110 to S410.

S110: receiving an activation signal carrying activation row address information, and updating an activation count value corresponding to the activation row address in an ascending order of numerical values.

S300: latching the activated row address in response to the in-ratio signal.

S521: and responding to the ratio signal, and clearing the activation count value corresponding to each attack address.

In this embodiment, the updating the activation count value corresponding to the activation row address according to the first preset order in step S100 specifically includes updating the activation count value corresponding to the activation row address in an ascending order of numerical values. In step S520, resetting the activation count value corresponding to each attack address specifically includes clearing the activation count value corresponding to each attack address.

Specifically, the activation count value is updated in an incremental manner, for example, in a manner of 0,1,2,3 \8230, and accordingly, the activation count value is updated in a zero clearing manner when the activation counter 100 is reset, and the clear correspondence relationship is provided between the activation count value and the zero clearing manner, so that the difficulty in data analysis of the activation counter 100 can be greatly simplified, and the data processing efficiency of the acquisition method of the embodiment is improved. In other embodiments, if the activation count value is updated in a decreasing manner, for example, in the manner of 10,9,8,7 \8230, the activation count value may be updated in a manner of resetting to 10 when the activation counter 100 is reset, so as to achieve the above-mentioned effect of improving data processing efficiency.

Fig. 6 is a fifth flowchart of an attack address obtaining method according to an embodiment, and referring to fig. 6, in the embodiment, the attack address obtaining method includes steps S120 to S410.

S120: receiving an activation signal carrying activation row address information, and updating the activation count value according to a current activation count value corresponding to the activation row address and a first preset count step length.

S300: latching the activated row address in response to the in-ratio signal.

S511: and responding to the signal in the ratio, and updating the signal count value in the ratio according to the current signal count value in the ratio and a second preset count step length.

S521: and responding to the ratio middle signal, and clearing the activation count value corresponding to each attack address.

S410: at least one of the latched plurality of active row addresses is randomly selected as the attack address in response to a refresh signal.

In this embodiment, the updating the activation count value corresponding to the activation row address according to the first preset order in step S100 specifically includes updating the activation count value according to the current activation count value corresponding to the activation row address and the first preset count step. The step S510 of updating the signal count value in the ratio according to the second preset order specifically includes updating the signal count value in the ratio according to the current signal count value in the ratio and the second preset count step.

When both the first preset counting step and the second preset counting step are greater than 0, that is, the updating is performed in the order of increasing numerical values in step S210 in the foregoing embodiment, and when both the second preset counting step and the first preset counting step are less than 0, the updating is performed in the order of decreasing numerical values. Illustratively, the second preset count step and the first preset count step may both be 1, the update order of the sequence counter may be, for example, 1,2,3,4 \8230, the update order of the activation counter 100 may be, for example, 0,1,2,3,4 \8230. In this embodiment, the occurrence probability of the row hammering problem of each data row can be accurately evaluated, and the risk of malicious cracking and targeted attack of the acquisition method can be effectively reduced, so that the security of the acquisition method is further improved.

Further, the second preset counting step length and the first preset counting step length may be equal, and by adopting the same manner of the preset counting step lengths, the internal logics of the sequence counter and the activation counter 100 may be greatly simplified, thereby improving the technical accuracy of the sequence counter and the activation counter 100, and moreover, since the sequence counter is still a counter whose number of changes with the signal in the ratio, the method for acquiring the attack address of the embodiment may still avoid the problem of malicious cracking, thereby ensuring the reliability of the acquisition method.

Fig. 7 is a flowchart of a hammer refresh method according to an embodiment, and referring to fig. 7, in the embodiment, the hammer refresh method includes steps S100 to S700.

S300: latching the activated row address in response to the in-ratio signal.

S600: and determining the adjacent row address of the attack address as a hammering refreshing address.

S700: and performing hammering refreshing on the data line corresponding to the hammering refreshing address.

Steps S100 to S400 are steps of the method for acquiring the attack address. In this embodiment, by refreshing the data row corresponding to the hammered refresh address, the influence of the row hammering on the data stored in the adjacent row address can be avoided, so as to improve the reliability of the data stored in the memory. It is understood that steps S100 to S400 of the present embodiment may be further replaced by the embodiment of fig. 3 to 6, so as to implement a more reliable hammer refresh method.

In one embodiment, the determining that the row address adjacent to the attack address is a hammer refresh address includes: and respectively acquiring a first adjacent row address and a second adjacent row address of the attack address, wherein the attack address is positioned between the first adjacent row address and the second adjacent row address. Specifically, fig. 8 is a schematic diagram of an attack row and an adjacent row in an embodiment, and referring to fig. 8, a plurality of attack rows may exist in a storage array, and each attack row may be located in a different storage block as shown in fig. 8, and in other embodiments, one storage block may also include a plurality of attack rows.

Further, the aggressor row may be located in the middle of the memory block, i.e., as shown in the first memory block in fig. 8, the aggressor row is located in the same memory block as its corresponding first and second adjacent rows. The aggressor row may also be located at the boundary of the memory block, i.e., the aggressor row is located in a different memory block from its corresponding first and second adjacent rows, as shown in the second memory block in fig. 8. It is understood that the hammer refresh method of the present embodiment can be applied to the attack rows in the above-mentioned various positions, and thus has higher reliability.

Still further, the determining that the row address adjacent to the attack address is the hammer refresh address includes: respectively obtaining a first adjacent row address and a second adjacent row address of the attack address, wherein the attack address is positioned between the first adjacent row address and the second adjacent row address. It is understood that, in some embodiments, only one adjacent row of the aggressor row may be hammered and refreshed, and multiple adjacent data rows on a single side of the aggressor row may also be hammered and refreshed, which may be determined according to a degree that different adjacent rows are affected by a row hammering effect, for example, according to a distance relationship between the adjacent rows and the hammered row, because a case that an adjacent row receives row hammering more seriously than a farther adjacent row, thereby improving accuracy and efficiency of the hammered refresh.

It should be understood that although the steps in the flowcharts of fig. 2 through 7 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence in the order indicated by the arrows. The steps are not performed in a strict order unless explicitly stated herein, and may be performed in other orders. Moreover, at least some of the steps in fig. 2-7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

With continued reference to fig. 1, an embodiment of the present application provides an attack address obtaining circuit, which includes an activation counter 100, a count comparison unit 200, an address latch 300, and a random selection unit 400.

The activation counter 100 is configured to receive an activation signal carrying activation row address information, and update an activation count value corresponding to an activation row address according to a first preset order. The count comparing unit 200 is connected to the activation counter 100, and is configured to generate a signal in a ratio when the activation count value satisfies a preset condition. An address latch 300 is connected to the count comparison unit 200 for latching the activated row address in response to the compare signal. A random selection unit 400 is connected to the address latch 300 for randomly selecting at least one of the latched plurality of active row addresses as the attack address. In the embodiment, the activation counter 100 is used for acquiring the activation count value of each row in the storage array, so that the occurrence probability of the row hammering problem of each data row can be accurately evaluated, the memory can conveniently and respectively execute corresponding row hammering avoidance measures according to different occurrence probabilities, and moreover, one of a plurality of alternative activation row addresses is randomly selected as an attack address through the random selection unit 400, so that the risks of malicious cracking and targeted attack of the acquisition method can be effectively reduced, and the safety of the acquisition method is further improved.

Fig. 9 is a second block diagram of the configuration of the circuit for acquiring an attack address according to an embodiment, and referring to fig. 9, in this embodiment, the circuit for acquiring an attack address further includes a sequence counter 500, the sequence counter 500 is connected to the value comparator 210, and the sequence counter 500 is configured to update a signal count value in the ratio according to a second preset order in response to the signal in the ratio. Specifically, the second predetermined order may be Y1, Y2, Y3, Y4 \8230, for example, if the signal count value in the ratio is Y2 before the signal in the ratio is received, the signal count value in the ratio is updated to Y3 after the signal in the ratio is received. Similar to the first predetermined order, the second predetermined order may be an increasing sequence with a constant variation rule, a decreasing sequence with a constant variation rule, or a series of sequences without a constant variation rule. It should be clear that the first preset order may be the same as the second preset order, or may be different from the first preset order, and this embodiment is not particularly limited. In this embodiment, the sequence counter 500 continuously updates the signal count value in the ratio based on the signal in the ratio, so that the risks of malicious cracking and targeted attack on the acquisition circuit can be effectively reduced, and the security of the acquisition circuit is improved.

Further, the count comparing unit 200 includes a value comparator 210, and the value comparator 210 is respectively connected to the activation counter 100 and the sequence counter 500, and is configured to determine that, when the activation count value is equal to a signal count value in a ratio, a data row corresponding to a current activation row address is at risk of row hammering, and generate a signal in the ratio accordingly. The in-ratio signal is used to instruct the address latch 300 to latch the activated row address, instruct the sequence counter 500 to update the in-ratio signal count value, and instruct the activation counter 100 to reset, so that a relatively efficient attack address acquisition circuit is implemented.

Fig. 10 is a third block diagram of a circuit for acquiring an attack address according to an embodiment, and referring to fig. 10, in this embodiment, the random number selection unit 400 includes a random number generator 410 and a multiplexer 420. The random number generator 410 is used to generate a random number that is less than or equal to the number of active row addresses stored by the address latch 300. The multiplexer 420 is respectively connected to the random number generator 410 and the address latch 300, and is configured to select the activated row address in the corresponding order of the random numbers as the attack address.

Illustratively, the random number generator 410 may include a plurality of D flip-flops and a logic gate cascaded in order to generate a multi-bit random number. Where the phase cascade means that the output terminal of the previous D flip-flop is connected to the input terminal of the next D flip-flop, in this example, the random number generator 410 includes 4D flip-flops and an exclusive or gate. It is understood that in other examples, the random number generator 410 may include a greater number of D flip-flops, and the number of D flip-flops corresponds to the number of activated row addresses that can be latched by the address latch 300, and in addition, the application does not specifically limit the types of logic gates and the number of input terminals, and the structure of the random number generator 410 in fig. 10 is only used for illustration.

The embodiment of the application further provides a hammering refreshing circuit, and the hammering refreshing circuit comprises the circuit for acquiring the attack address in the embodiment, an addition and subtraction arithmetic unit and a refreshing module.

The add-subtract operator is connected to the address latch 300 in the circuit for obtaining the attack address, and is configured to add and subtract the attack address output by the address latch 300 to obtain an adjacent row address as the hammering refresh address. For example, if the add-subtract operator performs operations of adding one and subtracting one to the attack address respectively, two hammering refresh addresses can be obtained; if the add-subtract operator respectively performs the operations of adding one, adding two, subtracting one and subtracting two on the attack address, then four hammering refreshing addresses can be obtained. It is understood that the specific operation content of the add-subtract operator may be determined according to the spacing between adjacent word lines, and the number of hammered refresh addresses obtained by the operation is inversely related to the spacing between adjacent word lines.

The refreshing module is connected with the add-subtract arithmetic unit and respectively connected with the data reading and writing circuits of the plurality of data rows, and is used for acquiring the stored data in the data row corresponding to the hammering refreshing address through the data reading and writing circuits, generating refreshing data according to the stored data, and rewriting the refreshing data into the data row corresponding to the hammering refreshing address through the data reading and writing circuits, so that hammering refreshing is realized. Optionally, the hammered refresh operation may share at least a portion of the refresh modules with the auto-refresh operation, thereby reducing the number and volume of refresh modules in the memory.

The embodiment of the application also provides a memory, which comprises the attack address acquisition circuit and the attack address acquisition circuit, and the embodiment provides a memory with higher data reliability.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.

Claims

1. A method for acquiring an attack address is characterized by comprising the following steps:

latching the active row address in response to the in-ratio signal;

2. The method according to claim 1, wherein the generating a signal in a ratio when the activation count value satisfies a preset condition includes:

3. The method according to claim 2, wherein the randomly selecting at least one of the latched plurality of active row addresses as the attack address includes:

4. The acquisition method according to claim 2, characterized in that the method further comprises:

5. The method according to claim 4, wherein the updating the activation count value corresponding to the activation row address according to the first preset order includes: updating the activation count value corresponding to the activation row address in an ascending order of numerical values;

resetting the activation count value corresponding to each attack address includes: and clearing the activation count value corresponding to each attack address.

6. The method according to claim 2, wherein the updating the activation count value corresponding to the activation row address according to the first preset order includes:

7. The method of claim 6, wherein said updating the signal count value in the ratio according to a second predetermined order in response to the signal in the ratio comprises:

8. The acquisition method according to claim 7, characterized in that said first preset counting step and said second preset counting step are equal.

9. A new hammering brushing method, comprising the step of the method for acquiring an attack address according to any one of claims 1 to 8, further comprising:

and performing hammering refreshing on the data row corresponding to the hammering refreshing address.

10. The hammer refresh method of claim 9, wherein the determining that the adjacent row address of the attack address is a hammer refresh address comprises:

11. An attack address acquisition circuit, comprising:

12. The acquisition circuit of claim 11, further comprising:

and the sequence counter is used for responding to the signal in the ratio and updating the signal count value in the ratio according to a second preset sequence.

13. The acquisition circuit of claim 12, wherein the count comparison unit comprises:

and the numerical value comparator is respectively connected with the activation counter and the sequence counter and is used for generating a signal in a ratio when the activation count value is equal to a signal count value in the ratio.

14. The acquisition circuit according to claim 11, wherein the random selection unit comprises:

and the multiplexer is respectively connected with the random number generator and the address latch and is used for selecting the activation row addresses in the sequence corresponding to the random numbers as the attack addresses.

15. A memory comprising an attack address acquisition circuit according to any one of claims 11 to 14.