CN115248741A - A Serdes PHY multiplexing method, apparatus, equipment and storage medium - Google Patents

Abstract

The present application discloses a Serdes PHY multiplexing method, device, equipment and storage medium, which relate to the technical field of integrated circuits, including: separately counting the number of target controllers required in various application scenarios, and obtaining corresponding multi number of controllers; determine the maximum value from the number of controllers, and determine multiple target Serdes PHYs with the same number as the maximum number; set a variety of different working modes respectively, so as to The target controller and the multiple target Serdes PHYs in the different application scenarios are matched in the different working modes. In this application, by setting a variety of different working modes, and matching different controllers and Serdes PHYs in different modes, the Serdes PHYs can be flexibly multiplexed, thereby reducing the number of Serdes PHYs and greatly reducing the chip area. System integration is improved and costs are reduced.

Description

A Serdes PHY multiplexing method, device, equipment and storage medium

technical field

The present application relates to the technical field of integrated circuits, in particular to a Serdes PHY multiplexing method, device, equipment and storage medium.

Background technique

In the current test scheme, the high-speed serial interface (HSSI, High-Speed Serial Interface) is composed of a controller corresponding to a Serdes PHY (Serializer/Deserializer Physical Layer, serializer/deserializer port physical layer), If the system integrates multiple high-speed serial interfaces at the same time, then multiple controllers correspond to multiple Serdes PHYs. For example, when there are PCIE0 (Peripheral Component InterconnectExpress, high-speed serial computer expansion bus standard), PCIE1, SATA (Serial Advanced Technology Attachment, serial advanced technology attachment) and EMAC (Ethernet Media Access Control, Ethernet Media Access Controller) four For the controller, it will correspond to four Serdes PHYs. For example, the PCIE0 controller corresponds to Serdes PHY0, the PCIE1 controller corresponds to Serdes PHY1, the SATA controller corresponds to Serdes PHY2, and the EMAC controller corresponds to Serdes PHY3.

However, in actual application scenarios, different applications usually require multiple controllers of different types or the same type. At this time, if the above-mentioned test scheme in which one controller corresponds to one Serdes PHY is used, a large number of Serdes PHYs are required. As a result, the chip area is large and the cost is high.

Therefore, how to implement the multiplexing of multiple Serdes PHYs in different application scenarios is a problem that those skilled in the art need to solve at present.

SUMMARY OF THE INVENTION

In view of this, the purpose of this application is to provide a Serdes PHY multiplexing method, device, equipment and storage medium, which can flexibly multiplex Serdes PHYs, thereby reducing the number of Serdes PHYs, greatly reducing the area of the chip, and improving system integration , and reduce costs. The specific plan is as follows:

In the first aspect, the application discloses a Serdes PHY multiplexing method, including:

Count the number of target controllers required in various application scenarios to obtain the corresponding number of multiple controllers;

determining a maximum value from a plurality of said controller quantities, and determining a plurality of target Serdes PHYs equal to said maximum quantity;

Multiple different working modes are respectively set, so as to match the target controller and multiple target Serdes PHYs in the different application scenarios under the multiple different working modes.

Optionally, after counting the number of target controllers required in multiple different application scenarios, and obtaining the corresponding number of multiple controllers, the method further includes:

The types of all the target controllers required in the different application scenarios are counted to obtain the first number of target controller types.

Optionally, multiple different working modes are set respectively, including:

A variety of different working modes are set by rationally configuring the working mode registers by the central processing unit.

Optionally, the matching the target controller and multiple target Serdes PHYs in the different application scenarios in multiple different working modes includes:

Determining a plurality of target selectors with the same number as the maximum value through the operating mode register;

Match each of the target selectors with the first number of controllers with the same type as the target controllers, and match the matched target selectors with multiple target Serdes PHYs respectively Match one by one.

Optionally, the Serdes PHY multiplexing method also includes:

When a new application scenario is detected, the number and type of controllers required in the new application scenario are counted to obtain the number of new application scenario controllers and the second number of new application scenario controller types;

Judging whether the controller types of the new application scenario belong to the types of the target controller types;

If the new application scenario controller types all belong to the type of the target controller type, then determine whether the number of the new application scenario controllers exceeds the number of multiple target Serdes PHYs;

If the number of controllers in the new application scenario does not exceed the number of multiple target Serdes PHYs, using the target selector to match the controllers in the new application scenario with multiple target Serdes PHYs.

Optionally, using the target selector to match the controller in the new application scenario with multiple target Serdes PHYs includes:

Using the target selector to match multiple controllers with the same type as the second quantity and the new application scenario controller one by one to a plurality of target Serdes PHYs.

Optionally, the number of target controllers required in a variety of different application scenarios is counted respectively to obtain the corresponding number of multiple controllers, including

Count the number of PCIE controllers, SATA controllers, and EMAC controllers required in various application scenarios, and obtain the corresponding number of PCIE controllers, SATA controllers, and EMAC controllers.

In a second aspect, the application discloses a Serdes PHY multiplexing device, including:

The number statistics module is used to count the number of target controllers required in various application scenarios respectively, and obtain the corresponding number of multiple controllers;

A determining module, configured to determine a maximum value from a plurality of the controllers, and determine a plurality of target Serdes PHYs having the same number as the maximum value;

The working mode setting module is configured to set multiple different working modes, so as to match the target controller and multiple target Serdes PHYs in the different application scenarios under the multiple different working modes.

In a third aspect, the present application discloses an electronic device, including a processor and a memory; wherein, the aforementioned Serdes PHY multiplexing method is implemented when the processor executes the computer program stored in the memory.

In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned Serdes PHY multiplexing method is implemented.

It can be seen that the present application first counts the number of target controllers required in various application scenarios to obtain the corresponding number of controllers, and then determines the maximum value from the number of controllers, and determines Output a plurality of target Serdes PHYs with the same maximum number as the maximum value, and then set a plurality of different working modes, so as to match the target controller and the target controller in the different application scenarios in a plurality of different working modes A plurality of said target Serdes PHYs. In this application, by setting a variety of different working modes and matching different controllers and Serdes PHYs in different modes, the Serdes PHY can be flexibly multiplexed, thereby reducing the number of Serdes PHYs and greatly reducing the area of the chip. The system integration degree is improved and the cost is reduced.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is a flow chart of a Serdes PHY multiplexing method disclosed in the present application;

FIG. 2 is a schematic diagram of a specific Serdes PHY application scenario disclosed in the present application;

Fig. 3 is a block diagram of a traditional Serdes PHY usage method disclosed in the present application;

Fig. 4 is a block diagram of a specific Serdes PHY multiplexing method disclosed in the present application;

Fig. 5 is a schematic structural diagram of a Serdes PHY multiplexing device disclosed in the present application;

FIG. 6 is a structural diagram of an electronic device disclosed in the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The embodiment of the present application discloses a Serdes PHY multiplexing method, as shown in Figure 1, the method includes:

Step S11: Counting the number of target controllers required in various application scenarios respectively to obtain corresponding numbers of multiple controllers.

In this embodiment, first, it is necessary to make statistics on the number of controllers required in various application scenarios to obtain corresponding numbers of multiple controllers. Wherein, the target controller includes but is not limited to a PCIE controller, a SATA controller, and an EMAC controller.

In a specific implementation manner, the counting of the number of target controllers required in various different application scenarios to obtain the corresponding number of multiple controllers may specifically include: Count the number of required PCIE controllers, SATA controllers, and EMAC controllers to obtain the corresponding number of PCIE controllers, SATA controllers, and EMAC controllers. For example, referring to Fig. 2, Fig. 2 shows 5 specific application scenarios of the Serdes PHY chip, and statistics are obtained on the types and quantities of controllers used in the 5 application scenarios in Fig. 2: Scenario 1 , requires 4 PCIE controllers + 4 PHYs; scenario 2, requires 4 SATA controllers + 4 PHYs; scenario 3, requires 4 EMAC controllers + 4 PHYs; scenario 4, requires 2 PCIE controllers and 2 SATA controllers + 4 PHYs; Scenario 5 requires 2 PCIE controllers, 1 SATA controller and 1 EMAC controller + 4 PHYs.

In this embodiment, the counting of the number of target controllers required in a variety of different application scenarios, after obtaining the corresponding number of multiple controllers, may also include: counting the number of target controllers in a variety of different application scenarios The types of all required target controllers are counted to obtain the first number of target controller types. That is, it is not only necessary to count the number of controllers required in various application scenarios, but also to further count the types of all controllers and the corresponding types. It can be seen from FIG. 2 that 3 types of controllers are included in 5 specific application scenarios, namely: PCIE controller, SATA controller and EMAC controller.

Step S12: Determine a maximum value from the plurality of controllers, and determine a plurality of target Serdes PHYs having the same number as the maximum value.

In this embodiment, after counting the number of target controllers required in a variety of different application scenarios to obtain the corresponding number of controllers, further, determine the maximum value from the number of the above-mentioned controllers, and then Identify as many target Serdes PHYs as the maximum number above. For example, through the analysis of the five specific application scenarios in Figure 2, it can be seen that scene one, scene two, scene three, scene four, and scene five all require four controllers, so the controllers used in the five application scenarios The maximum number is 4. At this time, it is necessary to determine the corresponding 4 Serdes PHY chips.

Step S13: setting multiple different working modes, so as to match the target controller and multiple target Serdes PHYs in the different application scenarios under the multiple different working modes.

In this embodiment, after determining the maximum value from the plurality of controllers, and determining a plurality of target Serdes PHYs with the same number as the maximum value, multiple different working mode, so as to match the target controller and multiple target Serdes PHYs in the above-mentioned different application scenarios in a variety of different working modes, that is, multiple target controllers and multiple target Serdes PHYs are connected one by one match.

Specifically, setting a plurality of different working modes respectively may specifically include: setting a plurality of different working modes by rationally configuring a working mode register by a central processing unit. That is, the working mode register can be configured through a central processing unit (CPU, Central Processing Unit), and then multiple different working modes can be set through the configured working mode register.

In this embodiment, the matching of the target controller and the multiple target Serdes PHYs in the different application scenarios in a plurality of different working modes may specifically include: determining through the working mode register Generate a plurality of target selectors with the same number as the maximum value; respectively match each of the target selectors with a plurality of controllers with the same first quantity and the same type of the target controller, and match the The multiple target selectors are respectively matched one by one with multiple target Serdes PHYs. Specifically, refer to FIG. 3 and FIG. 4. FIG. 3 shows the quantitative relationship and corresponding relationship between the controller and the Serdes PHY chip in order to realize the above five specific application scenarios at the same time. It can be seen that, The 4 PCIE controllers in scenario 1, namely PCIE0, PCIE1, PCIE2, and PCIE3, respectively correspond to 4 Serdes PHY chips, namely Serdes PHY0, Serdes PHY1, Serdes PHY2, and Serdes PHY3; the 4 SATA controllers in scenario 2, namely SATA0, SATA1, SATA2, and SATA3 correspond to four Serdes PHY chips, namely Serdes PHY4, SerdesPHY5, Serdes PHY6, and Serdes PHY7; the four EMAC controls in scene three, namely EMAC0, EMAC1, EMAC2, and EMAC3, correspond to four Serdes PHY chips, Serdes PHY8, Serdes PHY9, Serdes PHY10, SerdesPHY11; 2 PCIE controllers and 2 SATA controllers in Scenario 4, namely PCIE0, PCIE1, SATA2, SATA3, correspond to 4 Serdes PHY chips respectively, namely Serdes PHY0, Serdes PHY1, Serdes PHY6, Serdes PHY7; 2 PCIE controllers, 1 SATA controller and 1 EMAC controller in scenario 5, namely PCIE0, PCIE1, SATA2, EMAC3, corresponding to 4 Serdes PHY chips , Serdes PHY0, Serdes PHY1, Serdes PHY6, Serdes PHY11. It can be seen from the above that a total of 12 Serdes PHY chips are currently required for the above five specific application scenarios. Figure 4 is a specific Serdes PHY multiplexing framework proposed by the present application. As can be seen from Figure 4, in order to realize the multiplexing of Serdes PHY, that is, to meet multiple application scenarios at the same time, the CPU can be used to reasonably configure the working mode register, and then A corresponding number of selectors are allocated through the working mode register, wherein the number of the selectors is the above-mentioned maximum value, that is, the value with the largest number of controllers in all application scenarios, and further, the controllers in each scenario are passed through the selector It is connected with the Serdes PHY chip, and finally realizes five different working modes. Specifically, when the working mode register is configured as scene 1: use PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, PCIE2 controller + Serdes PHY2, PCIE3 Controller + Serdes PHY3; when the working mode register is configured as scene 2: use SATA0 controller + Serdes PHY0, SATA1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, SATA3 controller + Serdes PHY3; when the working mode register is configured For scene three: use EMAC0 controller + Serdes PHY0, EMAC1 controller + Serdes PHY1, EMAC2 controller + Serdes PHY2, EMAC3 controller + Serdes PHY3; when the working mode register is configured as scene four: use PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, SATA2 controller + SerdesPHY2, SATA3 controller + Serdes PHY3; when the working mode register is configured as scene five: use PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, SATA2 controller +Serdes PHY2, EMAC3 controller +Serdes PHY3. It can be seen from Figure 4 that the above five specific application scenarios can be realized through four Serdes PHY chips. Compared with the traditional 12 Serdes PHY chips, the number of Serdes PHY chips is greatly reduced.

Further, after matching the target controllers and multiple target Serdes PHYs in the different application scenarios in a variety of different working modes, it may also include: when a new application scenario is detected, counting the The number and type of controllers required under the new application scenario are obtained to obtain the number of new application scenario controllers and the second number of new application scenario controller types; determine whether the new application scenario controller types belong to the target control type in the controller type; if the new application scenario controller types all belong to the type in the target controller type, then determine whether the number of the new application scenario controller exceeds the number of multiple target Serdes PHYs; if If the number of controllers in the new application scenario does not exceed the number of multiple target Serdes PHYs, use the target selector to match the controllers in the new application scenario with multiple target Serdes PHYs. In this embodiment, if a new application scenario is detected, the number and types of controllers required in the new application scenario can be counted first to obtain the number of controllers in the new application scenario and the number of controllers in the new application scenario type, and then further count the number of controller types in the new application scenario, that is, the second number; then determine whether all controller types in the above-mentioned new application scenario belong to the type in the above-mentioned target controller type, If all controller types existing in the above-mentioned new application scenario belong to the type in the above-mentioned target controller type, it is further judged whether the total number of controllers in the above-mentioned new application scenario exceeds the total number of multiple target Serdes PHYs, If the total number of controllers in the above-mentioned new application scenario does not exceed the number of multiple target Serdes PHYs, then the above-mentioned target selector can be directly used to connect the controller in the new application scenario with multiple target Serdes PHYs. match. For example, when monitoring application scenario six (2 SATA controllers and 1 EMAC controller + 4 PHYs), first count the number of controllers required in scenario six, that is, 3, and then judge the number of controllers in scenario six Whether the number of all controllers is greater than the number of Serdes PHYs in the above 5 specific application scenarios, that is, to judge whether 3 is greater than 4, since 3 is less than 4, you can configure the working mode register through the CPU to realize scenario 6, such as using SATA0 controller + Serdes PHY0, SATA1 controller + Serdes PHY1, EMAC2 controller + Serdes PHY2.

In this embodiment, using the target selector to match the controller in the new application scenario with multiple target Serdes PHYs may specifically include: using the target selector to match the controller with the second A plurality of controllers having the same number and type as the controllers in the new application scenario match a plurality of the target Serdes PHYs one by one. That is, when it is necessary to configure a new application scenario, first count the number of all controllers and the number of controller types in the new application scenario, and then determine whether the controller types in the new application scenario belong to the configured Serdes The controller type of the PHY chip, if the controller type in the new application scenario belongs to the controller type that has already been configured with Serdes PHY chips, then further judge whether the number of all controllers in the new application scenario exceeds multiple target Serdes If the total number of PHYs is not exceeded, the existing controller and Serdes PHY chip can be reused directly, and the selector can be used to create a connection relationship between the corresponding controller and the Serdes PHY chip. Specifically, the new controller type required by the new application scenario can be determined first, and then the selector is used to match the new controller type with the existing Serdes PHY chip one by one.

It can be seen that in the embodiment of the present application, the number of target controllers required in various application scenarios is firstly counted to obtain the corresponding number of multiple controllers, and then the maximum value is determined from the number of multiple controllers. And determine a plurality of target Serdes PHYs with the same number as the maximum value, and then set a variety of different working modes, so as to match the target control in the different application scenarios under a variety of different working modes tor and multiple of the target Serdes PHY. In the embodiment of the present application, by setting a variety of different working modes, and matching different controllers and Serdes PHYs in different modes, the Serdes PHYs can be flexibly multiplexed, thereby reducing the number of Serdes PHYs, and greatly reducing the chip size. Area, improved system integration, and reduced cost.

Correspondingly, the embodiment of the present application also discloses a Serdes PHY multiplexing device, as shown in Figure 5, the device includes:

Quantity statistics module 11, is used for counting the quantity of target controllers required in various different application scenarios respectively, and obtains the corresponding quantity of multiple controllers;

A determining module 12, configured to determine a maximum value from a plurality of the controllers, and determine a plurality of target Serdes PHYs having the same number as the maximum value;

The working mode setting module 13 is configured to respectively set multiple different working modes, so as to match the target controller and multiple target Serdes PHYs in the different application scenarios under the multiple different working modes.

For the specific work flow of each of the above modules, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

It can be seen that in the embodiment of the present application, the number of target controllers required in various application scenarios is firstly counted to obtain the corresponding number of multiple controllers, and then the maximum number of controllers is determined from the number of multiple controllers. value, and determine a plurality of target Serdes PHYs with the same number as the maximum value, and then set a plurality of different working modes, so as to match the described different application scenarios in a plurality of different working modes A target controller and a plurality of said target Serdes PHYs. In the embodiment of the present application, by setting a variety of different working modes, and matching different controllers and Serdes PHYs in different modes, the Serdes PHYs can be flexibly multiplexed, thereby reducing the number of Serdes PHYs, and greatly reducing the chip size. Area, improved system integration, and reduced cost.

In some specific embodiments, after the quantity statistics module 11, it may also include:

The controller type statistics unit is configured to make statistics on all the types of the target controllers required in the various application scenarios to obtain a first number of target controller types.

In some specific embodiments, the working mode setting module 13 may specifically include:

The working mode setting unit is used for setting multiple different working modes by rationally configuring the working mode registers by the central processing unit.

In some specific embodiments, the working mode setting module 13 may specifically include:

a selector determining unit, configured to determine a plurality of target selectors having the same number as the maximum value through the operating mode register;

a matching unit, configured to respectively match each of the target selectors with a plurality of controllers having the same first quantity and type of the target controllers, and match the matched target selectors with a plurality of The target SerdesPHY matches one by one.

In some specific embodiments, the Serdes PHY multiplexing device may also include:

A statistical unit, configured to count the number and types of controllers required in the new application scenario when a new application scenario is detected, to obtain the number of new application scenario controllers and the second number of new application scenario controller types;

A first judging unit, configured to judge whether the new application scene controller types all belong to the target controller types;

A second judging unit, configured to judge whether the number of new application scenario controllers exceeds the number of multiple target Serdes PHYs if the types of the new application scenario controllers belong to the type of the target controller type;

A first Serdes PHY matching unit, configured to use the target selector to match the controller in the new application scenario with the multiple target Serdes PHYs if the number of controllers in the new application scenario does not exceed the number of multiple The target Serdes PHY is matched.

In some specific embodiments, the first Serdes PHY matching unit may specifically include:

A second Serdes PHY matching unit, configured to use the target selector to match a plurality of controllers with the same type as the second quantity and the new application scenario controller one by one to a plurality of the target Serdes PHYs.

In some specific embodiments, the quantity statistics module 11 may specifically include:

The quantity statistics unit is used to count the number of PCIE controllers, SATA controllers and EMAC controllers required in various application scenarios, and obtain the corresponding number of PCIE controllers, SATA controllers and EMAC controllers .

Further, the embodiment of the present application also discloses an electronic device. FIG. 6 is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the figure should not be regarded as any limitation on the application scope of the present application.

FIG. 6 is a schematic structural diagram of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21 , at least one memory 22 , a power supply 23 , a communication interface 24 , an input/output interface 25 and a communication bus 26 . Wherein, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the Serdes PHY multiplexing method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is applicable Any communication protocol in the technical solution of the present application is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the external, and its specific interface type can be selected according to specific application needs, here Not specifically limited.

In addition, the memory 22, as a resource storage carrier, can be a read-only memory, random access memory, magnetic disk or optical disk, etc., and the resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage. .

Wherein, the operating system 221 is used to manage and control various hardware devices and computer programs 222 on the electronic device 20 , which may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program 222 that can be used to complete the Serdes PHY multiplexing method performed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

Further, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the Serdes PHY multiplexing method disclosed above is realized. Regarding the specific steps of the method, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related information, please refer to the description of the method part.

Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the possibilities of hardware and software. Interchangeability, the above description has generally described the components and steps of each example in terms of functionality. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

Finally, it should also be noted that in this text, relational terms such as first and second etc. are only used to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Above, a kind of Serdes PHY multiplexing method, device, equipment and storage medium provided by this application have been introduced in detail. In this paper, specific examples have been used to illustrate the principle and implementation of this application. The description of the above embodiments is only used To help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. In summary, this specification The content should not be construed as a limitation of the application.

Claims (10)

1. A Serdes PHY multiplexing method, comprising:

respectively counting the number of target controllers required in various different application scenes to obtain the number of a plurality of corresponding controllers;

determining a maximum value from a plurality of controller numbers, and determining a plurality of target Serdes PHYs which are the same as the maximum value;

setting a plurality of different operation modes respectively so as to match the target controller and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operation modes.

2. The Serdes PHY multiplexing method according to claim 1, wherein the counting the number of target controllers required in different application scenarios to obtain the number of corresponding controllers further comprises:

and counting the types of all the target controllers required in various different application scenes to obtain a first number of types of the target controllers.

3. The Serdes PHY multiplexing method of claim 2, wherein said separately setting a plurality of different operating modes comprises:

and various different working modes are set in a mode of reasonably configuring the working mode register by the central processing unit.

4. The Serdes PHY multiplexing method of claim 3, wherein said matching said target controller and said plurality of target Serdes PHYs in said different application scenarios in said plurality of said different operating modes comprises:

determining a plurality of target selectors with the same number as the maximum value through the working mode register;

and respectively matching each target selector with a plurality of controllers with the first number and the same type of target controller, and respectively matching the matched target selectors with a plurality of target Serdes PHYs one by one.

5. The Serdes PHY multiplexing method according to claim 4, further comprising:

when a new application scene is monitored, counting the number and types of controllers required in the new application scene to obtain the number of controllers in the new application scene and the types of controllers in the new application scene with a second number;

judging whether the new application scene controller types all belong to the types in the target controller types;

if the new application scene controller types all belong to the types in the target controller types, judging whether the number of the new application scene controllers exceeds the number of the plurality of target Serdes PHYs or not;

and if the number of the controllers of the new application scene does not exceed the number of the plurality of target Serdes PHYs, matching the controllers in the new application scene with the plurality of target Serdes PHYs by using the target selector.

6. The Serdes PHY multiplexing method of claim 5, wherein said matching a controller in the new application scenario with a plurality of the target Serdes PHYs using the target selector comprises:

matching a plurality of controllers of the same number as the second number and the new application scenario controller type one-to-one with a plurality of target Serdes PHYs using the target selector.

7. The Serdes PHY multiplexing method according to any of claims 1 to 6, wherein the counting of the number of target controllers required in a plurality of different application scenarios respectively to obtain a corresponding number of controllers comprises

And respectively counting the number of PCIE controllers, SATA controllers and EMAC controllers required in various different application scenes to obtain the number of the corresponding PCIE controllers, the number of the SATA controllers and the number of the EMAC controllers.

8. A Serdes PHY multiplexing device, comprising:

the quantity counting module is used for respectively counting the quantity of the target controllers required in various different application scenes to obtain the quantity of the corresponding controllers;

a determining module, configured to determine a maximum value from the plurality of controller quantities, and determine a plurality of target Serdes PHYs with the same quantity as the maximum value;

and the working mode setting module is used for respectively setting a plurality of different working modes so as to match the target controller and the plurality of target Serdes PHYs under different application scenes under the plurality of different working modes.

9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the Serdes PHY multiplexing method of any of claims 1 to 7.

10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the Serdes PHY multiplexing method of any of claims 1 to 7.

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