CN115248741A - Serdes PHY multiplexing method, device, equipment and storage medium - Google Patents
Serdes PHY multiplexing method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a Serdes PHY multiplexing method, a Serdes PHY multiplexing device, serdes PHY multiplexing equipment and a storage medium, which relate to the technical field of integrated circuits and comprise the following steps: respectively counting the number of target controllers required in various different application scenes to obtain the number of a plurality of corresponding controllers; determining a maximum value from a plurality of controller numbers, and determining a plurality of target Serdes PHYs which are the same as the maximum value; setting a plurality of different operation modes respectively so as to match the target controller and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operation modes. This application is through setting up multiple different mode to match different controllers and Serdes PHY under different modes, make Serdes PHY obtain nimble multiplexing, and then reduced Serdes PHY quantity, reduced the area of chip greatly, improved system integration degree, and the cost is reduced.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a Serdes PHY multiplexing method, apparatus, device, and storage medium.
Background
In the current testing scheme, a High-Speed Serial Interface (HSSI) is formed by one controller corresponding to one Serdes PHY (Serializer/Deserializer Physical Layer), and if a system integrates multiple High-Speed Serial interfaces at the same time, multiple controllers respectively correspond to multiple Serdes PHYs. For example, when there are four controllers, namely PCIE0 (Peripheral Component Interconnect Express), PCIE1, SATA (Serial Advanced Technology Attachment) and EMAC (Ethernet Media Access controller), four Serdes PHYs are respectively corresponding to the four Serdes PHYs, for example, PCIE0 controller corresponds to Serdes PHY0, PCIE1 controller corresponds to Serdes PHY1, SATA controller corresponds to Serdes PHY2, and EMAC controller corresponds to Serdes PHY3.
However, in practical application scenarios, different applications usually require multiple controllers of different types or the same type, and if the above-mentioned test scheme that one controller corresponds to one Serdes PHY is adopted, a large number of Serdes PHYs are required, which results in a large chip area and high cost.
Therefore, how to implement multiplexing of multiple Serdes PHYs in different application scenarios is a problem that needs to be solved by those skilled in the art at present.
Disclosure of Invention
In view of this, an object of the present application is to provide a method, an apparatus, a device, and a storage medium for multiplexing a Serdes PHY, which can flexibly multiplex the Serdes PHY, thereby reducing the number of Serdes PHYs, greatly reducing the chip area, improving the system integration level, and reducing the cost. The specific scheme is as follows:
in a first aspect, the present application discloses a Serdes PHY multiplexing method, comprising:
respectively counting the number of target controllers required in various different application scenes to obtain the number of a plurality of corresponding controllers;
determining a maximum value from a plurality of controller numbers, and determining a plurality of target Serdes PHYs which are the same as the maximum value;
setting a plurality of different operation modes respectively so as to match the target controller and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operation modes.
Optionally, after the counting the number of the target controllers required in the multiple different application scenarios respectively to obtain the number of the corresponding multiple controllers, the method further includes:
and counting the types of all the target controllers required in various different application scenes to obtain a first number of types of the target controllers.
Optionally, the setting of a plurality of different operating modes respectively includes:
and various different working modes are set in a mode of reasonably configuring the working mode register by the central processing unit.
Optionally, the matching the target controller and the target Serdes PHYs in the different application scenarios in the plurality of different operating modes includes:
determining a plurality of target selectors with the same number as the maximum value through the working mode register;
and respectively matching each target selector with a plurality of controllers with the first number and the same type of target controller, and respectively matching the matched target selectors with a plurality of target Serdes PHYs one by one.
Optionally, the Serdes PHY multiplexing method further includes:
when a new application scene is monitored, counting the number and types of controllers required in the new application scene to obtain the number of controllers in the new application scene and the types of controllers in the new application scene with a second number;
judging whether the new application scene controller types all belong to the types in the target controller types;
if the new application scene controller types all belong to the types in the target controller types, judging whether the number of the new application scene controllers exceeds the number of the target Serdes PHYs;
if the number of controllers of the new application scenario does not exceed the number of the plurality of target Serdes PHYs, matching the controllers in the new application scenario with the plurality of target Serdes PHYs by using the target selector.
Optionally, the matching, by using the target selector, the controller in the new application scenario with a plurality of target Serdes PHYs includes:
matching a plurality of controllers of the same number as the second number and the new application scenario controller type one-to-one with a plurality of target Serdes PHYs using the target selector.
Optionally, the number of target controllers required in multiple different application scenarios is counted respectively to obtain the corresponding number of multiple controllers, including
And respectively counting the number of PCIE controllers, SATA controllers and EMAC controllers required in various different application scenes to obtain the number of the corresponding PCIE controllers, the number of the SATA controllers and the number of the EMAC controllers.
In a second aspect, the present application discloses a Serdes PHY multiplexing apparatus, comprising:
the quantity counting module is used for respectively counting the quantity of the target controllers required in various different application scenes to obtain the quantity of the corresponding controllers;
a determining module, configured to determine a maximum value from the plurality of controller numbers, and determine a plurality of target Serdes PHYs with the same number as the maximum value;
and the working mode setting module is used for respectively setting a plurality of different working modes so as to match the target controller and the plurality of target Serdes PHYs under different application scenes under the plurality of different working modes.
In a third aspect, the present application discloses an electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the aforementioned Serdes PHY multiplexing method.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the aforementioned Serdes PHY multiplexing method.
It can be seen that, this application is first respectively to the required target controller's quantity under the multiple different application scenes make statistics of, obtains corresponding a plurality of controller quantity, then follow a plurality of determine the maximum value in the controller quantity, and determine with a plurality of target Serdes PHY that the maximum value quantity is the same, set up multiple different operating mode respectively again to in a plurality of different operating mode match under the different application scenes target controller and a plurality of target Serdes PHY. This application is through setting up multiple different mode to match different controllers and Serdes PHY under different modes, make Serdes PHY obtain nimble multiplexing, and then reduced Serdes PHY quantity, reduced the area of chip greatly, improved system integration degree, and the cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flow chart of a Serdes PHY multiplexing method disclosed herein;
fig. 2 is a diagram illustrating a specific Serdes PHY application scenario disclosed herein;
FIG. 3 is a block diagram of a conventional Serdes PHY utilization method disclosed herein;
FIG. 4 is a block diagram of a particular Serdes PHY multiplexing method disclosed herein;
fig. 5 is a schematic structural diagram of a Serdes PHY multiplexing apparatus disclosed in the present application;
fig. 6 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
The embodiment of the application discloses a Serdes PHY multiplexing method, which is shown in figure 1 and comprises the following steps:
step S11: and respectively counting the number of target controllers required in various different application scenes to obtain the number of the corresponding controllers.
In this embodiment, the number of controllers required in various different application scenarios needs to be counted to obtain the number of corresponding multiple controllers. The target controller includes, but is not limited to, a PCIE controller, a SATA controller, an EMAC controller, and the like.
In a specific embodiment, the counting the number of target controllers required in a plurality of different application scenarios respectively to obtain the number of corresponding controllers may specifically include: and respectively counting the number of PCIE controllers, SATA controllers and EMAC controllers required in various different application scenes to obtain the corresponding number of PCIE controllers, SATA controllers and EMAC controllers. For example, referring to fig. 2, fig. 2 shows 5 specific application scenarios of the Serdes PHY chip, and statistics is respectively performed on the types and the number of controllers used in the 5 application scenarios in fig. 2 to obtain: in scenario one, 4 PCIE controllers +4 PHYs are required; scene two, 4 SATA controllers +4 PHYs are needed; in a third scenario, 4 EMAC controllers +4 PHYs are required; scene four, 2 PCIE controllers and 2 SATA controllers +4 PHYs are required; scene five, 2 PCIE controllers, 1 SATA controller, and 1 EMAC controller +4 PHYs are required.
In this embodiment, after the counting the number of the target controllers required in the multiple different application scenarios respectively to obtain the corresponding number of the multiple controllers, the method may further include: and counting the types of all the target controllers required in various different application scenes to obtain a first number of types of the target controllers. That is, not only the number of controllers required in various application scenarios needs to be counted, but also the types and the corresponding types of the controllers need to be further counted. As shown in fig. 2, a total of 3 types of controllers are included in 5 specific application scenarios, which are respectively: PCIE controller, SATA controller and EMAC controller.
Step S12: determining a maximum value from a plurality of the controller numbers, and determining a plurality of target Serdes PHYs which are the same as the maximum value number.
In this embodiment, after the number of target controllers required in a plurality of different application scenarios is respectively counted to obtain a corresponding number of controllers, a maximum value is further determined from the number of controllers, and then a plurality of target Serdes PHYs having the same number as the maximum value are determined. For example, it can be known from the analysis of 5 specific application scenarios in fig. 2 that 4 controllers are required for scenario one, scenario two, scenario three, scenario four, and scenario five, so that the maximum value of the number of controllers used in the 5 application scenarios is 4, and at this time, 4 Serdes PHY chips are required to be defined.
Step S13: setting a plurality of different operating modes respectively so as to match the target controller and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operating modes.
In this embodiment, after determining the maximum value from the number of the plurality of controllers and determining the plurality of target Serdes PHYs having the same number as the maximum value, a plurality of different operating modes may be set for each of the application scenarios, so as to match the target controllers and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operating modes, that is, match the plurality of target controllers and the plurality of target Serdes PHYs one by one.
Specifically, the setting of the plurality of different working modes respectively may specifically include: and various different working modes are set in a mode of reasonably configuring the working mode register by the central processing unit. That is, the Central Processing Unit (CPU) may configure the operation mode register, and then set a plurality of different operation modes through the configured operation mode register.
In this embodiment, the matching the target controller and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operating modes may specifically include: determining a plurality of target selectors with the same number as the maximum value through the working mode register; and respectively matching each target selector with a plurality of controllers with the first number and the same type of target controller, and respectively matching the matched target selectors with a plurality of target Serdes PHYs one by one. Specifically, referring to fig. 3 and 4, fig. 3 shows the quantity relationship and the corresponding relationship between the controllers and Serdes PHY chips when the 5 specific application scenarios are implemented at the same time in the conventional manner, and it can be seen that 4 PCIE controllers in scenario one, namely PCIE0, PCIE1, PCIE2, and PCIE3, respectively correspond to 4 Serdes PHY chips, namely Serdes PHY0, serdes PHY1, serdes PHY2, and Serdes PHY3; the 4 SATA controls in the scene two, namely SATA0, SATA1, SATA2, SATA3, correspond to the 4 Serdes PHY chips, namely Serdes PHY4, serdes PHY5, serdes PHY6, and Serdes PHY7, respectively; the control of 4 EMACs in the third scene, namely EMAC0, EMAC1, EMAC2 and EMAC3, respectively corresponds to 4 Serdes PHY chips, namely Serdes PHY8, serdes PHY9, serdes PHY10 and Serdes PHY11; in the scene four, 2 PCIE controllers and 2 SATA controllers, namely PCIE0, PCIE1, SATA2, and SATA3, respectively correspond to 4 Serdes PHY chips, namely Serdes PHY0, serdes PHY1, serdes PHY6, and Serdes PHY7; in the scene five, 2 PCIE controllers, 1 SATA controller, and 1 EMAC controller, that is, PCIE0, PCIE1, SATA2, and EMAC3 correspond to 4 Serdes PHY chips, that is, serdes PHY0, serdes PHY1, serdes PHY6, and Serdes PHY11, respectively. As can be seen, a total of 12 Serdes PHY chips are currently required for the above 5 specific application scenarios. Fig. 4 shows a specific Serdes PHY multiplexing framework proposed in the present application, and as shown in fig. 4, in order to implement Serdes PHY multiplexing, that is, to simultaneously satisfy multiple application scenarios, a CPU may reasonably configure a working mode register, and then allocate a corresponding number of selectors through the working mode register, where the number of selectors is the maximum value, that is, the maximum value of the number of controllers in all application scenarios, and further, the controller in each scenario is connected to a Serdes PHY chip through the selector, and finally, five different working modes are implemented, specifically, when the working mode register is configured as scenario one: the PCIE-0 controller + Serdes PHY0, the PCIE-1 controller + Serdes PHY1, the PCIE-2 controller + Serdes PHY2, the PCIE-3 controller + Serdes PHY3 are used; when the operating mode register is configured as scenario two: using SATA0 controller + Serdes PHY0, SATA1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, SATA3 controller + Serdes PHY3; when the operating mode register is configured as scenario three: the EMAC0 controller + Serdes PHY0, the EMAC1 controller + Serdes PHY1, the EMAC2 controller + Serdes PHY2 and the EMAC3 controller + Serdes PHY3 are used; when the operating mode register is configured as scenario four: PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, SATA3 controller + Serdes PHY3 are used; when the operating mode register is configured as scenario five: PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, EMAC3 controller + Serdes PHY3 are used. As can be seen from fig. 4, the above 5 specific application scenarios can be realized by 4 Serdes PHY chips, and the number of Serdes PHY chips is greatly reduced compared to the conventional 12 Serdes PHY chips.
Further, after matching the target controller and the target Serdes PHYs in the different application scenarios in the plurality of different operation modes, the method may further include: when a new application scene is monitored, counting the number and types of controllers required in the new application scene to obtain the number of controllers in the new application scene and the types of controllers in the new application scene with a second number; judging whether the new application scene controller types all belong to the types in the target controller types; if the new application scene controller types all belong to the types in the target controller types, judging whether the number of the new application scene controllers exceeds the number of the target Serdes PHYs; and if the number of the controllers of the new application scene does not exceed the number of the plurality of target Serdes PHYs, matching the controllers in the new application scene with the plurality of target Serdes PHYs by using the target selector. In this embodiment, if a new application scenario is monitored, the number and types of controllers required in the new application scenario may be counted first to obtain the number of controllers in the new application scenario and the types of controllers in the new application scenario, and then the number of controller types in the new application scenario, that is, the second number may be further counted; and then judging whether all controller types existing in the new application scene belong to the types in the target controller types, if so, further judging whether the total number of the controllers in the new application scene exceeds the total number of a plurality of target Serdes PHYs, and if not, directly utilizing the target selector to match the controllers in the new application scene with the plurality of target Serdes PHYs. For example, when an application scene six (2 SATA controllers and 1 EMAC controller +4 PHYs) is monitored, the number of controllers which are required in the scene six is counted, that is, 3 controllers are counted, and then it is determined whether the number of all the controllers in the scene six is greater than the number of Serdes PHYs in the above 5 specific application scenes, that is, it is determined whether 3 is greater than 4, and since 3 is less than 4, the scene six can be implemented by configuring a working mode register through a CPU, for example, using a SATA0 controller + Serdes PHY0, a SATA1 controller + Serdes PHY1, an EMAC2 controller + Serdes PHY2.
In this embodiment, the matching the controller in the new application scenario with the plurality of target Serdes PHYs by using the target selector may specifically include: matching a plurality of controllers of the same number as the second number and the new application scenario controller type one-to-one with a plurality of target Serdes PHYs using the target selector. That is, when a new application scenario needs to be configured, the number of all controllers and the number of controller types in the new application scenario are counted, then it is determined whether the controller type in the new application scenario completely belongs to the controller type already configured with the Serdes PHY chip, if the controller type in the new application scenario completely belongs to the controller type already configured with the Serdes PHY chip, it is further determined whether the number of all controllers in the new application scenario exceeds the total number of the target Serdes PHYs, if not, the existing controllers and Serdes PHY chips can be directly multiplexed, and the selector is used to create the connection relationship between the corresponding controllers and the Serdes PHY chips. Specifically, a new controller type required by a new application scenario may be determined, and then the new controller type may be matched with an existing Serdes PHY chip by using a selector.
It can be seen that, in the embodiment of the present application, the number of target controllers required in a plurality of different application scenarios is counted respectively to obtain the number of corresponding plurality of controllers, then the maximum value is determined from the number of the plurality of controllers, a plurality of target Serdes PHYs having the same number as the maximum value are determined, and then a plurality of different operating modes are set respectively, so that the target controllers and the plurality of target Serdes PHYs in different application scenarios are matched in the plurality of different operating modes. The embodiment of the application sets up multiple different working modes and matches different controllers and Serdes PHYs in different modes, so that the Serdes PHYs are flexibly multiplexed, the number of the Serdes PHYs is reduced, the area of a chip is greatly reduced, the system integration level is improved, and the cost is reduced.
Correspondingly, the embodiment of the present application further discloses a Serdes PHY multiplexing apparatus, as shown in fig. 5, the apparatus includes:
the quantity counting module 11 is used for respectively counting the quantity of target controllers required in various different application scenes to obtain the quantity of a plurality of corresponding controllers;
a determining module 12, configured to determine a maximum value from a plurality of controller numbers, and determine a plurality of target Serdes PHYs with the same number as the maximum value;
a working mode setting module 13, configured to set multiple different working modes respectively, so as to match the target controller and multiple target Serdes PHYs in different application scenarios in the multiple different working modes.
For the specific work flow of each module, reference may be made to corresponding content disclosed in the foregoing embodiments, and details are not repeated here.
It can be seen that, in the embodiment of the present application, the number of target controllers required in a plurality of different application scenarios is counted respectively to obtain the number of corresponding plurality of controllers, then the maximum value is determined from the number of the plurality of controllers, a plurality of target Serdes PHYs having the same number as the maximum value are determined, and then a plurality of different operating modes are set respectively, so that the target controllers and the plurality of target Serdes PHYs in different application scenarios are matched in the plurality of different operating modes. The embodiment of the application sets up multiple different working modes and matches different controllers and Serdes PHYs in different modes, so that the Serdes PHYs are flexibly multiplexed, the number of the Serdes PHYs is reduced, the area of a chip is greatly reduced, the system integration level is improved, and the cost is reduced.
In some specific embodiments, after the quantity statistics module 11, the method may further include:
and the controller type counting unit is used for counting the types of all the target controllers required under various different application scenes to obtain a first number of target controller types.
In some specific embodiments, the operating mode setting module 13 may specifically include:
and the working mode setting unit is used for setting various different working modes in a mode of reasonably configuring the working mode register through the central processing unit.
In some specific embodiments, the working mode setting module 13 may specifically include:
a selector determining unit configured to determine, by the operating mode register, a plurality of target selectors having the same number as the maximum value;
and the matching unit is used for respectively matching each target selector with a plurality of controllers with the same first number and the same type of the target controllers, and respectively matching the matched target selectors with a plurality of target Serdes PHYs one by one.
In some specific embodiments, the Serdes PHY multiplexing apparatus may further include:
the counting unit is used for counting the number and types of the controllers required in the new application scene when the new application scene is monitored, so as to obtain the number of the controllers in the new application scene and the types of the controllers in the new application scene in a second number;
the first judging unit is used for judging whether the new application scene controller types all belong to the types in the target controller types;
a second determining unit, configured to determine whether the number of new application scenario controllers exceeds the number of target Serdes PHYs if the new application scenario controller types all belong to the types in the target controller types;
a first Serdes PHY matching unit to match a controller in the new application scenario with a plurality of the target Serdes PHYs using the target selector if the new application scenario controller number does not exceed a number of the plurality of the target Serdes PHYs.
In some embodiments, the first Serdes PHY matching unit may specifically include:
a second Serdes PHY matching unit for matching a plurality of controllers of the same number as the second number and the new application scenario controller type one by one with the target selectors.
In some specific embodiments, the quantity statistics module 11 may specifically include:
and the quantity counting unit is used for respectively counting the quantity of the PCIE controllers, the SATA controllers and the EMAC controllers required in various different application scenes to obtain the corresponding quantity of the PCIE controllers, the SATA controllers and the EMAC controllers.
Further, an electronic device is disclosed in the embodiments of the present application, and fig. 6 is a block diagram of an electronic device 20 according to an exemplary embodiment, which should not be construed as limiting the scope of the application.
Fig. 6 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein, the memory 22 is used for storing a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the Serdes PHY multiplexing method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
In addition, the storage 22 is used as a carrier for storing resources, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage manner may be a transient storage manner or a permanent storage manner.
The operating system 221 is used for managing and controlling each hardware device on the electronic device 20 and the computer program 222, and may be Windows Server, netware, unix, linux, or the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the Serdes PHY multiplexing method disclosed by any of the foregoing embodiments and executed by the electronic device 20.
Further, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the Serdes PHY multiplexing method disclosed above. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The Serdes PHY multiplexing method, apparatus, device and storage medium provided by the present application are introduced in detail above, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A Serdes PHY multiplexing method, comprising:
respectively counting the number of target controllers required in various different application scenes to obtain the number of a plurality of corresponding controllers;
determining a maximum value from a plurality of controller numbers, and determining a plurality of target Serdes PHYs which are the same as the maximum value;
setting a plurality of different operation modes respectively so as to match the target controller and the plurality of target Serdes PHYs in the different application scenarios in the plurality of different operation modes.
2. The Serdes PHY multiplexing method according to claim 1, wherein the counting the number of target controllers required in different application scenarios to obtain the number of corresponding controllers further comprises:
and counting the types of all the target controllers required in various different application scenes to obtain a first number of types of the target controllers.
3. The Serdes PHY multiplexing method of claim 2, wherein said separately setting a plurality of different operating modes comprises:
and various different working modes are set in a mode of reasonably configuring the working mode register by the central processing unit.
4. The Serdes PHY multiplexing method of claim 3, wherein said matching said target controller and said plurality of target Serdes PHYs in said different application scenarios in said plurality of said different operating modes comprises:
determining a plurality of target selectors with the same number as the maximum value through the working mode register;
and respectively matching each target selector with a plurality of controllers with the first number and the same type of target controller, and respectively matching the matched target selectors with a plurality of target Serdes PHYs one by one.
5. The Serdes PHY multiplexing method according to claim 4, further comprising:
when a new application scene is monitored, counting the number and types of controllers required in the new application scene to obtain the number of controllers in the new application scene and the types of controllers in the new application scene with a second number;
judging whether the new application scene controller types all belong to the types in the target controller types;
if the new application scene controller types all belong to the types in the target controller types, judging whether the number of the new application scene controllers exceeds the number of the plurality of target Serdes PHYs or not;
and if the number of the controllers of the new application scene does not exceed the number of the plurality of target Serdes PHYs, matching the controllers in the new application scene with the plurality of target Serdes PHYs by using the target selector.
6. The Serdes PHY multiplexing method of claim 5, wherein said matching a controller in the new application scenario with a plurality of the target Serdes PHYs using the target selector comprises:
matching a plurality of controllers of the same number as the second number and the new application scenario controller type one-to-one with a plurality of target Serdes PHYs using the target selector.
7. The Serdes PHY multiplexing method according to any of claims 1 to 6, wherein the counting of the number of target controllers required in a plurality of different application scenarios respectively to obtain a corresponding number of controllers comprises
And respectively counting the number of PCIE controllers, SATA controllers and EMAC controllers required in various different application scenes to obtain the number of the corresponding PCIE controllers, the number of the SATA controllers and the number of the EMAC controllers.
8. A Serdes PHY multiplexing device, comprising:
the quantity counting module is used for respectively counting the quantity of the target controllers required in various different application scenes to obtain the quantity of the corresponding controllers;
a determining module, configured to determine a maximum value from the plurality of controller quantities, and determine a plurality of target Serdes PHYs with the same quantity as the maximum value;
and the working mode setting module is used for respectively setting a plurality of different working modes so as to match the target controller and the plurality of target Serdes PHYs under different application scenes under the plurality of different working modes.
9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the Serdes PHY multiplexing method of any of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the Serdes PHY multiplexing method of any of claims 1 to 7.
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