CN115243034A - Readout circuit of photoelectric imaging array, and readout circuit calibration method and system - Google Patents

Abstract

The invention discloses a reading circuit of a photoelectric imaging array, a reading circuit calibration method and a system, relates to the technical field of integrated circuits, and solves the problem that random deviation exists between a CDS (complementary metal oxide semiconductor) capacitor and a feedback capacitor in an MDAC (medium-density digital ac) of the existing reading circuit, so that the output voltage of the MDAC exceeds the input voltage range of a rear-stage ADC (analog-to-digital converter), and the technical scheme is as follows: whether the output of the backup ADC is saturated or not is judged by adding a saturation detection circuit, when the saturation detection circuit detects that the output of the backup ADC is saturated, the DAC input is configured through the SPICFG, so that the output voltage of the integrator is equal to the SUBADC reference voltage, the proportional deviation of a sampling capacitor in the integrator and a feedback capacitor in the MDAC is detected, the SUBADC reference voltage is automatically adjusted, and the purpose of ensuring the normal work of a whole signal link is achieved.

Description

Reading circuit of photoelectric imaging array, and reading circuit calibration method and system

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a readout circuit of a photoelectric imaging array, a readout circuit calibration method and a readout circuit calibration system.

Background

Photoelectric imaging array: the photosensitive diode is a PN junction formed by an N-type semiconductor and a P-type semiconductor, and when the photosensitive diode works, a reverse bias voltage is applied to generate electric charges under illumination, and the generated electric charges are in direct proportion to the incident light intensity. An array structure composed of a plurality of photodiodes can be used for imaging. After exposure of the array, the amount of charge generated on the diodes reflects the information of the image.

A readout circuit: the signal generated by the photodiode array converts the analog signal of each pixel into a digital signal by a readout circuit. The charge information of the diode array is read out row by row, and each column of diodes shares one reading circuit. Firstly, the electric charge in the diode is converted into voltage through an integrator, then the voltage is converted into a digital signal through an ADC (analog-to-digital converter), and the information of the image is reconstructed through digital signal processing.

The PPIPELINE ADC (analog-digital converter with multi-stage structure working in series) is a multi-bit MDAC (multiplying digital-analog converter) at the first stage, high-bit digital output is generated, the residual error of the MDAC is converted by the ADC at the later stage to generate low-bit output, and the high-bit digital signal and the low-bit digital signal are combined to obtain ADC output. The structure can realize high-precision and high-speed analog-digital converters.

In the original reading circuit structure, a SUBADC (sub analog digital converter) and a CDS capacitor (sampling capacitor) are placed in an integrator channel, and because random deviation exists between the CDS capacitor and a feedback capacitor in an MDAC, the output voltage of the MDAC exceeds the input voltage range of a rear-stage ADC, so that the conversion result of the whole ADC is wrong.

Disclosure of Invention

The invention aims to provide a readout circuit of a photoelectric imaging array, a readout circuit calibration method and a readout circuit calibration system, which achieve the purposes of detecting the proportional deviation of a sampling capacitor in an integrator and a feedback capacitor in an MDAC, automatically adjusting the reference voltage of the SUBADC and ensuring the normal work of a whole signal link.

The technical purpose of the invention is realized by the following technical scheme:

a method of calibrating readout circuitry of a photoelectric imaging array, comprising the steps of:

s1, carrying out state detection on a back ADC output value under the current SUBADC reference voltage;

s2, when the backskend ADC output value is an abnormal value, adjusting the SUBADC reference voltage through an internal register to obtain an adjusted backskend ADC output value, updating the backskend ADC output value by using the adjusted backskend ADC output value, and executing S1; and outputting a normal value of the backskend ADC when the backskend ADC output value is not an abnormal value.

Further, the backskend ADC output value is an abnormal value, and includes: when the backstend ADC input value is larger than the backstend ADC maximum input threshold value, the backstend ADC output value is 1; and when the backskend ADC input value is smaller than the minimum input threshold value of the backskend ADC, the backskend ADC output value is 0.

Further, the accuracy of the SUBADC is 5 bits.

Further, the backskend ADC maximum input threshold is 2V.

Further, the minimum input threshold of the backup ADC is-2V.

A system for calibrating readout circuitry of a photoelectric imaging array, comprising: the detection module is used for carrying out state detection on the backskend ADC output value under the current SUBADC reference voltage; the configuration module is used for adjusting the SUBADC reference voltage through an internal register when the backhaul ADC output value is an abnormal value to obtain an adjusted backhaul ADC output value, updating the backhaul ADC output value by using the adjusted backhaul ADC output value and executing S2; and outputting a normal value of the backskend ADC when the backskend ADC output value is not an abnormal value.

Further, the configuration module comprises an internal register and a DAC buffer; the input end of the internal register is connected with the output end of the detection module; the input end of the DAC buffer is connected with the output end of the internal register; and the output end of the DAC buffer is connected with the input end of the integrator through a charge injection capacitor.

Further, the DAC buffer comprises a DAC circuit and a buffer driving circuit connected to an output terminal of the DAC circuit; the DAC circuit is connected with the internal register; and the output end of the buffer driving circuit is connected with the charge injection capacitor.

Further, the readout circuit of the photoelectric imaging array comprises the readout circuit calibration system of the photoelectric imaging array and a PIPELINE ADC circuit, wherein the output end of a back ADC in the PIPELINE ADC circuit is connected with the input end of the detection circuit.

Further, the backup ADC is a successive approximation ADC.

Compared with the prior art, the invention has the following beneficial effects:

a calibration method for a reading circuit of a photoelectric imaging array is characterized in that the detection of proportional deviation of a sampling capacitor in an integrator and a feedback capacitor in an MDAC (multiple-input multiple-output) is realized by carrying out state detection on an output value of a background ADC (analog-to-digital converter), and the purpose of ensuring the normal work of a whole signal link is achieved by automatically adjusting the reference voltage of an SUBADC through an internal register.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a circuit configuration diagram of a PIPELINE ADC (analog-to-digital converter operating in series in a multi-stage configuration);

FIG. 2 is a schematic structural diagram of a conventional readout circuit of a photoelectric imaging array;

fig. 3 is a transfer curve of input and output of an MDAC in a conventional readout circuit of a photo imaging array, where 3 (a) represents the MDAC transfer curve when CSp = CSn/Cf = 16; 3 (b) indicates the MDAC transfer curve when the gain between CSp and CSn exceeds 16.25; 3 (c) indicates an MDAC transfer curve for a gain between CSp and CSn of less than 15.75;

FIG. 4 is a schematic diagram of a readout circuit of a photo-imaging array according to an embodiment;

FIG. 5 is a schematic diagram of an integrator circuit employed in a readout circuit of a photoelectric imaging array according to an embodiment;

FIG. 6 is a MDAC transfer curve after calibration using a readout circuit of a photo-imaging array according to one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.

The embodiment is as follows: a readout circuit of a photoelectric imaging array, a readout circuit calibration method and a system are provided.

Fig. 1 shows a circuit configuration diagram of a PIPELINE ADC (analog-digital converter operating in series in a multi-stage configuration). The first stage is an MDAC (Multiply DAC multiplying digital-to-analog converter) which comprises three PARTs of PART1, PART2 and PART 3. PART1 comprises the following PARTs, IP and IN are differential input terminals, SW1 and SW2 are sampling switches, and CSp and CSn are sampling capacitors for sampling differential input signals. A SUBADC (sub analog to digital converter) converts a differential input into a digital signal, the SUBADC being a multi-bit output. PART2 contains the following PARTs, SWP, SWN, SWD are sampling switches, which are open at the time of sampling, where SWD is a switch for outputting a multi-bit digital signal from the SUBADC. PART3 comprises the following PARTs, DACP and DACN are differential DACs (differential digital-to-analog converters), whose inputs are the output of SUBADC, cf is the feedback capacitance, OP is the residual amplifier. The MDAC realizes analog output sampling and is roughly quantized by the SUBADC, then the residual error is amplified and output after the DAC output is subtracted from the input, and the roughly quantized result of the SUBADC is output.

And the back ADC of the PIPELINE ADC converts the residual error of the MDAC to obtain the digital output of the back stage, and the SUBADC output of the first stage and the back ADC output obtain the digital output result of the total ADC (analog-digital converter).

Fig. 2 shows the structure of the readout circuit of the existing photo imaging array. The photodiodes of each column share one integrator channel. INT in the figure is an integrator that converts the charge of the photodiode into a voltage. The method comprises the following steps that PART1 of a PIPELINE ADC shown in the figure 1 is placed in an integrator channel, PART2 is used as a MUX switch, an MDAC subtracts an analog sampling voltage from a DAC voltage controlled by a SUBADC to obtain a residual voltage, the other function of the MDAC is used as a MUX buffer, analog sampling of each integrator channel is processed by the MDAC to obtain the residual voltage, and the residual voltage is converted by a backup ADC.

Wherein, the precision of SUBADC is 5bit, the sampling capacitance in the integrator is CSp and CSn, the ratio of the sampling capacitance to the MDAC feedback capacitance Cf is 16, and the input range of the backskend ADC is-2V. The transition curves of the input and output of the MDAC are shown in fig. 3, in which the X axis is the MDAC input voltage, the Y axis is the MDAC output voltage, a binary number indicates the conversion result of the subac, X = (0-0.125), the subac output code is 00000, X = (0.125-0.25), the subac output code is 00001, and the subac output code is increased by 1LSB every 0.125v until X = (3.875V-4V), and the subac output code is 11111. Ideally, CSp = CSn/Cf =16, MDAC transfer curve is shown in fig. 3 (a), integrator output voltage, i.e. MDAC input voltage range 0-4V, MDAC output voltage range-1V, in the input range of the back ADC. If the gain between CSp and CSn exceeds 16.25, the output voltage of the MDAC will exceed 2V as the input voltage increases, as shown in 3 (b). If the gain between CSp and CSn is below 15.75, the output of the MDAC will be less than-2V as the input voltage increases, as shown in 3 (c). Where both cases 3 (b) and 3 (c) exceed the input range of the backskend ADC, resulting in erroneous backskend ADC outputs.

The embodiment provides a calibration method for a readout circuit of a photoelectric imaging array, which comprises the following steps:

s1, carrying out state detection on a back ADC output value under the current SUBADC reference voltage;

s2, when the backskend ADC output value is an abnormal value, adjusting the SUBADC reference voltage through an internal register to obtain an adjusted backskend ADC output value, updating the backskend ADC output value by using the adjusted backskend ADC output value, and executing S1; and outputting a normal value of the backskend ADC when the backskend ADC output value is not an abnormal value. When the backskend ADC input value is larger than the maximum input threshold value of the backskend ADC, the backskend ADC output value is 1; when the backskend ADC input value is less than the backskend ADC minimum input threshold value, the backskend ADC output value is 0. And the precision of the SUBADC is 5 bits, the maximum input threshold value of the backup ADC is 2V, the minimum input threshold value of the backup ADC is-2V, and the method specifically comprises the following steps:

the precision of the SUBADC is 5bit, the sampling capacitances in the integrator are CSp and CSn, the ratio of the sampling capacitances to the MDAC feedback capacitance Cf is 16, the input range of the backsond ADC is-2V, if the input of the backsond ADC exceeds 2V, the output is all 1, and if the input of the backsond ADC is less than-2V, the output is all 0. And if the backsand ADC outputs are all detected to be 0, the ratio of the sampling capacitance of the integrator to the MDAC feedback capacitance exceeds 15.75. If the backup ADC outputs are all detected to be 1, the digital input of the DAC is reduced through the SPICFG (internal register configured through an SPI interface) module configuration, the reference voltages of the integrator and the SUBADC are reduced at the moment, the analog input corresponding to each code is reduced, and the DAC output is reduced through the SPICFG configuration until the output of the backup ADC is in a normal range.

Similarly, when the backskend ADC outputs are all detected to be 0, the DAC input is increased through the SPICFG module until the backskend ADC outputs are in a normal range.

The present embodiment further provides a calibration system for a readout circuit of a photoelectric imaging array, including:

the detection module is used for S1, carrying out state detection on a back ADC output value under the current SUBADC reference voltage;

the configuration module is used for S2, when the backhaul ADC output value is an abnormal value, adjusting the SUBADC reference voltage through an internal register to obtain an adjusted backhaul ADC output value, updating the backhaul ADC output value by using the adjusted backhaul ADC output value, and executing S2; and outputting a normal value of the backskend ADC when the backskend ADC output value is not an abnormal value. The configuration module comprises an internal register and a DAC buffer; the input end of the internal register is connected with the output end of the detection module; the input end of the DAC buffer is connected with the output end of the internal register; and the output end of the DAC buffer is connected with the input end of the integrator through a charge injection capacitor. The DAC buffer comprises a DAC circuit and a buffer driving circuit connected with the output end of the DAC circuit; the DAC circuit is connected with the internal register; and the output end of the buffer driving circuit is connected with the charge injection capacitor.

The embodiment also provides a readout circuit of the photoelectric imaging array, which comprises a readout circuit calibration system of the photoelectric imaging array and a PIPELINE ADC circuit, wherein the output end of a backup ADC in the PIPELINE ADC circuit is connected with the input end of the detection circuit. The backskend ADC is a SAR ADC (successive approximation ADC).

As shown in fig. 4, a saturation detection circuit, an SPICFG circuit, a DAC circuit and its buffer driving circuit are added to the original readout circuit shown in fig. 2 as the reference voltage of the SUBADC, the DAC buffer output voltage is adjusted by the register configuration, and a charge injection capacitor is added to the input terminal of the integrator, the DAC buffer output is connected to the capacitor. When the saturation detection circuit detects that the output of the back ADC is saturated, the reference of the SUBADC is adjusted by the SPICFG circuit while the integrator output voltage changes until the output voltage of the MDAC is within the normal input range of the back ADC.

As shown in FIG. 5, a capacitor Cd is added at the input end of the integrator, the capacitance value of Cd is adjustable, the integrator capacitance of the integrator is Cint, and the capacitance is also adjustable. Cd and Cint were ensured to be equal at saturation detection. The SPICFG circuit writes configuration information to the internal register through the SPI bus for controlling the digital input of the DAC. The DAC and the backup ADC use the same reference voltage VREF. And a buffer circuit is added at the output end of the DAC to improve the driving capability, the buffer output is used as the reference voltage of the SUBADC, and meanwhile, the buffer output is also connected with a capacitor Cd at the input end of the integrator. Since Cd and Cint are equal, the integrator output voltage is equal to the SUBADC reference voltage, corresponding to the maximum integrator output. When the saturation detection is carried out, the saturation detection circuit, the SPICFG, the DAC, the buffer, the integrator, the MDAC and the backskend ADC form a signal link. The saturation detection circuit is connected with the output end of the back ADC, if the input of the back ADC exceeds 2V, the output is all 1, and if the input of the back ADC is less than-2V, the output is all 0. Detecting that the backskend ADC outputs are all 1 indicates that the ratio of the integrator sampling capacitance to the MDAC feedback capacitance exceeds 16.25, and if the backskend ADC outputs are all 0, indicates that the ratio of the integrator sampling capacitance to the MDAC feedback capacitance exceeds 15.75. And if the backskend ADC outputs are all detected to be 1, reducing the digital input of the DAC through the SPICFG module configuration, reducing the reference voltage of the integrator and the SUBADC at the moment, namely reducing the analog input corresponding to each code, and reducing the DAC output through the SPICFG configuration until the output of the backskend ADC is in a normal range. Similarly, when the backskend ADC outputs are all detected to be 0, the DAC input is increased through the SPICFG module until the backskend ADC outputs are in a normal range. The adjusted MDAC transfer curve is shown in fig. 6. And taking the final SPICFG configuration value as the DAC input in normal operation.

As shown in fig. 6, the calibrated transfer curve is illustrated in the case of two gain deviations, and as shown in fig. 6 (a), when CSp = CSn/Cf =16.6, the subdc reference voltage is reduced to 3.84v, the subdc precision is still 5 bits, the voltage represented by each 1LSB is 0.12V, the MDAC output voltage after multiplying by 16.6 times the gain is still between-1V and 1V, and the backhaul ADC operates normally. As shown in fig. 6 (b), when CSp = CSn/Cf =15.4, the subdc reference voltage is increased to 4.16v, the subdc accuracy is still 5bit, the voltage represented by every 1LSB is 0.13V, the MDAC output voltage is still between-1V and 1V after multiplying by 15.4 times of gain, and the buckend ADC operates normally.

Therefore, compared with the prior art, according to the readout circuit of the photoelectric imaging array, the readout circuit calibration method and the readout circuit calibration system provided by the embodiment, whether the output of the backhaul ADC is saturated or not is judged by adding a saturation detection circuit, when the saturation detection circuit detects that the output of the backhaul ADC is saturated, the DAC input is configured through the SPICFG, so that the output voltage of the integrator is equal to the SUBADC reference voltage, the proportional deviation between the sampling capacitor in the integrator and the feedback capacitor in the MDAC is detected, the SUBADC reference voltage is automatically adjusted, and the purpose of ensuring the normal operation of the whole signal link is achieved.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A method of calibrating a readout circuit of a photoelectric imaging array, comprising the steps of:

s1, carrying out state detection on a backskend ADC output value under the current SUBADC reference voltage;

s2, when the backskend ADC output value is an abnormal value, adjusting the SUBADC reference voltage through an internal register to obtain an adjusted backskend ADC output value, updating the backskend ADC output value by using the adjusted backskend ADC output value, and executing S1; and outputting a normal value of the backskend ADC when the backskend ADC output value is not an abnormal value.

2. The method of calibrating a readout circuit of a optoelectronic imaging array of claim 1, wherein the background ADC output value is an outlier, comprising:

when the backskend ADC input value is larger than the maximum input threshold value of the backskend ADC, the backskend ADC output value is 1;

when the backskend ADC input value is less than the backskend ADC minimum input threshold value, the backskend ADC output value is 0.

3. A method of calibrating a readout circuit of a photoelectric imaging array according to claim 2, wherein:

the accuracy of the SUBADC is 5 bits.

4. A method of calibrating a readout circuit of a optoelectronic imaging array according to claim 3, wherein:

the backskend ADC maximum input threshold is 2V.

5. A method of calibrating a readout circuit of a photoelectric imaging array according to claim 3, wherein:

the minimum input threshold of the backskend ADC is-2V.

6. A system for calibrating readout circuitry of a photoelectric imaging array, comprising:

the detection module is used for S1, carrying out state detection on a back ADC output value under the current SUBADC reference voltage;

the configuration module is used for S2. When the backskend ADC output value is an abnormal value, the SUBADC reference voltage is adjusted through an internal register to obtain an adjusted backskend ADC output value, the backskend ADC output value is updated by the adjusted backskend ADC output value, and S2 is executed; and outputting a normal value of the backskend ADC when the backskend ADC output value is not an abnormal value.

7. A calibration system for a readout circuit of a photoimaging array as set forth in claim 6, wherein:

the configuration module comprises an internal register and a DAC buffer;

the input end of the internal register is connected with the output end of the detection module;

the input end of the DAC buffer is connected with the output end of the internal register;

and the output end of the DAC buffer is connected with the input end of the integrator through a charge injection capacitor.

8. A system for calibrating readout circuitry for a photoimaging array according to claim 7, wherein:

the DAC buffer comprises a DAC circuit and a buffer driving circuit connected with the output end of the DAC circuit;

the DAC circuit is connected with the internal register;

and the output end of the buffer driving circuit is connected with the charge injection capacitor.

9. A readout circuit for a photoelectric imaging array, comprising a readout circuit calibration system for a photoelectric imaging array according to any one of claims 6 to 8, wherein:

the circuit also comprises a PIPELINE ADC circuit, wherein the output end of a backup ADC in the PIPELINE ADC circuit is connected with the input end of the detection circuit.

10. A readout circuit for a photoelectric imaging array according to claim 9, wherein:

the back ADC is a successive approximation ADC.

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