CN115238635A

CN115238635A - Integrated circuit layout construction method convenient for multiple Metal-fix

Info

Publication number: CN115238635A
Application number: CN202210937484.7A
Authority: CN
Inventors: 卢君明; 洪享
Original assignee: Shanghai Kingchip Electronics Technology Co ltd
Current assignee: Shanghai Kingchip Electronics Technology Co ltd
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2022-10-25

Abstract

The invention is suitable for the field of integrated circuits, and provides an integrated circuit layout construction method convenient for multiple Metal-fix, which specifically comprises the following steps: and (4) at least two times of connecting all the layers of the top layer Metal to the bottom layer Metal in series, and reserving a width meeting the disconnection relation on each Metal layer. The integrated circuit layout structure obtained by the method can support multiple times of modification on the same node, can reduce modification levels as much as possible, and is worthy of popularization.

Description

Integrated circuit layout construction method convenient for multiple Metal-fix

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to an integrated circuit layout construction method convenient for multi-time Metal-fix.

Background

At present, integrated circuit chips are widely applied in various fields of electronic products, compared with discrete device circuits, the circuits of the integrated circuit chips are relatively difficult to modify, and if the functions or the performance of products do not meet the design requirements or the definition of the functions of the products needs to be modified, the plates are made again and the plates are reflowed. The cost for manufacturing the mask re-tape-out is high, the product research and development cost is increased, and the product research and development period is prolonged due to the fact that the mask re-tape-out is performed for many times.

In the modification of integrated circuit chips, there is a modification method called Metal-fix, which is suitable for achieving the function or performance of the product by a connection modification mode on a certain Metal or Via layer without modifying the size and characteristics of the bottom layer device. The method can only manufacture a plurality of Metal or Via layers which need to be modified without re-manufacturing the whole set of mask plates. The modification method can greatly save the cost of a complete set of mask plates, and can switch to a newly modified mask plate in the middle of the original tape-out, thereby shortening the tape-out period of research and development.

In order to add a modification expectation to possible reticle revisions, some expected modification points and modification schemes need to be added when the first layout design is carried out, which is also the most common design idea in the integrated circuit design tape-out at present. However, the existing layout structure of the modification point is generally only suitable for single modification, and when the same node is modified for multiple times, the design is lacked, so that the hierarchy of the modification layer which is additionally added is possibly needed.

Therefore, in view of the above situation, there is an urgent need to develop a method for constructing an integrated circuit layout that facilitates multiple Metal-fix operations, and can support multiple modifications on the same node, and reduce modification levels as much as possible to overcome the shortcomings in the current practical application.

Disclosure of Invention

The invention aims to provide an integrated circuit layout construction method convenient for Metal-fix for multiple times, and aims to solve the problem that the layout structure of the existing modification point is generally only suitable for single modification, and the additional modification of the layout hierarchy is possibly required due to the lack of design when the same node is modified for multiple times.

The invention is realized in this way, a method for constructing integrated circuit layout convenient for multiple Metal-fix, which specifically comprises: and connecting all the layers of the top layer Metal to the bottom layer Metal at least twice, and reserving a width meeting the disconnection relation on each Metal layer.

In the further technical scheme, when Metal-fix is carried out, the region of the same Metal layer of the modified signal far away from the signal outflow end is selected.

The further technical scheme is that the reserved width on the Metal layer is used for meeting the design rule of DRC when Metal modification connection is carried out.

In a further aspect, the design rules for DRC include minimum spacing and/or minimum width of the wrap Via.

In a further technical scheme, the constructed integrated circuit layout is in a positive V-shaped, inverted V-shaped, positive U-shaped or inverted U-shaped structure.

The integrated circuit layout construction method convenient for multi-time Metal-fix provided by the invention can be used for carrying out multi-time Metal-fix when a circuit is modified, thereby achieving the purposes of saving plate making cost and reducing the research and development period of a product; the obtained integrated circuit layout structure can support multiple times of modification on the same node, can reduce modification levels as much as possible, and is worthy of popularization.

Drawings

Fig. 1 is a schematic top view of a positive V-shaped structure layout provided in an embodiment of the present invention;

FIG. 2 is a schematic front cross-sectional view of FIG. 1;

FIG. 3 is a schematic diagram of FIG. 1 with a first Metal-fix (B disconnected A and then connected C);

FIG. 4 is a schematic front cross-sectional view of FIG. 3;

FIG. 5 is a schematic diagram of FIG. 3 with a second Metal-fix (B disconnected C and then connected D);

FIG. 6 is a schematic front cross-sectional view of FIG. 5;

fig. 7 is a schematic front view cross-sectional view of an inverted V-shaped structure layout provided in an embodiment of the present invention;

fig. 8 is a schematic front view cross-sectional view of an inverted U-shaped structure layout according to an embodiment of the present invention;

fig. 9 is a schematic front view cross-sectional view of a layout of a positive U-shaped structure according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

Specific implementations of the present invention are described in detail below with reference to specific embodiments.

As shown in fig. 1 to 9, a layout construction method for an integrated circuit convenient for multiple Metal-fix according to an embodiment of the present invention includes:

all layers of a top layer Metal to a bottom layer Metal (namely, a Metal1 layer, M1) are connected in series at least twice, namely, all layers of the top layer Metal to the bottom layer Metal are used; meanwhile, the width meeting the disconnection relation is reserved on each Metal layer, and the design rules of DRC (design control data) such as the minimum spacing and the minimum width of a package Via are met when the Metal is modified and connected.

Furthermore, when the Metal-fix is carried out, the area of the same Metal layer of the modified signal far away from the signal outflow end is preferably selected, and the operation possibility is reserved for carrying out the Metal-fix later.

Furthermore, the integrated circuit layout is a positive V-shaped, inverted V-shaped, positive U-shaped or inverted U-shaped structure, and the like, and the Metal-fix scheme which is changed twice in a single layer can be provided at worst due to the structural characteristics of the several types of layouts.

In the embodiment of the invention, the provided integrated circuit layout construction method convenient for multiple Metal-fix can carry out multiple Metal-fix when modifying the circuit, thereby achieving the purposes of saving plate making cost and reducing the research and development period of products; the obtained integrated circuit layout structure can support multiple times of modification on the same node, can reduce modification levels as much as possible, and is worthy of popularization.

The following description of specific embodiments is made with reference to fig. 1-6.

As shown in fig. 1-2, as a preferred embodiment of the present invention, the integrated circuit layout structure is a multiple Metal-fix integrated circuit layout structure with a positive V-shaped structure, the top-level Metal is Metal4 (i.e., M4), M4, M3, M2, M1, M2, M3, and M4 are connected in series in sequence, and the signal flow is from the left side a end to the right side B end.

In normal operation, the signal flows from the left side a terminal to the right side B terminal in the order of M4 → Via3 → M3 → Via2 → M2 → Via1 → M1 → Via1 → M2 → Via2 → M3 → Via3 → M4, where Via represents a Via hole.

As shown in fig. 3-4, as a preferred embodiment of the present invention, the first time Metal-fix, B signal needs to be disconnected from a signal a and connected to a signal C at M2, and the connection manner of its layout is shown in the figure.

The first time, metal-fix, processes the Metal area of the same level of the signal and selects the side far away from the signal outflow, i.e. selects the left M2 area to cut off and connect out as in fig. 3-4. This operation is such that the input signal C flows to the right B-side end in the order of M2 → Via1 → M1 → Via1 → M2 → Via2 → M3 → Via3 → M4.

As shown in fig. 5-6, as a preferred embodiment of the present invention, the second Metal-fix, B signal needs to be disconnected from the C signal and connected to the signal D at M3, and the connection manner of its layout is shown in the figure.

At this time, the left M3 region is already disconnected from the signal B, and therefore only the right M3 region can be selected.

The second Metal-fix selects the side far away from the signal outflow, i.e. the left M3 region, according to the processing principle, and has been disconnected from the signal B, so that only the right M3 region can be selected, i.e. as shown in fig. 5-6, the right M3 region is selected for disconnection and external connection processing.

This operation is a flow of the input signal D to the right B terminal in the order of M3 → Via3 → M4.

Thereafter, if there is still a Metal-fix requirement, then only single-level Metal modifications that deal with signal connections on M3 or M4 can be processed if the function modification is to be done within a single level.

If there is also a third Metal-fix modification, for example, from the D input signal to the E signal on M2 as the input signal, this can only be done by modifying the two-layer Metal, i.e. D is disconnected on M3, C is disconnected on M2, and then M2 is connected to E.

Other layout structure embodiments are described below in conjunction with fig. 7-9.

As shown in fig. 7-9, as a preferred embodiment of the present invention, inverted V-shaped, inverted U-shaped, and regular U-shaped layout structures are respectively given, the rules when performing Metal-fix are the same as those of the regular V-shaped layout structure, and the region far from the signal outflow end of the same Metal layer of the modified signal is preferentially selected, and the concatenation mode may be the mode shown in fig. 7-9, without limitation and repeated description.

In addition, the inverted U-shaped layout structure is particularly suitable for the signal connection of the spare gate cells added in the APR, because the intention of the placement of the cells is to be reserved for the subsequent circuit modification application. An inverted U-shaped layout structure is placed on a port of the spark gate cell, so that the expected function can be realized by modifying with the minimum level when a circuit is modified.

The circuits, electronic components and modules referred to are well within the art of prior art and, needless to say, the present invention is not directed to software or process improvements.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for constructing an integrated circuit layout convenient for multiple Metal-fix is characterized by comprising the following steps:

and (4) at least two times of connecting all the layers of the top layer Metal to the bottom layer Metal in series, and reserving a width meeting the disconnection relation on each Metal layer.

2. The method of claim 1, wherein the same Metal level of the modified signal is selected to be in a region away from the signal egress port during Metal-fix.

3. The method of claim 2, wherein the reserved width at the Metal level is used to satisfy DRC rules when performing Metal modification connection.

4. The method for facilitating multiple Metal-fix integrated circuit layout construction as recited in claim 3, wherein the DRC design rules include a minimum pitch and/or a minimum width of a wrap Via.

5. The method for facilitating multiple Metal-fix integrated circuit layout construction as recited in any of claims 1-4, wherein the integrated circuit layout being constructed is a positive V-shaped, an inverted V-shaped, a positive U-shaped or an inverted U-shaped structure.