CN115237353B - ARM method for inquiring FPGA length register - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
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Abstract
The invention discloses a method for inquiring a length register of an FPGA by ARM, which comprises the following specific steps: step S1: defining DMA LengthA memory write pointer for the register and the RAM length register; step S2: when the descriptor addresses accumulate normally, the ARM reads data from the DMA length register and the RAM register; step S3: when the descriptor address crosses the domain 0 address, the ARM reads data from the DMA length register and the RAM register; the ARM does not execute the data moving operation, keeps the read period and the write period unchanged, does not influence the access efficiency of ARM memory, and the size of the pointed memory space of the ARM descriptor is 2 N (N>=2), effectively solving the problem that memory disorder occurs when descriptor addresses cross domain 0 addresses.
Description
Technical Field
The invention relates to the technical field of data reading, in particular to a method for inquiring a length register of an FPGA by an ARM.
Background
The host computer reads the external data generally by writing the external data into a memory or register, and then reads the data from the memory or register; for example, the application number is 202111604056.4, the invention is an invention patent of a data reading control method, the control module reads the first addresses of M target storage blocks and the block lengths of M target storage blocks in a memory from a head file and stores the first addresses and the block lengths in a first address register and a block length register respectively, wherein M is a positive integer; and the control module reads the data of the M target storage blocks from the memory according to the head addresses of the M target storage blocks and the block lengths of the M target storage blocks. The method is used for flexibly accessing the data in the memory without depending on the micro control unit;
at present, when the upper computer reads the memory or the register, the memory or the register cannot be read continuously, so that the memory of the memory or the register is occupied, for example, external data is written into the ARM, and the upper computer continuously inquires and reads the ARM memory, so that the ARM memory is occupied all the time and cannot perform other works; therefore, the data is required to be read and uploaded to the upper computer through an ARM storage medium for caching the data when the data is inquired; based on the current situation, there is an urgent need to reform the prior art.
Disclosure of Invention
The invention aims to provide a method for inquiring a length register of an FPGA by an ARM, which aims to solve the problems in the background technology.
The invention provides a method for inquiring a length register of an FPGA by ARM, which comprises the following steps:
step S1: defining a DMA length register and a memory write pointer of the RAM length register;
DMA memory write pointer=dma_length_reg, and the number of data bytes written to DMA memory=dma_length_reg_x;
RAM memory write pointer=ram_length_reg, and the number of data bytes written to RAM memory=ram_length_reg_y;
total memory write pointer=dma_length_reg+ram_length_reg, number of data bytes written to total memory=dma_length h_reg_x+ram_length_reg_y; wherein X represents the times of the upper computer inquiring DMA through ARM, Y represents the times of the upper computer inquiring RAM through ARM;
step S2: when the descriptor address normally accumulates, the ARM reads the data from the DMA length register and the RAM register:
ARM judges whether the total write pointer changes or not compared with the previous inquiry in the next inquiry; if the total write pointer is unchanged, indicating that no new data exists, waiting for the next inquiry; if the total write pointer changes, the data amount written into the DMA LENGTH register DMA_Length_REG is judged first, and if the data amount written into the DMA LENGTH register DMA_Length_REG does not change compared with the previous inquiry, the data amount written into the RAM LENGTH register RAM_Length_REG is judged.
Step S3: when the descriptor address crosses the domain 0 address, the ARM reads data from the DMA length register and the RAM register; judging whether the total write pointer changes when the next inquiry is carried out and the total write pointer when the last inquiry is carried out;
if no change exists, indicating that no new data exists, and waiting for the next inquiry;
if the data quantity of the memory written into the DMA length register next time is changed compared with the data quantity of the memory written into the memory last time, the ARM judges whether the data quantity of the memory written into the DMA length register next time is changed or not, if the data quantity of the memory written into the DMA length register is changed, the ARM reads the memory data and waits for the next query; for example, on the n+1th query, the descriptor address crosses the domain 0 address, dma_length_reg_n+1 is necessarily not equal to dma_length_reg_n, and dma_length_reg_n+1< dma_length_reg_n; then the new data is written into the memory, and the ARM read pointer accumulates and reads sequentially.
The invention has the following beneficial effects:
(1) The DMA register and the RAM register synchronously receive externally written data, the maximum value of DMA_LENGTH_REG is 0x1FFF_FFC0, the range of the value of the RAM_LENGTH_REG is 0-63 bytes, namely the maximum value of a write pointer is 0x1FFF_FFFF, and when new data is received again to 64 bytes, the data is accumulated to 0x0000_0000 and accumulated again.
(2) Comparing the next inquiry with the previous inquiry, the invention firstly judges whether the total read pointer changes, then judges whether the data amount written into the DMA length register changes, if the data amount written into the DMA length register changes, the RAM length register does not need to be judged, and if the data amount written into the DMA length register does not change, the data amount written into the RAM length register is judged whether the data amount written into the RAM length register changes;
(3) The data volume written into the FPGA length register is a multiple of 64 bytes, the RAM reads out the data by inquiring the DMA length register, and the RAM reads out the data by inquiring the RAM length register when the data volume of 0-63 bytes is the data volume.
(4) The ARM does not execute the data moving operation, keeps the read period and the write period unchanged, and does not influence the access efficiency of the ARM memory.
(4) The ARM descriptor of the invention points to a memory space with the size of 2 N (N>=2), effectively solving the problem that memory disorder occurs when descriptor addresses cross domain 0 addresses.
Drawings
FIG. 1 is a schematic diagram of an ARM read FPGA length register according to the present invention;
FIG. 2 is a schematic diagram of ARM query of the present invention for a length register of an FPGA;
FIG. 3 is a diagram illustrating a query of a descriptor address according to the present invention across domain 0 addresses.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the present invention without making any inventive effort fall within the scope of the present invention.
Referring to fig. 1, the present invention provides a method for querying an FPGA length register by using an ARM according to the following technical solution, where the FPGA length register includes: a DMA length register and a RAM length register; the external data is firstly input into an FPGA length register, then the upper computer queries the FPGA length register through the ARM, and the data is read out and stored into an ARM memory;
in the embodiment, after the upper computer reads the DMA register and the RAM register through the ARM, the inquiry read data amount needs to be calculated, and in the embodiment, the units of the address and the length are calculated according to 1byte, namely the data bit width of 1 address is 1 byte; the data length is 1, representing 1byte, and the method is as follows:
step S1: defining a DMA length register and a memory write pointer of the RAM length register;
DMA memory write pointer=dma_length_reg, and the number of data bytes written to DMA memory=dma_length_reg_x;
RAM memory write pointer=ram_length_reg, and the number of data bytes written to RAM memory=ram_length_reg_y;
total memory write pointer=dma_length_reg+ram_length_reg, number of data bytes written to total memory=dma_length h_reg_x+ram_length_reg_y; wherein X represents the times of the upper computer inquiring DMA through ARM, Y represents the times of the upper computer inquiring RAM through ARM;
in the embodiment, the DMA register and the RAM register synchronously receive externally written data, the dma_length_reg is 0x1fff_ffc0 at maximum, the ram_length_reg has a value range of 0-63 bytes, namely the write pointer is 0x1fff_ffff at maximum, and when new data is received again to 64 bytes, the data is accumulated to 0x0000_0000 and accumulated again; the read pointer is calculated by ARM according to the byte number of the uploading upper computer, and the maximum value of the read pointer is not more than the total memory write pointer.
Referring to fig. 2, step S2: when the descriptor address normally accumulates, the ARM reads the data from the DMA length register and the RAM register:
when the number of data bytes written into the memory of the DMA LENGTH register is DMA_LENGTH_REG_1 and the number of bytes of the memory in the RAM LENGTH register is RAM_LENGTH_REG_1, the ARM reads the number of bytes of the DMA_LENGTH_REG_1 from the memory of the DMA LENGTH register, reads the number of bytes of the RAM_LENGTH_REG_1 from the RAM LENGTH register, and the maximum number of read bytes of the read pointer can be increased to DMA_LENGTH_REG_1+RAM_LENGTH_REG_1.
When the second inquiry is performed, when the number of bytes of data written into the memory of the DMA LENGTH register is DMA_LENGTH_REG_2 and the number of bytes written into the memory of the RAM LENGTH register is RAM_LENGTH_REG_2; judging whether the total write pointer changes or not in the second query compared with the first query;
if the total write pointer is unchanged, the new data is not available, and the next query is waited.
If the total write pointer changes, firstly judging the data quantity written into a DMA LENGTH register DMA_Length_REG;
ARM judges whether the data byte number DMA_Length_REG_2 written into the memory of the DMA LENGTH register in the second inquiry and the data byte number DMA_Length_REG_1 written into the memory of the DMA LENGTH register in the first inquiry are changed or not; if the DM a_length_reg_2 is changed compared with the dma_length_reg_1, it indicates that new data is written into the DMA LENGTH register memory, the ARM read pointer accumulates and sequentially reads, and reads the data in the DMA LENGTH register memory, and the number of data read by the DMA LENGTH register memory is as follows: the new DMA LENGTH register memory write pointer minus the last read pointer data byte count, i.e., dma_length_reg_2- (dma_length_reg_1+ram_length_reg_1);
if the DMA_LENGTH_REG_2 is unchanged compared with the DMA_LENGTH_REG_1, indicating that the memory of the DMA LENGTH register has no new data, waiting for the next inquiry, and judging the data quantity of the RAM LENGTH register RAM_LENGTH_REG;
if the number of the data bytes RAM_Length_REG_2 written into the RAM LENGTH register memory during the second query is equal to the number of the data bytes RAM_Length_REG_1 written into the RAM LENGTH register memory during the first query, the result shows that no new data is written into the RAM LENGTH register memory, and the memory does not need to be read;
if the number of data bytes ram_length_reg_2 written into the RAM LENGTH register memory during the second query is greater than the number of data bytes ram_length_reg_1 written into the RAM LENGTH register memory during the first query, it indicates that new data is written into the RAM LENGTH register memory, the ARM read pointer accumulates and sequentially reads, and the number of data read by the RAM is: ram_length_reg_2-ram_length_reg_1.
If the number of data bytes RAM_Length_REG_2 written into the RAM LENGTH register memory during the second query is equal to 0, the data in the RAM LENGTH register memory reaches the updated value, the updated value is updated to 0, no new data is written into the RAM, and the memory does not need to be read.
Referring to fig. 3, step S3: when the descriptor address crosses the domain 0 address, the ARM reads data from the DMA length register and the RAM register; because of the bit width, the condition of crossing the 0 point address can certainly occur in the query process, so that the condition that the read pointer is larger than the write pointer can occur, and the query condition is not satisfied, so that calculation is needed to perform conversion;
when the N-th inquiry is performed, if the number of bytes of data written into the memory is DMA_LENGTH_REG_N, the number of bytes of the memory in the RAM is RAM_LENGTH_REG_N; the total write pointer is dma_length_reg_n+ram_length_reg_n at this time;
when the n+1th inquiry is performed, if the number of bytes of data written into the memory is DMA_LENGTH_REG_N+1, the number of bytes of the memory in the RAM is RAM_LENGTH_REGN+1; the total write pointer is (dma_length_reg_n+1) + (ram_length_reg_n+1);
judging whether the total write pointer (DMA_LENGTH_REG_N+1) + (RAM_LENGTH_REG_N+1) in the (N+1) th query and the total write pointer in the (N) th query are DMA_LENGTH_REG_N+RAM_LENGTH_REG_N;
if no change exists, indicating that no new data exists, and waiting for the next inquiry;
if there is a change, ARM needs to determine if there is a change in DMA_LENGTH_REG_N+1 compared to DMA_LENGTH_REG_N; if the memory data is changed, reading the memory data and waiting for the next inquiry.
If dma_length_reg_n+1 is not equal to dma_length_reg_n, (if the descriptor address is not equal to the address crossing the field 0, and dma_length_reg_n+1< dma_length_reg_n), it indicates that new data is written in the memory, the ARM read pointer accumulates and reads sequentially, and the number of data read by the memory is: the new memory write pointer, minus the last read pointer, plus the space range of the ARM descriptor, takes the ARM descriptor space size of 512MB as an example in this embodiment, the number of data read from the memory is: dma_length_regn+1- (dma_length_regn+ram_length_regn) +512MB.
In an embodiment, the ARM does not perform data movement operation, because if data movement is performed, a read cycle and a write cycle are increased, which affects the access efficiency of the ARM memory.
In an embodiment, the ARM descriptor points to a memory space size of 2 N (N>=2), if not 2 N A memory violation occurs when the descriptor address crosses the domain 0 address, for example: the ARM descriptor points to a memory space size of 15 (not 2 N ) Since the bit width of the length register of the DMA is 4 from the initial address 0 to the last address 14, the range of addresses written into the DMA length register is: 0000-1111, 16 bytes total, from initial address 0 to last address 15, it can be seen that the descriptor address crosses domain 0 address with a memory disorder compared to initial address 0 to last address 14, so the ARM descriptor points to a memory space size of 2 N (N>＝2)。
Although the present invention has been described with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements and changes may be made without departing from the spirit and principles of the present invention.
Claims (8)
1. A method for an ARM to query an FPGA length register, wherein the FPGA length register comprises: a DMA length register and a RAM length register; the external data is firstly input into an FPGA length register, then the upper computer queries the FPGA length register through the ARM to read out and store the data into an ARM memory, and the method is characterized by comprising the following specific steps of:
step S1: defining a DMA length register and a memory write pointer of the RAM length register;
DMA memory write pointer=dma_length_reg, and the number of data bytes written to DMA memory=dma_length_reg_x;
RAM memory write pointer=ram_length_reg, and the number of data bytes written to RAM memory=ram_length_reg_y;
total memory write pointer=dma_length_reg+ram_length_reg, and number of data bytes written to total memory=dma_length_reg_x+ram_length_reg_y; wherein X is the number of times that the upper computer inquires the DMA through the ARM, and Y is the number of times that the upper computer inquires the RAM through the ARM;
step S2: when the descriptor addresses accumulate normally, the ARM reads data from the DMA length register and the RAM register;
when the number of data bytes written into the memory of the DMA LENGTH register is DMA_LENGTH_REG_1 and the number of bytes of the memory in the RAM LENGTH register is RAM_LENGTH_REG_1, the ARM reads the number of bytes of DM A_LENGTH_REG_1 from the memory of the DMA LENGTH register, reads the number of bytes of RAM_LENGTH_REG_1 from the memory of the RAM LENGTH register, and the maximum read number of bytes of the read pointer is increased to DMA_LENGTH_REG_1+RAM_LENGTH_REG_1;
when the second inquiry is performed, when the number of bytes of data written into the memory of the DMA LENGTH register is DMA_LENGTH_REG_2 and the number of bytes written into the memory of the RAM LENGTH register is RAM_LENGTH_REG_2; judging whether the write pointer of the total memory changes or not when the second query is compared with the first query;
if the total memory write pointer is unchanged, no new data exists, and the next inquiry is waited;
if the total memory write pointer changes, judging the data quantity written into the DMA length register, and judging the data quantity written into the RAM length register;
when ARM judges that the number of data bytes DMA_Length_REG_2 written into the memory of the DMA LENGTH register is changed compared with the number of data bytes DMA_Length_REG_1 written into the memory of the DMA LENGTH register when first query is performed, new data are written into the memory of the DMA LENGTH register, ARM read pointer accumulation sequence is read, and the data in the memory of the DMA LENGTH register are read; and the ARM reads the data quantity from the DMA length register memory as follows: the DMA LENGTH register memory write pointer at the second inquiry minus the read pointer data byte count at the first inquiry, namely DMA_Length_REG_2-DMA_Length_REG_1;
step S3: when the descriptor address crosses the domain 0 address, the ARM reads data from the DMA length register and the RAM register;
when the number of data bytes written into the memory is DMA_LENGTH_REG_N and the number of bytes in the RAM is RAM_LENGTH_REG_N, the total memory write pointer is DMA_LENGTH_REG_N+RAM_LENGTH_REG_N;
when the number of data bytes written into the memory is DMA_LENGTH_REG_N+1 and the number of bytes in the RAM is RAM_LENGTH_REG_N+1, the total memory write pointer is (DMA_LENGTH_REG_N+1) + (RAM_LENGTH_RE G_N+1) in the N+1 th inquiry;
judging whether the total memory write pointer (DMA_LENGTH_REG_N+1) + (RAM_LENGTH_REG_N+1) in the (n+1) th query and the total memory write pointer in the (N) th query are DMA_LENGTH_REG_N+RAM_LENGTH_REG_N;
if no change exists, no new data exists, and the next inquiry is waited;
if the change exists, the ARM judges whether the DMA_LENGTH_REG_N+1 is changed compared with the DMA_LENGTH_REG_N, if the change exists, the ARM reads the memory data and waits for the next inquiry;
when the n+1st inquiry is made, the descriptor address crosses the domain 0 address, the DMA_LENGTH_REG_N+1 is not equal to the DMA_LENGTH_REG_N, and the DMA_LENGTH_REG_N+1< DMA_LENGTH_REG_N; new data are written into the memory, and ARM read pointer accumulation sequence is read;
and the number of data read by the ARM read pointer in the (n+1) th inquiry is as follows: the new memory write pointer, minus the last read pointer, plus the ARM descriptor space range.
2. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: the DMA register and the RAM register synchronously receive externally written data; and, in addition, the method comprises the steps of,
dma_length_reg is at most 0x1fff_ffc0; and, in addition, the method comprises the steps of,
the value range of the RAM_Length_REG is 0-63 bytes, and when new data reaches 64 bytes again, the new data is accumulated to 0x0000_0000 and accumulated again; and, in addition, the method comprises the steps of,
the read pointer is calculated by ARM according to the byte number of the uploading upper computer in a self-accumulation way, and the maximum value of the read pointer is not more than the total memory write pointer.
3. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: the ARM judges that the number of data bytes DMA_LENGTH_REG_2 written into the memory of the DMA LENGTH register in the second inquiry is unchanged compared with the number of data bytes DMA_LENGTH_REG_1 written into the memory of the DMA LENGTH register in the first inquiry, the memory of the DMA LENGTH register has no new data, waits for the next inquiry, and judges the data quantity of the RAM LENGTH register RAM_LENGTH_REG.
4. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: if the number of data bytes ram_length_reg_2 written into the RAM LENGTH register memory during the second query is equal to the number of data bytes ram_length_reg_1 written into the RAM LENGTH register memory during the first query, no new data is written into the RAM LENGTH register memory, and no memory reading is required.
5. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: if the number of data bytes ram_length_reg_2 written into the RAM LENGTH register memory during the second query is greater than the number of data bytes ram_length_reg_1 written into the RAM LENGTH register memory during the first query, new data is written into the RAM LENGTH register memory, the ARM read pointer is sequentially read in an accumulating manner, and the number of data read by the RAM is as follows: ram_length_reg_2-ram_length_reg_1.
6. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: if the number of data bytes RAM_Length_REG_2 written into the RAM LENGTH register memory during the second query is equal to 0, the data in the RAM LENGTH register memory reaches the updated value, the updated value is updated to 0, no new data is written into the RAM, and the memory does not need to be read.
7. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: ARM does not execute the data moving operation, and keeps the read period and the write period unchanged.
8. The method for querying the length register of the FPGA by using the ARM according to claim 1, wherein the method comprises the following steps: the memory space size of the ARM descriptor is pointed to as 2N where N > =2.
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