CN115237242A

CN115237242A - Control method and device

Info

Publication number: CN115237242A
Application number: CN202210772908.9A
Authority: CN
Inventors: 刘澎
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2022-10-25

Abstract

The embodiment of the application discloses a control method, which comprises the following steps: monitoring the load of a processor core set of electronic equipment, wherein the processor core set comprises at least one processor core; adjusting configuration information of the set of processor cores based at least on the load; wherein the processing capabilities of different sets of processor cores are the same or different. The embodiment of the application also discloses a control device.

Description

Control method and device

Technical Field

The present application relates to control technologies in the field of computers, and in particular, to a control method and apparatus.

Background

Intel Speed Selection Technology (SST) is a Central Processing Unit (CPU) power management Technology proposed by Intel; SST technology provides a number of ways to configure CPU frequency ranges and performance allocations. The CPU is divided into two priority groups with different computing capacities by one power management technology, and a user can conveniently divide the two priority groups into the CPUs of the corresponding group to operate according to the service level of the application program. However, since the CPU packet is static, in the case where the CPU load of the high priority group is not full, there may occur a problem that the CPU performance of the low priority group is limited, and thus there is a waste of performance.

Disclosure of Invention

The technical scheme of the application is realized as follows:

a control method, comprising:

monitoring the load of a processor core set of electronic equipment, wherein the processor core set comprises at least one processor core;

adjusting configuration information of the set of processor cores based at least on the load;

wherein the processing capabilities of different sets of processor cores are the same or different.

In the above scheme, adjusting the configuration information of the processor core set based on the load includes:

determining a target processor core in each processor core set at least based on the load of each processor core in each processor core set, and adjusting the target processor core from the processor core set where the target processor core is currently located to another processor core set; and/or the presence of a gas in the gas,

determining a target frequency range of a set of processor cores based at least on a load of each processor core in the set of processor cores, tuning the frequency range of the set of processor cores to the target frequency range.

In the above solution, the determining a target processor core in each processor core set based on at least a load of each processor core in each processor core set includes:

obtaining source information of each processor core, wherein the source information represents processor core set information to which the processor core belongs before last adjustment of a processor core set;

a target processor core in each set of processor cores is determined based on the source information and the load.

In the above solution, adjusting the configuration information of the processor core set based on the load includes at least one of:

determining a first processor core of a first set of processor cores is a first target processor core if the first processor core is from a second set of processor cores and the load of the first processor core is greater than or equal to a first threshold value;

tuning the first processor core to the second set of processor cores, or,

tuning the first processor core to the second set of processor cores and tuning a second target processor core in the second set of processor cores to the first set of processor cores; or the like, or, alternatively,

tuning the first processor core to the second set of processor cores and tuning a third target processor core in a third set of processor cores to the first set of processor cores.

In the above solution, adjusting the configuration information of the set of processor cores based on the load includes at least one of:

if the load of a second processor core in the second processor core set is smaller than or equal to a second threshold value and the duration is larger than or equal to a first duration, determining the second processor core as a second target processor core, and adjusting the second processor core to the first processor core set, or adjusting the second processor core to the first processor core set and adjusting the first target processor core in the first processor core set to the second processor core set;

if a third processor core in the second processor core set is from the first processor core set, the load of the third processor core is less than or equal to a third threshold value, and the duration of the third processor core is greater than or equal to a second duration, the third processor core is determined as a second target processor core, and the third processor core is adjusted to the first processor core set, or the third processor core is adjusted to the first processor core set and the first target processor core in the first processor core set is adjusted to the second processor core set;

if the load of a fourth processor core in the first processor core set is larger than a fourth threshold value and the duration is larger than or equal to a third duration, the fourth processor core is determined as a first target processor core, the fourth processor core is adjusted to the second processor core set, or the fourth processor core is adjusted to the second processor core set and the second target processor core in the second processor core set is adjusted to the first processor core set.

In the above scheme, the method further comprises:

determining a number of processor cores in the first set of processor cores and the second set of processor cores;

determining to tune a first target processor core to a second set of processor cores or to tune the first target processor core to the second set of processor cores and to tune a second target processor core in the second set of processor cores to the first set of processor cores based on the number of processor cores; or the like, or, alternatively,

determining to tune a second target processor core to the first set of processor cores based on the number of processor cores, or tuning the second processor core to the first set of processor cores and tuning a first target processor core of the first set of processor cores to the second set of processor cores.

In the above solution, the adjusting the configuration information of the set of processor cores based on at least the load includes at least one of:

adjusting configuration information of the set of processor cores based on the changing information of the load;

obtaining power supply information of electronic equipment, and adjusting configuration information of the processor core set based on the power supply information and the load;

obtaining a configuration instruction acting on an electronic device, and adjusting configuration information of the processor core set based on the configuration instruction and the load;

task change information of the electronic equipment is obtained, and configuration information of the processor core set is adjusted based on the task change information and the load.

In the foregoing solution, adjusting the configuration information of the processor core set based on the load change information includes:

if the load of a fifth processor core in the first processor core set is increased from a fifth threshold value to a sixth threshold value, adjusting the fifth processor core to the second processor core set and/or increasing the frequency range of the first processor core set; or the like, or a combination thereof,

if the load of a sixth processor core in the second processor core set is reduced from the seventh threshold value to the eighth threshold value, the sixth processor core is adjusted to the first processor core set and/or the frequency range of the second processor core set is reduced.

In the foregoing solution, adjusting the configuration information of the processor core set based on the power information and the load includes:

obtaining power supply information and/or power receiving information of an electronic device, and adjusting at least one of a target processor core position, a processor core number or a frequency range of a processor core set in the processor core set based on at least one of the power supply information and the power receiving information and the load.

A control device, comprising:

the monitoring module is used for monitoring the load of a processor core set of the electronic equipment, wherein the processor core set comprises at least one processor core;

a processing module to adjust configuration information of the set of processor cores based at least on the load;

An electronic device, the electronic device comprising: a processor, a memory, and a communication bus;

the communication bus is used for realizing communication connection between the processor and the memory;

the processor is used for executing the control program in the memory to realize the steps of the control method.

A computer-readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the steps of the above-described control method.

The control method and the control device provided by the embodiment of the application can monitor the load of the processor core set of the electronic equipment, and adjust the configuration information of the processor core set at least based on the load, and the processing capacities of different processor core sets are the same or different, so that the configuration information of the processor core set can be dynamically adjusted according to the load of the processor cores in the processor core set, the grouping of the processor cores is not always unchanged, the problem that the performance of the CPU of a low-priority group is limited when the load of the CPU of a high-priority group is not full in the power management technology in the related technology is solved, and the performance of the CPU is ensured.

Drawings

Fig. 1 is a schematic flowchart of a control method according to an embodiment of the present application;

fig. 2 is a schematic flow chart of another control method provided in the embodiment of the present application;

fig. 3 is a schematic flowchart of another control method provided in an embodiment of the present application;

fig. 4 is a schematic flowchart of a control method according to another embodiment of the present application;

FIG. 5 is a schematic flow chart diagram of another control method provided in another embodiment of the present application;

fig. 6 is a schematic flowchart of another control method according to another embodiment of the present application;

fig. 7 is a schematic structural diagram of a control device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

An embodiment of the present application provides a control method, which is applied to an electronic device and is shown in fig. 1, and the method includes the following steps:

step 101, monitoring the load of a processor core set of an electronic device.

Wherein, the processor core set comprises at least one processor core.

In this embodiment, a processor core may refer to a CPU core, a Graphics Processing Unit (GPU) core, even a Data Processing Unit (DPU) core, a Video Processing Unit (VPU) core, and so on, that is, a processor core set may refer to a CPU core set, a GPU core set, or a set of a CPU core and a GPU core; the processor core set may refer to a set of a plurality of CPU cores in one CPU in the electronic device, or may refer to a set formed by grouping cores of a plurality of CPUs in the electronic device. Furthermore, the types of processor cores in different sets of processor cores are different.

Step 102, adjusting configuration information of a set of processor cores based at least on load.

In the embodiment of the present application, in addition to considering the load of the processor core set when adjusting the configuration information of the processor core set, specific requirements of a user (i.e., user intervention), power supply parameters of the electronic device, requirements of a corresponding task (e.g., task requirement efficiency) and the like may also be combined. In one possible implementation, the configuration information may include the frequency, type, number, etc. of the set of processor cores.

It should be noted that, when the configuration information mainly includes the number, the type, and the frequency, the processing capabilities of the processor core sets may be the same because of the three factors of the number, the type, and the frequency. Of course, the processing power of different sets of processor cores may also be different.

The control method provided by the embodiment of the application can monitor the load of the processor core set of the electronic equipment, and adjust the configuration information of the processor core set at least based on the load, wherein the processing capacities of different processor core sets are the same or different, so that the configuration information of the processor core set can be dynamically adjusted according to the load of the processor cores in the processor core set, the grouping of the processor cores is not always unchanged, the problem that the performance of a CPU (and/or a GPU) of a low-priority group is limited when the load of the CPU of the high-priority group is not full in the power management technology in the related technology is solved, and the performance of the CPU is ensured.

Based on the foregoing embodiments, an embodiment of the present application provides a control method, as shown in fig. 2, including the following steps:

step 201, the electronic device monitors the load of a processor core set of the electronic device.

Wherein, the processor core set comprises at least one processor core.

After step 201, step 202 or step 203 may be executed, or steps 202 to 203 may be executed (shown as execution 202 to 203 in fig. 2).

Step 202, the electronic device determines a target processor core in each processor core set at least based on the load of each processor core in each processor core set, and transfers the target processor core from the processor core set where the target processor core is currently located to another processor core set.

In this embodiment of the present application, the target processor core may be a processor core whose load determined from the respective processor core sets satisfies the target load condition according to the load of each processor core; in one possible implementation, the target load condition may refer to the load being the largest, or the load being the smallest; that is, the target processor core may be the most or least loaded processor core of the set of processor cores.

It should be noted that, in the process of implementing tuning of the target processor core from the currently located processor core set to another processor core set, two different processor core sets where processor core tuning occurs may be paired tuned processor cores; of course, the processor cores may be swapped instead of being paired. That is, when a target processor core in the processor core set A1 is tuned to the processor core set A2, a target processor core in the processor core set A2 is also tuned to the processor core set A1; of course, only one target processor core in the processor core set A1 may be tuned to the processor core set A2, but no corresponding target processor core in the processor core set A2 is tuned to the processor core set A1.

Wherein, the step 202 of determining the target processor core in each processor core set based on at least the load of each processor core in each processor core set may be implemented by:

in step 202a, the electronic device obtains source information for each processor core.

Wherein the source information characterizes processor core set information to which the processor core belongs prior to a last processor core set adjustment.

In an embodiment of the present application, the source information of each processor core may include frequency information of a set of processor cores to which the processor core belongs before the last adjustment of the set of processor cores.

Step 202b, the electronic device determines a target processor core in each processor core set based on the source information and the load.

In the embodiment of the present application, when determining the target processor core, the target processor core may be selected from each set of processor cores by combining the frequency before the processor core and the load of the processor core. That is, the frequency before the target processor core must satisfy a certain condition, and the load of the target processor core must also satisfy a certain condition.

Step 203, the electronic device determines a target frequency range of the target processor core set based on at least the load of each processor core in the processor core set, and adjusts the frequency range of the processor core set to the target frequency range.

In the embodiment of the application, the frequency range of the processor core set can be adjusted according to the load of each processor core in the processor core set. In a feasible implementation manner, the average load of the processor core set may be calculated based on the load of each processor core, and if the average load is greater than a preset load threshold, the load of the processor core set is considered to be too large, and in order to ensure the processing efficiency of data, the processor core set may be subjected to frequency increase processing, that is, it is determined that the target frequency range is greater than the current frequency of the processor core set; if the average load is less than a preset load threshold, the load of the processor core set is considered to be too low, and in order to avoid waste of resources, the processor core set may be subjected to frequency reduction processing, that is, it is determined that the target frequency range is less than the current frequency of the processor core set.

Of course, the frequency range of the processor core set may also be adjusted according to the load of each processor core in the processor core set and the number of the processor cores included in the processor core set; if the number of the processor cores with the loads larger than a preset load threshold value in the processor core set is large, the frequency of the processor core set needs to be increased at the moment, namely, the target frequency range is determined to be larger than the current frequency of the processor core set, and the processing efficiency is ensured. If the number of the processor cores with the loads smaller than a preset load threshold value in the processor core set is large, the frequency of the processor core set needs to be reduced at the moment, namely, the target frequency range is determined to be smaller than the current frequency of the processor core set, and the effective utilization of resources is ensured. It should be noted that, for the explanation of the same or related steps as those in the other embodiments, reference may be made to the explanation in the other embodiments, and details are not described here.

The control method provided by the embodiment of the application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set, the grouping of the processor cores is not invariable all the time, the problem that the performance of the CPU of a low priority group is limited when the CPU load of a high priority group is not full in the power management technology in the related technology is solved, and the performance of the CPU is ensured.

Based on the foregoing embodiments, an embodiment of the present application provides a control method, as shown in fig. 3, the method includes the following steps:

step 301, the electronic device monitors a load of a processor core set of the electronic device.

Wherein, the processor core set comprises at least one processor core.

At step 302, if a first processor core of the first set of processor cores is from the second set of processor cores and its load is greater than or equal to a first threshold, the electronic device determines that the first processor core is a first target processor core.

Wherein the processing capabilities of the first set of processor cores and the second set of processor cores are the same or different.

In this embodiment, the first set of processor cores may include a plurality of processor cores that are less frequent and correspond to a low priority group of processor cores; the second set of processor cores may include a plurality of processor cores having a higher frequency and corresponding to a higher priority group of processor cores. The first processor core in the first processor core set is called from the second processor core set, which indicates that the priority of the first processor core before being called is high priority, the current priority is low priority, and the current load of the first processor core is greater than or equal to the first threshold, and at this time, the frequency of the first processor core needs to be readjusted. It should be noted that the first threshold may be a load threshold preset according to historical data. In one possible implementation, the first threshold may be 10%, as shown in fig. 4, if the first processor core is originally (before adjusting the frequency) a high priority group and currently belongs to a low priority group, when the load is greater than or equal to 10%, any one of the following steps 303 to 305 may be performed; fig. 4 illustrates the execution of step 304.

Wherein, after the step 302, any one of the steps 303 to 305 may be executed.

Step 303, the electronic device tunes the first processor core to the second processor core set.

In the embodiment of the application, the first processor core can be adjusted to the second processor core set with a frequency larger than that of the first processor core set, and a second target processor core in the second processor core set is not required to be adjusted to the first processor core set correspondingly.

Step 304, the electronic device tunes the first processor core to the second set of processor cores, and tunes a second target processor core in the second set of processor cores to the first set of processor cores.

In the embodiment of the application, the first processor core is adjusted to the second processor core set B2 with the frequency larger than that of the first processor core set B1, and meanwhile, the second target processor core in the second processor core set B2 is adjusted to the first processor core set B1 with the lower frequency. It should be noted that the second target processor core may be the least loaded processor core in the second set of processor cores.

Step 305, the electronic device tunes the first processor core to the second set of processor cores and tunes a third target processor core of the third set of processor cores to the first set of processor cores.

And the processing capacities of the first processor core set, the second processor core set and the third processor core set are the same or different.

In this embodiment, the first processor core is tuned to a second set of processor cores having a frequency greater than that of the first set of processor cores, so that a denomination of a tunable processor core is available in the first set of processor cores, and a third target processor core in another third set of processor cores can be tuned to the first set of processor cores. It should be noted that the frequency of the third set of processor cores may be greater than the frequency of the first set of processor cores, or may be less than the frequency of the first set of processor cores.

It should be noted that, in this embodiment, because the first processor core is initially at a high priority and is currently at a low priority, when the load of the first processor core is greater than or equal to 10%, it is indicated that the tasks that the first processor core needs to process become more, and at this time, in order to ensure the processing efficiency, the priority of the first processor core may be adjusted back to the original high priority.

Based on the foregoing embodiment, in other embodiments of the present application, as shown in fig. 5, any one of steps 306 to 308 may be performed after step 302;

step 306, if the load of the second processor core in the second processor core set is less than or equal to the second threshold and the duration is greater than or equal to the first duration, the electronic device determines the second processor core as a second target processor core and adjusts the second processor core to the first processor core set, or adjusts the second processor core to the first processor core set and adjusts the first target processor core in the first processor core set to the second processor core set.

In this embodiment, the second processor in the second processor core set B2 may be always in the second processor core set, that is, the second processor core is in the high priority group both originally (i.e., before adjusting the frequency) and currently. In a possible implementation manner, the second threshold may be 5%, the first duration is t1, and as shown in fig. 4, when the load of the second processor core in the second set of processor cores B2 is less than or equal to 5%, and the duration of the load being less than or equal to 5% is greater than or equal to t1, the second processor core is considered to be the second target processor core whose priority needs to be adjusted; at this time, the second processor core may be downgraded, i.e., the second processor core is adjusted to the first set of processor cores B1 with lower priority. Alternatively, after the second processor core is adjusted to the first processor core set B1 with lower priority, the first target processor core in the first processor core set B1 can be adjusted to the second processor core set B2 at the same time because a denomination is vacated in the second processor core set.

It should be noted that, in this embodiment, because the initial priority and the current priority of the second processor core are both high priorities, when the load of the second processor core is less than 5%, in order to ensure the maximum utilization rate of resources and avoid resource waste, the priority of the second processor core may be adjusted to a low priority.

And 307, if a third processor core in the second processor core set is from the first processor core set, the load of the third processor core is less than or equal to a third threshold value, and the duration of the third processor core is greater than or equal to a second duration, the electronic device determines the third processor core as a second target processor core and adjusts the third processor core to the first processor core set, or adjusts the third processor core to the first processor core set and adjusts the first target processor core in the first processor core set to the second processor core set.

In this embodiment, a third processor core in the second set of processor cores is tuned from the first set of processor cores, indicating that the third processor core was a low priority group prior to tuning and is currently a high priority group. In a possible implementation manner, the third threshold may be 50%, the second duration is t2, and as shown in fig. 4, when the load of the third processor core in the second set of processor cores B2 is less than or equal to 50% (i.e., the current load is less than half), and the duration of the load less than or equal to 50% is greater than or equal to t2, the third processor core is considered to be the second target processor core whose priority needs to be adjusted; at this time, the third processor core may be downgraded, i.e., the third processor core is tuned to the first set of processor cores B1 with lower priority. Alternatively, after the third processor core is adjusted to the first processor core set B1 with lower priority, the first target processor core in the first processor core set B1 can be adjusted to the second processor core set B2 at the same time because a denomination is vacated in the second processor core set.

It should be noted that, in this embodiment, because the initial priority of the third processor core is the low priority, when the load of the third processor core is less than half of the full load, the priority of the third processor core may be adjusted back to the original low priority in order to avoid the waste of resources.

Step 308, if the load of the fourth processor core in the first processor core set is greater than a fourth threshold and the duration is greater than or equal to a third duration, the electronic device determines the fourth processor core as the first target processor core, and tunes the fourth processor core to the second processor core set, or tunes the fourth processor core to the second processor core set and tunes the second target processor core in the second processor core set to the first processor core set.

In this embodiment, the fourth processor core may be always in the first set of processor cores, that is, the fourth processor core originally and now belongs to the low priority group; in one possible implementation, the fourth threshold may be 100%, the third duration is t3, and as shown in fig. 4, when the load of the fourth processor core in the first set of processor cores B1 is greater than or equal to 100% (i.e., the current load is already full), and the duration of the full load is greater than or equal to t3, the fourth processor core is considered to be the first target processor core whose priority needs to be adjusted; at this time, the fourth processor core may be upgraded, that is, the fourth processor core is moved to the second processor core set B2 with a higher priority. Alternatively, after the fourth processor core is adjusted to the second set of processor cores B2 with higher priority, the second target processor core in the second set of processor cores B2 may be adjusted to the first set of processor cores B1 at the same time because a denomination is vacated in the first set of processor cores B1.

It should be noted that, in this embodiment, since the fourth processor core originally and currently belongs to the low priority, when the load of the fourth processor core is full, in order to ensure that the task can be successfully and timely processed, the priority of the fourth processor core may be upgraded to the high priority.

In other embodiments of the present application, the second target processor core may be determined based on the load of the processor cores in the second set of processor cores, a specific set processor core, or whether an over-grouping switching or frequency switching occurs. Wherein, exchanging the frequency refers to exchanging the frequency of the processor core set.

In addition, as shown in fig. 4, when performing the priority downgrading or upgrading processing on the processor cores, the processor cores that need to be downgraded or upgraded are added into the corresponding downgraded list or upgraded list, and then the downgraded list or upgraded list is subjected to the corresponding downgrading processing or upgrading processing on the processor cores in the downgraded queue or upgraded queue according to the principle of "first in first out, then last out" of the queue. In a feasible implementation manner, when neither the downgrade list nor the upgrade list is empty, the downgrade processing and the upgrade processing can be performed at the same time; when the promotion list is empty and the demotion list is not empty, demotion processing may be performed.

Based on the foregoing embodiments, in other embodiments of the present application, the method may further include the following steps:

step 309, the electronic device determines the number of processor cores in the first set of processor cores and the second set of processor cores.

Wherein step 309 may be followed by an option to perform step 310 or step 311.

In step 310, the electronic device determines to adjust the first target processor core to the second set of processor cores based on the number of processor cores, or adjust the first target processor core to the second set of processor cores and adjust the second target processor core in the second set of processor cores to the first set of processor cores.

In step 311, the electronic device determines to adjust the second target processor core to the first set of processor cores based on the number of processor cores, or adjust the second processor core to the first set of processor cores and adjust the first target processor core in the first set of processor cores to the second set of processor cores.

In this embodiment of the application, only when the number of processor cores in the first processor core set and the second processor core set is not empty, the electronic device may upgrade the priority of the first target processor core and downgrade the priority of the second target processor core.

In other embodiments of the present application, the levels of the sets of processor cores with different priorities have a certain correspondence with tasks in the electronic device.

It should be noted that, for the explanation of the same or related steps as those in the other embodiments, reference may be made to the explanation in the other embodiments, and details are not repeated here.

Based on the foregoing embodiments, an embodiment of the present application provides a control method, as shown in fig. 6, including the following steps:

step 401, the electronic device monitors a load of a processor core set of the electronic device.

Wherein, the processor core set comprises at least one processor core.

It should be noted that any one of steps 402 to 405 may be executed after step 401.

Step 402, the electronic device adjusts configuration information of the processor core set based on the load change information.

In the embodiment of the application, the change information of the load of the processor core set of the electronic device may be monitored, and only the priority of the processor core with the changed load is adjusted correspondingly based on whether the load is increased or decreased, or the frequency of the processor core set to which the processor core with the changed load belongs is adjusted, so that the processor core with the changed load can still process tasks efficiently.

Wherein, step 402 can be implemented by:

step 402a, if the load of a fifth processor core in the first processor core set increases from a fifth threshold to a sixth threshold, the electronic device tunes the fifth processor core to the second processor core set and/or tunes a frequency range of the first processor core set larger.

If the load of a certain processor core (for example, a fifth processor core) in the first set of processor cores is increased, the fifth processor core may be adjusted to the second set of processor cores with higher priority, or the frequency range of the first set of processor cores is increased. Of course, it is also possible to increase the frequency range of the first set of processor cores while tuning the fifth processor core to the second set of processor cores having a higher priority. When the frequency range of the first set of processor cores is increased, the load of other processor cores in the first set of processor cores may also be increased.

Step 402b, if the load of the sixth processor core in the second processor core set is reduced from the seventh threshold value to the eighth threshold value, the electronic device adjusts the sixth processor core to the first processor core set and/or adjusts the frequency range of the second processor core set.

If the load of a certain processor core (for example, the sixth processor core) in the second set of processor cores is reduced, the sixth processor core may be adjusted to the first set of processor cores with lower priority, or the frequency range of the second set of processor cores is reduced. Of course, it is also possible to turn the sixth processor core to the lower priority first set of processor cores while reducing the frequency range of the second set of processor cores. It should be noted that when the frequency range of the second set of processor cores is reduced, the load of other processor cores in the second set of processor cores may also be reduced.

In step 403, the electronic device obtains power information of the electronic device, and adjusts configuration information of the processor core set based on the power information and the load.

In the embodiment of the present application, the power supply information may include power supply information of the electronic apparatus and/or power receiving information of the electronic apparatus.

Wherein, step 403 can be implemented by:

in step 403a, the electronic device obtains power supply information and/or power receiving information of the electronic device.

In step 403b, the electronic device adjusts at least one of a target processor core location within the set of processor cores, a number of processor cores, or a frequency range of the set of processor cores based on the load, the at least one of the power supply information, the power receive information, and the target processor core location.

Wherein at least one of a location of a target processor core in the set of processor cores, a number of processor cores, or a frequency range of the set of processor cores may be adjusted based on the power information and the load together. Alternatively, it may be that at least one of a location of a target processor core in the set of processor cores, the number of processor cores, or a frequency range of the set of processor cores is adjusted based on the powered information and the load together; alternatively, at least one of a location of a target processor core in the set of processor cores, a number of processor cores, or a frequency range of the set of processor cores may be adjusted based on the power supply information, the power receiving information, and the load in common.

Step 404, the electronic device obtains a configuration instruction acting on the electronic device, and adjusts configuration information of the processor core set based on the configuration instruction and the load.

The configuration instruction can be an instruction for a user to reconfigure the SST configuration file according to the actual requirement of the user; at this time, the electronic device may obtain relevant configuration information about the SST configuration file based on the configuration instruction, then update the SST configuration file based on the configuration information, and jointly adjust the configuration information of the set of processor cores based on the updated SST configuration file and the load.

Step 405, the electronic device obtains task change information of the electronic device, and adjusts configuration information of the processor core set based on the task change information and the load.

In the embodiment of the present application, because the processor cores in the processor core set are used for processing tasks in the electronic device; at this time, the task change information may refer to change information of a task that the processor core set needs to process. In a possible implementation manner, if the task of the seventh processor core in the first processor core set is increased, the seventh processor core is adjusted to the second processor core set when the load of the seventh processor core is increased, so as to reduce the priority of the seventh processor core; alternatively, if the task of the eighth processor core in the second set of processor cores is reduced, the eighth processor core may be tuned to the first set of processor cores when the load of the eighth processor core is reduced to increase the priority of the eighth processor core.

It should be noted that, for the explanation of the same or related steps as those in the other embodiments, reference may be made to the explanation in the other embodiments, and details are not described here.

Based on the foregoing embodiment, in other embodiments of the present application, the control method may further include the following steps:

a1, the electronic device determines a ninth processor core from the first processor core set based on the load of each processor core in the first processor core set.

And A2, the electronic device determines a tenth processor core from the second processor core set based on the load of each processor core in the second processor core set.

The ninth processor core may be a processor core selected from the first set of processor cores and having a load satisfying a load condition; the tenth processor core may be a processor core selected from the second set of processor cores that has a load that satisfies a load condition. It should be noted that the ninth processor core includes at least one processor core, and the tenth processor core also includes at least one processor core.

And A3, the electronic device determines a fourth processor core set based on the ninth processor core and the tenth processor core.

Wherein the ninth processor core and the tenth processor core may be automatically grouped into a group, resulting in a fourth set of processors.

Based on the foregoing embodiments, embodiments of the present application provide a control device, which may be applied to the control method provided in the embodiments corresponding to fig. 1 to 3 and 5 to 6, and as shown in fig. 7, the device 5 may include: a monitoring module 51 and a processing module 52, wherein:

a monitoring module 51, configured to monitor a load of a processor core set of the electronic device, where the processor core set includes at least one processor core;

a processing module 52 for adjusting configuration information of the set of processor cores based at least on load;

In other embodiments of the present application, the processing module 52 is further configured to perform the following steps:

determining a target processor core in each processor core set at least based on the load of each processor core in each processor core set, and adjusting the target processor core from the processor core set where the target processor core is located to another processor core set; and/or the presence of a gas in the gas,

and determining a target frequency range of the target processor core set at least based on the load of each processor core in the processor core set, and adjusting the frequency range of the processor core set to the target frequency range.

obtaining source information of each processor core, wherein the source information represents processor core set information to which the processor core belongs before last adjustment of the processor core set;

In other embodiments of the present application, the processing module 52 is further configured to perform at least one of the following steps:

if a first processor core in the first processor core set is from the second processor core set and the load of the first processor core is greater than or equal to a first threshold value, determining that the first processor core is a first target processor core;

tuning the first processor core to the second set of processor cores, or,

the first processor core is tuned to the second set of processor cores and a third target processor core in the third set of processor cores is tuned to the first set of processor cores.

if the load of a second processor core in the second processor core set is smaller than or equal to a second threshold value and the duration is longer than or equal to a first duration, determining the second processor core as a second target processor core, and adjusting the second processor core to the first processor core set, or adjusting the second processor core to the first processor core set and adjusting the first target processor core in the first processor core set to the second processor core set;

if a third processor core in the second processor core set is from the first processor core set, the load of the third processor core is smaller than or equal to a third threshold value, and the duration of the third processor core is larger than or equal to a second duration, the third processor core is determined as a second target processor core, and the third processor core is adjusted to the first processor core set, or the third processor core is adjusted to the first processor core set and the first target processor core in the first processor core set is adjusted to the second processor core set;

and if the load of a fourth processor core in the first processor core set is greater than a fourth threshold value and the duration is greater than or equal to a third duration, determining the fourth processor core as a first target processor core, and adjusting the fourth processor core to the second processor core set, or adjusting the fourth processor core to the second processor core set and adjusting the second target processor core in the second processor core set to the first processor core set.

determining to tune the first target processor core to the second set of processor cores or to tune the first target processor core to the second set of processor cores and to tune a second target processor core of the second set of processor cores to the first set of processor cores based on the number of processor cores; or the like, or, alternatively,

based on the number of processor cores, determining to tune a second target processor core to the first set of processor cores, or to tune the second processor core to the first set of processor cores and to tune a first target processor core of the first set of processor cores to the second set of processor cores.

adjusting configuration information of the set of processor cores based on the change information of the load;

obtaining power supply information of the electronic equipment, and adjusting configuration information of the processor core set based on the power supply information and the load;

obtaining a configuration instruction acting on the electronic equipment, and adjusting configuration information of the processor core set based on the configuration instruction and the load;

if the load of a sixth processor core in the second set of processor cores decreases from the seventh threshold value to the eighth threshold value, the sixth processor core is tuned to the first set of processor cores and/or the frequency range of the second set of processor cores is narrowed.

the method includes obtaining power supply information and/or power receiving information of the electronic device, and adjusting at least one of a target processor core position within a set of processor cores, a number of processor cores, or a frequency range of the set of processor cores based on at least one of the power supply information, the power receiving information, and a load.

It should be noted that, in the present embodiment, an interaction process between the modules may refer to an implementation process in the control method provided in the embodiments corresponding to fig. 1 to 3 and 5 to 6, and details are not described here.

The control device provided by the embodiment of the application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set, the grouping of the processor cores is not invariable all the time, the problem that the performance of the CPU of a low priority group is limited when the CPU load of a high priority group is not full in the power management technology in the related technology is solved, and the performance of the CPU is ensured.

Based on the foregoing embodiments, an embodiment of the present application provides an electronic device, which may be applied to the control method provided in the embodiments corresponding to fig. 1 to 3 and 5 to 6, and as shown in fig. 8, the electronic device 6 may include: a processor 61, a memory 62, and a communication bus 63, wherein:

the communication bus 63 is used for realizing communication connection between the processor 61 and the memory 62;

the processor 61 is configured to execute a control program in the memory 62 to implement the following steps:

monitoring the load of a processor core set of the electronic equipment, wherein the processor core set comprises at least one processor core;

adjusting configuration information for a set of processor cores based at least on load;

The electronic device provided by the embodiment of the application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set, the grouping of the processor cores is not invariable all the time, the problem that the performance of the CPU of a low priority group is limited when the CPU load of a high priority group is not full in the power management technology in the related technology is solved, and the performance of the CPU is ensured.

Based on the foregoing embodiments, embodiments of the present application provide a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps of the control method provided by the corresponding embodiments of fig. 1 to 3 and 5 to 6.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.

Claims

1. A control method, comprising:

2. The method of claim 1, wherein adjusting configuration information of the set of processor cores based on the load comprises:

determining a target frequency range of a set of processor cores based at least on a load of each processor core in the set of processor cores, and tuning the frequency range of the set of processor cores to the target frequency range.

3. The method of claim 2, wherein the determining a target processor core in each set of processor cores based at least on a load of each processor core in each set of processor cores comprises:

4. The method of claim 3, wherein adjusting configuration information of the set of processor cores based on the load comprises:

tuning the first processor core to the second set of processor cores, or,

tuning the first processor core to the second set of processor cores and tuning a second target processor core of the second set of processor cores to the first set of processor cores; or the like, or, alternatively,

5. The method of claim 3, wherein adjusting configuration information of the set of processor cores based on the load comprises at least one of:

6. The method of claim 4 or 5, further comprising:

determining to tune a second target processor core to the first set of processor cores or tune the second processor core to the first set of processor cores and tune a first target processor core of the first set of processor cores to the second set of processor cores based on the number of processor cores.

7. The method of any of claims 1 to 5, the adjusting the configuration information of the set of processor cores based at least on the load, comprising at least one of:

8. The method of claim 7, wherein adjusting configuration information of the set of processor cores based on the information of the change in load comprises:

9. The method of claim 7, wherein adjusting configuration information of the set of processor cores based on the power information and the load comprises:

10. A control device, comprising: