CN115225767A - Echo cancellation system and echo cancellation method - Google Patents

Abstract

The present disclosure relates to an echo cancellation system. A digital-to-analog conversion circuit is used for generating an analog transmission signal according to a digital transmission signal. A first echo cancellation circuit is used for generating a first echo cancellation signal according to the digital transmission signal. A processing circuit is used for generating an analog processing signal according to the analog transmission signal, the first echo cancellation signal and a receiving signal. An analog-to-digital conversion circuit is used for generating a digital value according to the analog processing signal and the two slicing levels. A memory circuit is used for storing a lookup table. The lookup table records an offset value corresponding to the digital value. The memory circuit is further configured to generate a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Description

Echo cancellation system and echo cancellation method

Technical Field

The present invention relates to echo cancellation technologies, and in particular, to an echo cancellation system and an echo cancellation method.

Background

As communication technologies have evolved, various types of communication systems have been developed and used in many different applications. In a communication system employing full-duplex (full-duplex) technology, there are transmit signals and receive signals on a pair of transmission lines. When there is a mismatch in the impedances of the two transmission lines or a mismatch in the hybrid integrated architecture of the receiving device, the transmission signal may be introduced into the reception signal and cause echo (echo). In some related techniques, this echo may be cancelled using echo cancellation techniques. However, when the slice level of the analog-to-digital conversion circuit in the communication system is shifted, quantization noise (quantization noise) may become large and affect the signal-to-noise ratio (SNR) of the communication system.

Disclosure of Invention

Some embodiments of the invention relate to an echo cancellation system. The echo cancellation system comprises a digital-to-analog conversion circuit, a first echo cancellation circuit, a processing circuit, an analog-to-digital conversion circuit and a storage circuit. The digital-to-analog conversion circuit is used for generating an analog transmission signal according to a digital transmission signal. The first echo cancellation circuit is used for generating a first echo cancellation signal according to the digital transmission signal. The processing circuit is used for generating an analog processing signal according to the analog transmission signal, the first echo cancellation signal and a receiving signal. The analog-to-digital conversion circuit is used for generating a digital value according to the analog processing signal and two of the plurality of slicing levels. The memory circuit is used for storing a lookup table. The lookup table records an offset value corresponding to the digital value. The memory circuit is further configured to output a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Some embodiments of the invention relate to a method of echo cancellation. The echo cancellation method comprises the following steps: generating an analog transmission signal according to a digital transmission signal through a digital-to-analog conversion circuit; generating a first echo cancellation signal according to the digital transmission signal through a first echo cancellation circuit; generating an analog processing signal by a processing circuit according to the analog transmission signal, the first echo cancellation signal and a receiving signal; generating a digital value according to the analog processing signal and two of the plurality of slice levels by an analog-to-digital conversion circuit; storing a lookup table through a memory circuit and outputting a first output signal according to the digital value and an offset value corresponding to the digital value, wherein the lookup table records the offset value; and updating the offset value in the lookup table according to an error value associated with the first output signal.

In summary, in the echo cancellation system and the echo cancellation method of the present invention, the offset value can be updated according to the corresponding error value. Accordingly, even if the slice level is shifted, the output signal can be maintained at approximately the middle of the two shifted slice levels by the updated offset value. In this way, quantization noise can be minimized and the signal-to-noise ratio of the system can be maintained (or improved).

Drawings

In order to make the aforementioned and other objects, features, and advantages of the present invention comprehensible, embodiments accompanied with figures are as follows:

FIG. 1 is a schematic diagram of an echo cancellation system according to some embodiments of the invention;

fig. 2A is a schematic diagram illustrating the operation of the analog-to-digital conversion circuit when the slice level is not deviated according to some embodiments of the present invention;

fig. 2B is a diagram illustrating the operation of the analog-to-digital conversion circuit when the slice level is deviated according to some embodiments of the present invention;

FIG. 3 is a schematic diagram of a lookup table shown in accordance with some embodiments of the invention;

FIG. 4 is a schematic diagram illustrating signal-to-noise ratios according to some embodiments of the present invention; and

FIG. 5 is a flow chart illustrating a method of echo cancellation according to some embodiments of the invention.

Detailed Description

In the present specification, the term "coupled" is used to refer to "electrically coupled" as well, and the term "connected" is used to refer to "electrically connected". "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

Refer to fig. 1. Fig. 1 is a schematic diagram of an echo cancellation system S1 shown in accordance with some embodiments of the present invention. In some embodiments, the echo cancellation system S1 is applied in an Ethernet (Ethernet) system.

In some embodiments, the echo cancellation system S1 employs Full Duplex (Full-Duplex) technology. That is, the system has a pair of transmission lines, and the two transmission lines carry transmission signals and reception signals, respectively. Taking fig. 1 as an example, the transmission signal of the echo cancellation system S1 is a digital transmission signal TX, and the reception signal of the echo cancellation system S1 is a reception signal RXC.

Taking fig. 1 as an example, the echo cancellation system S1 includes a data transmission circuit 100, an echo cancellation circuit 200, and an echo cancellation circuit 300. The data transmission circuit 100 is coupled to the echo cancellation circuit 200 and the echo cancellation circuit 300.

The data transmission circuit 100 includes a digital-to-analog conversion circuit (DAC) 110, a processing circuit 120, an analog-to-digital conversion circuit (ADC) 130, a storage circuit 140, a mixing circuit 150, and an update circuit 160. The digital-to-analog conversion circuit 110 and the echo cancellation circuit 200 are coupled to the processing circuit 120. For example, the digital-to-analog conversion circuit 110 and the echo cancellation circuit 200 may be coupled to the processing circuit 120 through a hybrid integrated circuit (hybrid) HY. The processing circuit 120 is coupled to the analog-to-digital conversion circuit 130. The analog-to-digital conversion circuit 130 is coupled to the storage circuit 140. The memory circuit 140 is coupled to the hybrid circuit 150 and the refresh circuit 160. The hybrid circuit 150 is coupled to the refresh circuit 160. The echo cancellation circuit 300 is coupled to the hybrid circuit 150.

In operation, the digital-to-analog conversion circuit 110 may receive a digital transmission signal TX. The dac circuit 110 may generate an analog transmission signal TXC according to the digital transmission signal TX. For example, the dac circuit 110 may perform a dac process to convert the digital transmission signal TX into the analog transmission signal TXC. The analog transmission signal TXC can be outputted to the outside (outside the data transmission circuit 100) through the hybrid integrated circuit HY.

The processing circuit 120 may receive a reception signal RXC from the outside, and generate an analog processing signal AFE _ O according to the reception signal RXC. In some embodiments, processing circuit 120 is implemented by an analog front-end processing circuit.

However, in some cases (e.g., impedance mismatch of the two transmission lines or mismatch of the hybrid integrated architecture of the receiving device), the analog transmission signal TXC may be introduced (e.g., via the hybrid integrated circuit HY) into the transmission line used to carry the reception signal RXC, causing echo (echo).

The echo cancellation circuit 200 may also receive a digital transmission signal TX. The echo cancellation circuit 200 may generate an echo cancellation signal EC1 according to the digital transmission signal TX to cancel most of the echo in the system at the analog end. For example, the hybrid integrated circuit HY may subtract the echo cancellation signal EC1 from the analog transmission signal TXC and input the calculation result to the processing circuit 120. In some embodiments, hybrid integrated circuit HY includes two current sources, one current source corresponding to the analog transmit signal TXC and the other current source corresponding to the echo cancellation signal EC1. In some embodiments, the echo cancellation circuit 200 at least includes a digital-to-analog conversion circuit and a filter circuit (not shown).

The echo cancellation circuit 300 may also receive a digital transmission signal TX. The echo cancellation circuit 300 may generate an echo cancellation signal EC2 according to the digital transmission signal TX to cancel the remaining echo at the digital end. In some embodiments, the echo cancellation circuit 300 comprises at least one filter circuit (not shown).

By means of the echo cancellation signal EC1 and the echo cancellation signal EC2, the influence of echo on the signal in the system can be cancelled, and further, the signal-to-noise ratio (SNR) of the system is improved.

As mentioned above, if the analog transmission signal TXC is introduced into the transmission line carrying the reception signal RXC, an echo will be caused. That is, the processing circuit 120 receives part or all of the analog transmission signal TXC to generate the analog processing signal AFE _ O according to the analog transmission signal TXC, the echo cancellation signal EC1 and the reception signal RXC.

Analog-to-digital conversion circuit 130 may receive analog processing signal AFE _ O. The analog-to-digital conversion circuit 130 may perform an analog-to-digital conversion procedure on the analog processing signal AFE _ O to convert the analog processing signal AFE _ O into a digital value (code word) CW.

Refer to fig. 2A. Fig. 2A is a schematic diagram illustrating the operation of the analog-to-digital conversion circuit 130 when the slice level SL is not deviated according to some embodiments of the invention.

In implementation, the analog-to-digital conversion circuit 130 may have a function (i.e., an analog-to-digital conversion function) of corresponding a plurality of slice levels (slice levels) SL to a plurality of digital values (codeword) CW. Taking fig. 2A as an example, the slice level SL includes a slice level SL [ -n ] -SL [ + n ], and the digital value CW includes a digital value CW [ - (n + 1) ] -CW [ + n ]. Further, any two adjacent slice levels SL may correspond to a digital value CW. This digital value CW may be substantially equal to a middle value between the two adjacent slice levels SL, but is not limited thereto. In operation, the adc circuit 130 determines which two adjacent slice levels SL the level of the analog processing signal AFE _ O it receives (i.e., the slice level SL closest to and greater than the level of the analog processing signal AFE _ O and the slice level SL closest to and less than the level of the analog processing signal AFE _ O) fall between, and selects and outputs the digital value CW corresponding to the two adjacent slice levels SL. For example, the slice level SL +1 and the slice level SL [0] correspond to the digital value CW [0]. Accordingly, if the analog-to-digital conversion circuit 130 determines that the level of the analog processing signal AFE _ O it receives falls between the slice level SL +1 and the slice level SL [0], the analog-to-digital conversion circuit 130 selects the digital value CW [0] and outputs the digital value CW [0].

Based on the above operation principle, the ADC circuit 130 will correspond all levels falling between the slice level SL [0] and the slice level SL [ +1] to a single digital value CW [0]. It is understood that the analog-to-digital conversion circuit 130 has a plurality of stages defined by level intervals. When the analog processing signal AFE _ O falls within a specific level interval, the analog-to-digital conversion circuit 130 outputs the digital value CW corresponding to the shift position. However, the values of these levels are mostly not identical to the digital value CW [0], and thus there may be a difference (i.e., noise) between the level of the digital value CW output by the analog-to-digital conversion circuit 130 and the actual level of the analog processing signal AFE _ O. These noises are also called quantization noise (quantization noise).

Refer to fig. 2A and 2B. Fig. 2B is a schematic diagram illustrating the operation of the analog-to-digital conversion circuit 130 when the slice level SL deviates according to some embodiments of the present invention.

In some embodiments, these clip levels SL may deviate from the originally designed level values due to changes in the manufacturing process or ambient temperature. That is, the deviated clip levels SL '[ + n ] -SL' [ -n ] after the deviation include the deviation values SH [ -n ] -SH [ + n ], respectively. For example, in FIG. 2B, if the difference between the offset slice level SL [ +1] and the offset slice level SL' [0] is greater than the difference between the slice level SL [ +1] and the slice level SL [0] in FIG. 2A, this means that there are more levels corresponding to a single digital value CW [0] in FIG. 2B (i.e., the width of the slice level interval corresponding to the same digital value increases). These level intervals widened by the deviation have a larger difference between the level value and the digital value CW [0], and thus the quantization noise of the analog-to-digital conversion circuit 130 increases.

In order to avoid the above problem, in the present invention, the storage circuit 140 may store a lookup table (e.g., the lookup table LUT in fig. 3). In some embodiments, storage circuit 140 is implemented by a register.

Refer to fig. 3. Fig. 3 is a schematic diagram of a lookup table LUT according to some embodiments of the invention. Taking fig. 3 as an example, the lookup table LUT records the digital values CW [ -n ] -CW [ + n ] and corresponding offset values OFF [ - (n + 1) ] -OFF [ + n ].

Taking digital value CW [0] as an example, digital value CW [0] is mapped to the sum of digital value CW [0] and offset value OFF [0] in look-up table LUT. Accordingly, as described above, when the analog-to-digital conversion circuit 130 determines from fig. 2B that the level of the received analog processing signal AFE _ O falls within the level interval between the offset slice level SL '[ +1] and the offset slice level SL' [ + 0], the analog-to-digital conversion circuit 130 may first select the corresponding digital value CW [0]. Then, the storage circuit 140 may output the sum of the digital value CW [0] and the offset value OFF [0] as the output signal OUT1 in FIG. 1 based on the lookup table LUT in FIG. 3 (or other control circuit operating with the lookup table LUT in the storage circuit 140). In some embodiments, the initial value of these offset values, OFF [ - (n + 1) ] -OFF [ + n ], is 0 and can be updated by the update circuit 160 to converge to the appropriate value. In this regard, further details will be provided in the following paragraphs.

Reference is again made to fig. 1. After the digital value CW output by the analog-to-digital conversion circuit 130 is converted into the output signal OUT1 by the storage circuit 140, the hybrid circuit 150 can receive the output signal OUT1. The hybrid circuit 150 may generate the output signal OUT2 according to the output signal OUT1 and the echo cancellation signal EC 2. For example, the mixing circuit 150 adds the output signal OUT1 to the echo cancellation signal EC2 to generate the output signal OUT2. The output signal OUT2 reflects the received signal RXC and the error value ER. For example, the error value ER includes an echo not completely eliminated in the output signal OUT2 and quantization noise (e.g., quantization noise corresponding to an undistorted slice level and quantization noise corresponding to a deviated slice level).

In some embodiments, the filter coefficients of the echo cancellation circuit 300 may be updated according to the output signal OUT2 and a Least Mean Square (LMS) operation procedure during an initial number of operation cycles (for example, but not limited to, 10 operation cycles). These offset values OFF [ - (n + 1) ] -OFF [ + n ] are updated again (as in the following formula (1)) until the filter coefficients of the echo cancellation circuit 300 are stabilized. These offset values, OFF [ - (n + 1) ] -OFF [ + n ], may be updated more than once in each operating cycle after the system has stabilized.

Refer again to fig. 1 and 3. As previously described, the update circuit 160 may update these offset values OFF [ - (n + 1) ] -OFF [ + n ] in the look-up table LUT. For example, as shown in FIG. 1, if the ADC circuit 130 selects and outputs the digital value CW [0], the update circuit 160 may update the offset value OFF [0] corresponding to the digital value CW [0] according to the digital value CW [0] and the output signal OUT2 (which may reflect the error value ER corresponding to the digital value CW [0 ]). In some embodiments, the update circuit 160 may update each offset value according to the following equation (1):

OFF [ i ] = OFF [ i ] -M × ER … equation (1)

Where i ranges from- (n + 1) to + n, n is a positive integer, OFF [ i ] to the right of the equal sign is the current offset value, M is the intensity value and can be designed according to system requirements, ER is the error value, and OFF [ i ] to the left of the equal sign is the updated offset value.

The above-mentioned intensity value and the characteristic value (Eigen-value) of the least mean square operation procedure of the systemRelated, and may range from 2 ^-10 ～2 ^-5 However, the present invention is not limited to this range.

For example, when the offset value OFF [0] is updated by the above equation (1), the updated offset value OFF [0] will approach or substantially equal to the middle between the offset value SH [0] and the offset value SH [ +1 ].

The more times the analog-to-digital conversion circuit 130 selects and outputs the digital value CW [0] is accumulated, the closer the offset value OFF [0] after update is to the middle value between the offset value SH [0] and the offset value SH [ +1 ]. Accordingly, quantization noise can be minimized. Conversely, if the digital value CW [0] is never selected and output by the ADC circuit 130 (i.e., there are no accumulated times), the offset value OFF [0] will not be updated. However, if the digital value CW [0] is never selected by the analog-to-digital conversion circuit 130, this is relatively representative of the absence (or lack) of a corresponding level in the analog processing signal AFE _ O. Therefore, even if the offset value OFF [0] is not updated, quantization noise is relatively unaffected.

It should be noted that, although in FIG. 1, the offset value OFF [0] is updated according to the error value ER reflected by the node N1 where the output signal OUT2 is located. However, the present invention is not limited to the above. In some other embodiments, the offset value OFF [0] may be updated according to an error value reflected by other back-end circuit internal nodes.

Based on the above operation, the present invention can make the updated offset value OFF [0] close to or substantially equal to the middle value between the deviation value SH [0] and the deviation value SH [ 1] without correcting the deviation slice level SL '[0] -SL' [ +1] of the analog-to-digital conversion circuit 130, so that the output signal OUT1 (the sum of the digital value CW [0] and the updated offset value OFF [0 ]) is approximately maintained at the middle value of the two corresponding deviation slice levels, thereby minimizing the quantization noise and maintaining (or improving) the signal-to-noise ratio of the system.

For easy understanding, the above description takes the digital value CW [0] as an example. The other digital values CW have similar operations and will not be described in detail herein.

Refer to fig. 4. Fig. 4 is a graph illustrating signal-to-noise ratios according to some embodiments of the invention. For the example of fig. 4, after 10 operating cycles, the signal-to-noise ratio of the system will be improved by 1 to 3 db.

Please refer to fig. 1-5. Fig. 5 is a flow diagram illustrating an echo cancellation method 500 according to some embodiments of the invention. The echo cancellation method 500 includes operations S510, S520, S530, S540, S550, and S560.

In operation S510, an analog transmission signal TXC is generated from the digital transmission signal TX by the digital-to-analog conversion circuit 110. In some embodiments, the dac circuit 110 may perform a dac process to convert the digital transmission signal TX into the analog transmission signal TXC.

In operation S520, an echo cancellation signal EC1 is generated from the digital transmission signal TX by the echo cancellation circuit 200. In some embodiments, the echo cancellation circuit 200 at least includes a digital-to-analog conversion circuit and a filter circuit to generate the echo cancellation signal EC1, so as to cancel most of the echoes in the system at the analog end.

In operation S530, an analog processing signal AFE _ O is generated by the processing circuit 120 according to the analog transmission signal TXC, the echo cancellation signal EC1, and the reception signal RXC. In some embodiments, processing circuit 120 is implemented by an analog front-end processing circuit.

In operation S540, a digital value CW is generated from the analog processing signal AFE _ O and the two slice levels SL by the analog-to-digital conversion circuit 130. In some embodiments, the digital value CW may be substantially equal to a value midway between the two slice levels SL. If the analog-to-digital conversion circuit 130 determines that the level of the analog processing signal AFE _ O falls between two slice levels SL, the analog-to-digital conversion circuit 130 outputs a digital value CW.

In operation S550, the look-up table LUT is stored by the memory circuit 140, and the output signal OUT1 is output according to the digital value CW and the offset value OFF corresponding to the digital value CW. In some embodiments, the two slice levels SL may deviate from the originally designed level values due to changes in the manufacturing process or the ambient temperature. Accordingly, the offset value OFF may be updated according to the above equation (1), and the storage circuit 140 may output the sum of the digital value CW and the updated offset value OFF as the output signal OUT1 according to the digital value CW output by the analog-to-digital conversion circuit 130.

In operation S560, the offset value OFF is updated according to the error value ER. In some embodiments, the offset value OFF is updated according to the above formula (1), and the error value ER is related to the output signal OUT1 of the memory circuit 140.

In summary, in the echo cancellation system and the echo cancellation method of the present invention, the offset value can be updated according to the corresponding error value. Accordingly, even if the slice level is shifted, the output signal can be maintained at approximately the middle of the two shifted slice levels by the updated offset value. In this way, quantization noise can be minimized and the signal-to-noise ratio of the system can be maintained (or improved).

Although the present invention has been described in terms of the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention, so that the scope of the present invention should be determined by the appended claims.

Description of the reference numerals:

100: data transmission circuit

110: digital-to-analog conversion circuit

120: processing circuit

130: analog-to-digital conversion circuit

140: memory circuit

150: hybrid circuit

160: refresh circuit

200. 300, and (2) 300: echo cancellation circuit

500: echo cancellation method

S1: echo cancellation system

TX: digital transmission signal

TXC: analog transmission signal

RXC: receiving a signal

EC1, EC2: echo cancellation signal

HY: hybrid integrated circuit

AFE _ O: analog processing of signals

SL, SL [ + n ] -SL [ -n ]: slice level

CW, CW [ + n ] -CW [ - (n + 1) ]: digital value

SL '[ + n ] -SL' [ -n ]: deviating from the slice level

SH < -n > -SH < + n >: deviation value

LUT: lookup table

OFF, OFF [ - (n + 1) ] -OFF [ + n ]: offset value

OUT1, OUT2: output signal

ER: error value

N1: node point

S510, S520, S530, S540, S550, S560: operation of

Claims (10)

1. An echo cancellation system, comprising:

a digital-to-analog conversion circuit for generating an analog transmission signal according to a digital transmission signal;

a first echo cancellation circuit for generating a first echo cancellation signal according to the digital transmission signal;

a processing circuit for generating an analog processing signal according to the analog transmission signal, the first echo cancellation signal and a receiving signal;

an analog-to-digital conversion circuit for generating a digital value according to the analog processing signal and two of the plurality of slice levels; and

a memory circuit configured to store a lookup table, wherein the lookup table records an offset value corresponding to the digital value, wherein the memory circuit is further configured to output a first output signal according to the digital value and the offset value, wherein the offset value is updated according to an error value associated with the first output signal.

2. The echo cancellation system of claim 1, further comprising:

a second echo cancellation circuit for generating a second echo cancellation signal according to the digital transmission signal; and

a hybrid circuit for generating a second output signal according to the first output signal and the second echo cancellation signal.

3. The echo cancellation system of claim 2, wherein the second output signal reflects the received signal and the error value.

4. The echo cancellation system of claim 2, wherein an initial value of said offset value corresponding to said digital value is 0.

5. The echo cancellation system of claim 4, wherein the offset value corresponding to the digital value is updated based on a current offset value, a strength value, and the error value.

6. The echo cancellation system of claim 5, wherein the two clipping levels correspond to two offset values, and wherein the offset value corresponding to the digital value is updated according to the two offset values corresponding to the two clipping levels to generate an updated offset value, and wherein a sum of the digital value and the updated offset value is the first output signal.

7. The echo cancellation system of claim 6, wherein the updated offset value is substantially equal to an intermediate value between the two offset values corresponding to the two clipping levels.

8. The echo cancellation system of claim 2, further comprising:

an updating circuit, coupled to the storage circuit and the mixing circuit, for receiving the digital value and the second output signal, respectively, and updating the offset value corresponding to the digital value.

9. The echo cancellation system of claim 2, wherein a plurality of filter coefficients of the second echo cancellation circuit are updated according to the second output signal and a least mean square procedure.

10. An echo cancellation method, comprising:

generating an analog transmission signal according to a digital transmission signal through a digital-to-analog conversion circuit;

generating a first echo cancellation signal according to the digital transmission signal through a first echo cancellation circuit;

generating an analog processing signal according to the analog transmission signal, the first echo cancellation signal and a receiving signal through a processing circuit;

generating a digital value according to the analog processing signal and two of the plurality of slice levels by an analog-to-digital conversion circuit;

storing, by a memory circuit, a lookup table and outputting a first output signal according to the digital value and an offset value corresponding to the digital value, wherein the lookup table records the offset value; and

the offset value in the lookup table is updated according to an error value associated with the first output signal.

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