CN115223626A - Memory controller, operating method thereof, memory system and electronic equipment - Google Patents

Abstract

The present disclosure provides a memory controller, an operating method thereof, a memory system, and an electronic device. The memory controller is configured to: judging whether to perform read interference processing on the first storage block according to the reading times of the first storage block; the reading interference processing is to read a first physical page of the first storage block by adopting a single-state reading voltage, and judge whether to carry out data transportation on the first physical page according to the number of the first physical page empty-state storage units; and sequentially processing other physical pages to finish the read interference processing of the first storage block.

Description

Memory controller, operating method thereof, memory system and electronic equipment

Technical Field

The present disclosure relates to the field of memory device technologies, and in particular, to a memory controller, an operating method thereof, a memory system, and an electronic device.

Background

The semiconductor memory may include volatile memory and nonvolatile memory. The nonvolatile memory may include a flash memory, an Electrically Erasable Programmable Read Only Memory (EEPROM), a Ferroelectric memory (FRAM), and the like. Flash memory is a low cost, high density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. The flash memory may include a NOR flash memory and a NAND flash memory. Various operations, such as reading, programming (writing), and erasing, may be performed by the flash memory.

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit. To overcome the limitations imposed by 2D or planar NAND flash memories, three-dimensional memories (3D NAND) having a three-dimensional structure have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

As market demands for memory density continue to increase, programming methods with more programming states are being developed so that each physical memory cell (cell) can represent more bits of information. However, the implementation of more programmed states has higher requirements on the formation process of a single memory cell and the distribution uniformity among multiple memory cells. Therefore, how to increase the storage density of the memory cells and improve the performance of the three-dimensional memory is a technical problem to be solved.

Disclosure of Invention

The present disclosure provides a memory controller and an operating method thereof, a memory system, and an electronic device, which can effectively improve read disturb of a memory.

The present disclosure is directed to solving the above-mentioned problems, and provides a method for operating a memory controller,

performing read disturb processing on a first physical page of a first memory block, the read disturb processing comprising the steps of:

performing read disturb scanning on a first physical page of a first storage block to obtain the number N1 of storage units in an erasing state in the first physical page;

and if the N1 is smaller than the threshold of the number of the storage units, the data of the first physical page is transported to a second storage block.

In bookIn a disclosed embodiment, the read disturb scan is a single-state read voltage V applied to the physical page _SLR And performing a read operation.

In one embodiment of the present disclosure, the single-state read voltage V _SLR Lower than the default read voltage V for the erased state _RL1 。

In one embodiment of the present disclosure, when the memory block is not subjected to read disturb, the maximum threshold voltage of the erase state of the memory block and the default read voltage V of the erase state are set _RL1 Is a difference of E ₀ Then V is _RL1 -E ₀ ≤V _SLR <V _RL1 。

In one embodiment of the present disclosure, V _RL1 -1/2E ₀ ≤V _SLR <V _RL1 。

In an embodiment of the present disclosure, the method of operating the memory controller further includes:

and after the read disturb processing is carried out on the first physical page, the read disturb processing is carried out on other physical pages of the first storage block.

In an embodiment of the disclosure, the performing of the read disturb process on the other physical pages of the first memory block is performed sequentially.

In an embodiment of the present disclosure, before performing the read disturb process on the first memory block, the method further includes:

acquiring the reading times of the first storage block;

comparing the reading times of the first storage block with a reading time threshold;

and if the reading times of the first storage block are greater than the reading time threshold, performing reading interference processing on the first storage block.

In an embodiment of the present disclosure, before performing the read disturb process on the first memory block, the method further includes:

after the read interference processing of the first storage block is finished, the read times of the first storage block are reset to zero;

and when the reading times of the first storage block are larger than the reading time threshold, performing reading interference processing on the first storage block again.

In an embodiment of the present disclosure, the method of operating a memory controller further includes:

if N1 is larger than the threshold of the number of the storage units, recording the minimum N1 as Nmin, and recording the physical address of the Nmin; and when the first storage block is subjected to read interference processing again, preferentially scanning or only scanning the physical page corresponding to the Nmin.

In an embodiment of the present disclosure, the read disturb processing operation specifically includes:

setting a single-state read voltage V _SLR ；

Applying a single-state read voltage V to the first physical page once _SLR Performing a read operation;

recording the number N1 of memory units in an erasing state in the first physical page;

comparing N1 with a threshold of the number of storage units;

if N1 is smaller than the threshold of the number of the storage units, the data of the first physical page is transported to a second storage block;

and if the N1 is greater than the threshold of the number of the storage units, recording the N1 as the minimum number of the storage units Nmin, and recording the address of the first physical page.

In an embodiment of the present disclosure, the method of operating the memory controller further includes:

after the read disturb processing is carried out on the first physical page, the read disturb processing is carried out on a second physical page, and the method comprises the following steps:

applying a single-state read voltage V once to a second physical page _SLR Performing a read operation;

recording the number N2 of memory cells in an erasing state in the second physical page;

comparing N2 with a threshold of the number of storage units;

if the N2 is smaller than the threshold of the number of the storage units, the data of the second physical page is transported to a second storage block;

if N2 is greater than the threshold number of memory cells,

then the comparison of N2 to Nmin,

and if the N2 is smaller than the Nmin, taking the N2 as the Nmin, and recording the address of the second physical page.

After the read disturb processing is performed on the second physical page, the read disturb processing is continuously performed on other physical pages of the first memory block, which is consistent with the read disturb processing on the second physical page, specifically as follows,

applying a single-state read voltage V once to an Xth physical page (X is a natural number greater than 2) _SLR Performing a read operation;

recording the number Nx of memory cells in an erasing state in the Xth physical page;

comparing Nx with a threshold of the number of memory cells;

if Nx is smaller than the threshold of the number of storage units, the data of the Xth physical page is transported to a second storage block;

if Nx is greater than the threshold number of memory cells,

then Nx is compared with Nmin,

and if the Nx is smaller than the Nmin, taking the Nx as the Nmin and recording the address of the Xth physical page.

In one embodiment of the present disclosure, a method of operating the memory controller,

after the read interference processing operation is carried out on the first storage block, the read times of the first storage block are reset to zero;

and when the reading times of the first storage block are larger than the reading time threshold again, performing the reading interference processing of the first storage block again.

In one embodiment of the present disclosure, the method for operating the memory controller preferentially scans the Nmin physical page recorded by the previous read disturb process.

In one embodiment of the present disclosure, the memory controller operates by scanning only the Nmin physical pages recorded from the previous read disturb process.

In another aspect of the present disclosure, there is provided a memory controller, the memory controller being configured to:

acquiring reading frequency data of a storage block, reading interference scanning data of a physical page and address data of the physical page; calculating the relation between the reading time data of the storage block and a reading time threshold and the relation between the reading interference scanning data of the physical page and a storage unit number threshold; and judging whether to perform read interference processing and data transportation according to the calculation result, and controlling the data transportation.

In an embodiment of the present disclosure, the memory controller, the read disturb scan data, applies a single-state read voltage V to the physical page in the memory block _SLR And performing reading operation.

In one embodiment of the present disclosure, the reading of the disturb scan data by the memory controller includes applying a single-state read voltage V _SLR The number of memory cells in the later physical page that are in the erased state.

In one embodiment of the present disclosure, the memory controller,

setting the initial maximum threshold voltage value of the memory block in the erasing state and the default reading voltage V in the erasing state _RL1 A difference of E ₀ Then a single state read voltage V _SLR Is of a value range of V _RL1 -E ₀ ≤V _SLR <V _RL1 。

In an embodiment of the disclosure, the memory controller is configured to zero the number of reads of the first memory block after performing the read disturb processing operation on the first memory block.

In an embodiment of the disclosure, the memory controller is configured to instruct storage of the physical page address data to a specified location of a storage device.

In another aspect of the present disclosure, a memory system is provided, which includes a memory device and the memory controller or the memory controller capable of executing the control method.

In another aspect of the present disclosure, an electronic device is provided, which includes the storage system.

Compared with the prior art, the technical scheme adopted by the disclosure has the following remarkable advantages:

the control method of the three-dimensional memory of the invention,

first, the present disclosure employs a single-state read voltage to read a physical page, accurately represents the physical effect of read disturb by using the number of memory cells in an erased state, and eliminates the disturb of other factors, such as data retention, cross temperature and other reliability problems.

Secondly, when the memory block is a TLC (thin layer logic), QLC (quantum liquid crystal), PLC (programmable logic controller) or more state memory blocks, the single-state reading is the reading of the first physical page of the first memory block once, and the reading interference degree of the first physical page is obtained; compared with the reading interference degree of the first physical page obtained by reading each storage state of the first physical page, the speed is higher, and the efficiency is higher;

thirdly, the reading interference processing of the present disclosure uses the number of memory cells in an erased state to represent the physical effect of reading interference, and directly counts the number of memory cells in the erased state without Low Density Parity Check (LDPC), which is accurate and more efficient;

fourthly, the reading interference scanning of the present disclosure is to perform scanning and data transportation by taking a physical page as a unit, and by reading interference scanning, a physical position where a real reliability risk exists can be accurately located, and data transportation (data relocation) is performed on a certain storage page with a large reading interference degree in a targeted manner, without data transportation of the whole storage block, so that low processing efficiency and abrasion caused by mass data transportation are reduced;

fifth, the present disclosure records that, in the previous read disturb processing, the physical page scanned by the read disturb (i.e., the physical page corresponding to Nmin) is the largest among the physical pages that have not been subjected to data transportation, so that, in the case of needing to perform the read disturb processing quickly, the physical location scanned by the maximum read disturb degree of the previous time may be preferentially scanned, or only the physical location scanned by the maximum read disturb degree of the previous time may be performed in a special case, so as to save the read disturb processing time and improve the processing efficiency.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams and are not intended to limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, which are involved in the embodiments of the present disclosure.

FIG. 1 illustrates a schematic diagram of an example memory device, according to some aspects of the present disclosure.

Fig. 2 illustrates a side view of a cross section of an example memory cell array including NAND memory strings, in accordance with some aspects of the present disclosure.

FIG. 3 illustrates a block diagram of an example memory device, in accordance with some aspects of the present disclosure.

FIG. 4 is a three-dimensional memory read disturb diagram in accordance with an example embodiment of the present disclosure;

FIG. 5 is a schematic diagram of three-dimensional memory read reference voltages and turn-on voltages according to an example embodiment of the present disclosure;

FIG. 6 is a three-dimensional memory read disturb scan voltage schematic according to an example embodiment of the present disclosure;

FIG. 7 is a flow diagram of a three-dimensional memory read disturb scan according to an example embodiment of the present disclosure;

FIG. 8 is a schematic flow diagram of a read disturb scan of a first physical page of a first memory block of a three-dimensional memory according to an example embodiment of the present disclosure;

FIG. 9 is a schematic flow diagram of a read disturb scan for physical pages other than a first physical page of a first memory block of a three-dimensional memory according to an example embodiment of the present disclosure;

FIG. 10 illustrates a block diagram of an example system with a memory device in accordance with some aspects of the present disclosure.

FIG. 11A illustrates a diagram of an example memory card with a memory device, according to some aspects of the present disclosure.

Fig. 11B illustrates a diagram of an example Solid State Drive (SSD) with memory devices, according to some aspects of the disclosure.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of protection of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary" or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

"at least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of A and B, A and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "over 8230 \ 8230"; "8230; up", "above", and "over" should be interpreted in the broadest manner, such that "over" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "on" something, but also includes the meaning of "over" or "on" something (i.e., directly on something) without intervening features or layers therebetween.

Fig. 1 illustrates a schematic circuit diagram of an example memory device 300 in accordance with some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in fig. 1. The memory device 300 can include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are arranged in an array of NAND memory strings 308, with each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and therefore can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is capable of storing more than a single bit of data in more than two memory states. For example, a multi-level cell (MLC) may store two bits of data per memory cell, a triple-level cell (TLC) may store three bits of data per memory cell, or a quad-level cell (QLC) may store four bits of data per memory cell.

As shown in FIG. 1, a plurality of NAND memory strings 308 may be organized into a plurality of blocks 304. In some implementations, each block 304 is the basic unit of data for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time.

Fig. 2 illustrates a side view of a cross section of an example memory cell array 301 including NAND memory strings 308, in accordance with some aspects of the present disclosure. As shown in fig. 2, NAND memory strings 308 may extend vertically through a stack structure 404 above a substrate 402. Substrate 402 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon On Insulator (SOI), germanium On Insulator (GOI), or any other suitable material. The stacked structure 404 may include alternating conductive layers 406 and dielectric layers 408. The number of pairs of conductive layers 406 and dielectric layers 408 in the stacked structure 404 may determine the number of memory cells 306 in the memory cell array 301. Conductive layer 406 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

Fig. 3 shows some exemplary peripheral circuits, and peripheral circuit 302 includes a page buffer 504, a column decoder 506, a row decoder 508, a voltage generator 510, a control logic unit 512, a register 514, and an input/output (I/O) circuit 516. It should be understood that in some examples, additional peripheral circuitry not shown in fig. 3 may also be included.

FIG. 4 is a three-dimensional memory read disturb diagram according to an example embodiment of the present disclosure. Read Disturb (Read Disturb) is an important failure mechanism for Flash Media (Flash Media), and managing Read Disturb is an important task for Flash Media based storage products. Typical Read disturbs include Single Page Read Disturb (Single Page Read Disturb) and Block Level Read Disturb (Block Level Read Disturb). In order to manage the Read interference problem, the memory records the Read times (Read Count) of each Physical Block (Physical Block) or Super Block (Super Block) of the flash memory, wherein the Read times are the times of reading operations performed on the memory Block, including the times of reading operations after programming operations and the times of independently performing the Read operations, and the Physical blocks are a set of Physical pages which are connected to the same source and can simultaneously perform erasing operations; the super block is a storage block which is composed of a plurality of physical blocks in different storage planes and can simultaneously carry out read-write operation. Once the Read Count reaches the Read Count Threshold, the controller scans all physical pages of the entire page to see if there is a risk, where the scan is a Read Operation under a default voltage condition (Read Operation). If there is a risk (some physical page fault bits reach a threshold), the controller will move the valid data of this physical block or super block to a new physical block or super block, and wait for the next read count to reach the threshold if there is no risk. The default read voltage is scanned and then the number of Error bits is obtained from the Error Correction Code Engine (Error Correction Code Engine), which does not really reflect the physical effect of read disturb, but only roughly reflects some physical Error condition, which may be caused by other factors such as data retention, cross temperature and other reliability problems, and may even be caused by the wrong default read voltage. This results in unnecessary data scanning and data handling operations, which affects the endurance of the entire system storage product.

Referring to fig. 4, in a current three-dimensional memory (e.g., 3D NAND flash) performing a read operation, one method is to apply a read voltage V-ref to a selected layer word line (gate) and apply a turn-on voltage V-pass to a non-selected layer gate when reading data of a certain memory cell. Typically, the turn-on voltage V-pass reaches 6V or more, which causes a significant threshold voltage increase after ten thousand read operations, especially for the erased (L0) and low programmed states, resulting in read errors. This is the read disturb/read disturb due to the turn-on voltage. Experiments show that the reading interference is positively correlated with the voltage causing the reading interference, and the larger the voltage of the conduction voltage V-pass is, the more serious the reading interference is.

FIG. 5 is a schematic diagram of a three-dimensional memory read voltage V-ref and a turn-on voltage V-pass according to an example embodiment of the present disclosure. As shown in fig. 5, taking an MLC in which the memory cells include four memory states as an example, the abscissa represents threshold voltage distributions of four different memory states, where L0 is the threshold voltage distribution of the erased state, L1-L3 are the threshold voltage distributions of different programmed states, and the ordinate represents the number of memory cells in each state, and it can be seen that the number of memory cells in each state is in a gaussian distribution. The read voltage V-ref is between any two adjacent memory states, and the read voltage is V from small to large _RL1 ,V _RL2 ,V _RL3 Wherein V is _RL1 The default read voltage, representing the erased state, the turn-on voltage V-pass is higher than the maximum value of the threshold voltage.

Fig. 6 is a schematic diagram of a three-dimensional memory read disturb scan voltage according to an example embodiment of the present disclosure. As shown in fig. 6, taking TLC that the memory cell includes eight memory states as an example, the abscissa represents threshold voltage distributions of eight different memory states, where L0 is the erase state threshold voltage distribution, L1-L7 are the threshold voltage distributions of different program states, and the ordinate represents the number of memory cells of each state, and it can be seen that the number of memory cells of each state is gaussian. The read disturb causes the threshold voltages of L0-L8 to spread and move to the right, wherein the threshold voltage distribution in the erased state L0 is most affected because the memory cell stores no charge when in the erased state, and is most susceptible to the turn-on voltage V-pass to write the charge, resulting in the threshold voltage distribution in the erased state L0 spreading and moving to the right, as shown in FIG. 6. Based on the principle, when any physical page is affected by read interference, the threshold voltages of different states of the physical page are affected to be widened and move to the right, wherein the threshold voltage distribution of the erasing state L0 is affected most, and therefore, only the threshold value in the erasing state L0 can be readAnd (4) voltage to judge the situation that the whole physical page is subjected to read interference. The present disclosure uses a single read voltage V when performing a read disturb scan in order to accurately read the number of memory cells in the erased state L0 _SLR . The single read voltage is lower than the default read voltage V of the erase state when not subjected to read disturb _RL1 . Setting the maximum threshold voltage of the memory block in the erase state and the default read voltage V in the erase state when the memory block is not subjected to read disturb _RL1 Is a difference of E ₀ Then there is V _RL1 -E ₀ ≤V _SLR <V _RL1 。

In one embodiment of the present disclosure, V _RL1 -1/2E ₀ ≤V _SLR <V _RL1 。

From the above formula, the single read voltage V _SLR Lower than the default read voltage V for the erased state when not subjected to read disturb _RL1 V due to the threshold voltage broadening and moving to the right in the erased state L0 _SLR The smaller the value, the smaller the number of memory cells at L0 that are read. Therefore, the single reading voltage can be adjusted by adjusting the single reading voltage, the precision of the read disturb processing can be adjusted, the single reading voltage is reduced if the precision of the read disturb processing is high, and the single reading voltage is increased if the precision of the read disturb processing is low.

Fig. 7 is a flow diagram of a three-dimensional memory read disturb scan according to an example embodiment of the present disclosure. As shown in fig. 7, the flow of the three-dimensional memory read disturb scan includes the following steps:

step S10, the host computer reads the first storage block;

step S20, recording the reading times of the first storage block;

step S30, comparing the reading times of the first storage block with a reading time threshold, and judging whether the reading time is greater than the reading time threshold;

at this time, if the number of times of reading the first storage block is greater than the read number threshold, it indicates that the number of times of reading the first storage block is greater, and the first storage block may have a read interference error, so that the read interference processing is performed on the first storage block; and the reading times of the first storage block are smaller than the reading time threshold, which shows that the reading times of the first storage block are not too many at this moment, and no reading interference error exists, the reading interference processing on the first storage bank is not performed, and the operation is finished.

The method for processing the read interference of the first storage block comprises the following steps:

step S40, reading interference processing is carried out on the maximum reading interference physical page recorded in the first storage block during the previous reading interference scanning;

step S50, sequentially carrying out read interference processing on other physical pages of the first storage block;

and finishing the read interference processing of the first storage block.

In an embodiment of the present disclosure, performing the read disturb process on the first memory block may include only step S50, and sequentially performing the read disturb process on all physical pages of the first physical block.

In an embodiment of the present disclosure, in order to improve the scanning efficiency, the read disturb processing on the first memory block may include only step S40, where the read disturb processing is performed on the maximum read disturb physical page recorded in the first memory block during the previous read disturb scanning.

In an embodiment of the present disclosure, preferentially performing step S40, and performing read disturb processing on the maximum read disturb physical page recorded in the first storage block during the previous read disturb scan. Then, it is determined whether step S50, i.e. sequentially performing read disturb processing on other physical pages of the first memory block, is required according to the read disturb result of step S40. That is, if the read disturb of the maximum read disturb physical page recorded in the first memory block in the previous read disturb scan is not serious, and the data of the physical page does not need to be transported, it may be considered that the read disturb degree of other physical pages of the first memory block is lower than the maximum read disturb physical page recorded in the previous read disturb scan, and therefore, step S50 does not need to be performed. On the contrary, if the read disturbance of the maximum read disturbance physical page recorded in the first memory block during the previous read disturbance scan is serious, the data of the physical page needs to be carried, and it may be considered that other physical pages of the first memory block may also be subjected to the serious read disturbance and the data needs to be carried, so step S50 is performed.

It should be noted that the memory block described in the present disclosure may be a two-dimensional memory block or a three-dimensional memory block. The memory block is composed of memory cells, the memory cells controlled by the same word line form a physical page, and a plurality of simultaneously erasable physical pages connected to the same source line form a memory block.

FIG. 8 is a schematic flow diagram of a read disturb process for a first physical page of a first memory block of a three dimensional memory according to an example embodiment of the present disclosure. As shown in fig. 8, the step S50 of performing the read disturb process on the first physical page specifically includes the following steps:

s501, setting a single-state reading voltage V _SLR . As described above, the single read voltage is lower than the default read voltage V for the erased state when not subject to read disturb _RL1 The value of which is adjusted according to the characteristics of different storage particles, the adjustment range V _RL1 -E ₀ ≤V _SLR <V _RL1 In particular, for example V _SLR ＝V _RL1 -E ₀ ，V _SLR ＝V _RL1 -1/2E ₀ ，V _SLR ＝V _RL1 -1/3E ₀ Etc. within said adjustment range, V _SLR The larger, the closer to V _RL1 When the performance of the storage particles is good and the storage particles are not easily interfered by reading, the threshold voltage distribution in the erasing state is less influenced, the threshold voltage in the erasing state is widened and moves rightwards less, and V can be changed _SLR Set to a smaller value; on the contrary, when the performance of the memory particles is not good and is easy to be interfered by reading, the distribution of the threshold voltage in the erasing state is greatly influenced, the threshold voltage is widened and moves to the right greatly, and the V can be changed _SLR Set to a larger value, in this case, V _SLR Closer to the default read voltage V for the erased state when not subject to read disturb _RL1 。

Step S502, using V _SLR Reading a first physical page, and recording the number N1 of memory units in an erasing state;

and S503, judging whether N1 is smaller than the threshold of the number of the storage units. The threshold of the number of memory cells is determined according to the number of memory cells in the erased state of the physical page when the physical page is not subjected to read disturb. And programming a first physical page of the first memory block when the first memory block is not subjected to read interference, wherein the number of memory cells in each state in the first physical page is basically uniformly distributed after programming is finished. Taking TLC as an example, when the memory cell is not disturbed by reading, the ratio of the number of memory cells in an erased state in the first physical page of the first memory block storing data to the total number of memory cells in the physical page is about 1/8. After the read disturb, the number of memory cells in the physical page that are in the erased state is reduced. And when the reading interference degree of the physical page is serious, reading interference processing is required. The threshold of the number of memory cells is set in order to determine the degree of read disturb. The threshold of the number of memory cells is lower than 1/8 of the total number of memory cells of the first physical page, and the specific value is influenced by the performance of the memory grain, the error correction capability of the controller, the required data stability and the like.

According to the judgment result in the step S503, if N1 is smaller than the threshold of the number of storage units, it indicates that the read interference degree of the read physical page is relatively serious, and the step S504 is entered to transfer the data of the physical page to the first physical page of the second storage block. The "transfer" refers to copying and writing data of the physical page, that is, reading the data of the physical page and writing the data into the first physical page of the second storage block.

In an embodiment of the present disclosure, an address of a first physical page of the first memory block is mapped to a first physical page of a second memory block.

According to the judgment result of the step S503, if N1 is greater than the threshold of the number of storage units, it indicates that the read interference degree of the read physical page is relatively low, and the read interference processing on the first physical page is completed without data transportation.

In an embodiment of the present disclosure, the number of memory cells of the first physical page of the first memory block is recorded as Nmin as the minimum number of memory cells greater than a memory cell threshold;

in an embodiment of the present disclosure, the address of the physical page corresponding to Nmin is recorded.

And after the read interference processing of the first physical page of the first memory is finished, sequentially carrying out the read interference processing on other physical pages of the first memory.

Fig. 9 is a flowchart illustrating a read disturb process for a physical page other than a first physical page of a first memory block of a three-dimensional memory according to an exemplary embodiment of the disclosure. As shown in fig. 9, performing read disturb processing on the other physical pages includes the following steps:

s501', setting a single-state reading voltage V _SLR . In one embodiment of the present disclosure, the single-state read voltage set in step S501' is the same as the single-state read voltage set in step S501. In one embodiment of the present disclosure, the single-state read voltage is set only when the first physical page of the first memory block is read, and the single-state read voltage is not reset when other physical pages of the first memory block are read, but is directly used when the first physical page of the first memory block is read.

Step S502', using V _SLR Reading a second physical page and recording the number N2 of the memory units in an erasing state;

and S503', judging whether the N2 is smaller than the threshold of the number of the storage units. The threshold of the number of memory cells is the same as the threshold of the number of memory cells stored in step S503.

According to the judgment result of the step S503', if N2 is smaller than the threshold of the number of memory cells, it indicates that the read interference degree of the read physical page is relatively serious, the step S504' is entered, and the data of the second physical page of the first memory block is transferred to the second physical page of the second memory block.

In an embodiment of the present disclosure, an address of a second physical page of the first memory block is mapped to a second physical page of a second memory block.

According to the judgment result of the step S503', if N2 is greater than the threshold of the number of storage units, it indicates that the read interference degree of the read physical page is relatively low, and the read interference processing on the second physical page is completed without carrying data.

In an embodiment of the disclosure, the processing of the read disturb on the second physical page further includes the steps of:

and step S505', judging whether N2 is smaller than the minimum storage unit number Nmin recorded at the previous time. And if the N2 is not less than Nmin, finishing the read interference processing of the second physical page. If N2 is less than Nmin, step S506' is performed, and N2 is taken as Nmin.

In an embodiment of the present disclosure, the address of the physical page corresponding to Nmin is recorded.

And after the read interference processing on the second physical page of the first memory block is finished, sequentially performing the read interference processing on other physical pages, wherein the read interference processing step is the same as the read interference processing step of the second physical page until the read interference scanning on all the physical pages of the first memory block is finished.

At this time, nmin represents the minimum number of memory cells larger than the memory cell threshold in all the physical pages of the first memory block, and the physical page corresponding to Nmin is the physical page with the maximum read interference degree in the physical pages which are not subjected to data transfer.

After the read disturb processing operation on the first storage block is completed, the first storage block can be regarded as a storage block without read disturb, so that the read times of the first storage block are reset to zero; and when the reading times of the first storage block are larger than the reading time threshold again, performing the reading interference processing of the first storage block again.

Since the physical page address corresponding to Nmin is recorded in the previous read disturb processing, and the physical page corresponding to Nmin is the physical page that has the largest read disturb degree among the physical pages that have not been subjected to data transfer, when the read disturb processing is performed again on the first storage block, the read disturb processing can be preferentially performed on the processing page corresponding to Nmin. In a special case, in order to increase the read disturb processing speed, the read disturb processing may be performed only on the physical page corresponding to Nmin.

In another aspect of the present disclosure, there is provided a memory controller, the memory controller being configured to:

acquiring reading frequency data of a storage block, reading interference scanning data of a physical page and address data of the physical page; calculating the relation between the reading frequency data of the storage block and a reading frequency threshold and the relation between the reading interference scanning data of the physical page and a storage unit quantity threshold; and judging whether to perform read interference processing and data transportation according to the calculation result, and controlling the data transportation.

In an embodiment of the present disclosure, the memory controller, the read disturb scan data, applies a single-state read voltage V to the physical page in the memory block _SLR And performing reading operation.

In one embodiment of the present disclosure, the reading the disturb scan data includes applying a single-state read voltage V _SLR The number of memory cells in the later physical page that are in the erased state.

In one embodiment of the present disclosure, the memory controller,

setting the initial maximum threshold voltage value of the memory block in the erasing state and the default reading voltage V in the erasing state _RL1 A difference of E ₀ Then a single state read voltage V _SLR The numerical range of (A) is V _RL1 -E ₀ ≤V _SLR <V _RL1 。

In an embodiment of the disclosure, the memory controller is configured to zero the number of reads of the first memory block after performing the read disturb processing operation on the first memory block.

In an embodiment of the disclosure, the memory controller is configured to instruct storage of the physical page address data to a specified location of a storage device.

In another aspect of the present disclosure, a memory system is provided, which includes a memory device and the memory controller or the memory controller capable of executing the control method.

The Storage system may be integrated into various types of Storage devices, for example, included in the same package (e.g., universal Flash Storage (UFS) package or Embedded multimedia Card (eMMC) package). That is, the storage system may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, the memory system includes a controller and a three-dimensional memory, and the memory system may be integrated into a three-dimensional memory card.

The three-dimensional Memory Card includes any one of a PC Card (PCMCIA, personal computer three-dimensional Memory Card international association), a Compact Flash (CF) Card, a Smart Media (SM) Card, a three-dimensional Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, the storage system includes a controller and a plurality of three-dimensional memories, and the storage system 1000 is integrated into a Solid State Drive (SSD).

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system described above, and may further include at least one of a Central Processing Unit (CPU), a buffer (cache), and the like. Fig. 10 illustrates a block diagram of an example system 100 with a memory device in accordance with some aspects of the present disclosure. The system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 10, system 100 may include a host 108 and a memory system 102, memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may include a processor of an electronic device, such as a Central Processing Unit (CPU), or a system-on-chip (SoC), such as an Application Processor (AP). The host 108 may also include a storage interface for coupling with the memory system 102 that is configured to comply with a corresponding protocol (e.g., NVMe, PCIe, etc. protocol), and the host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104 through, for example, the storage interface. To send data to memory device 104 or receive data from memory device 104, host 108 may send instructions to memory system 102 in addition to the data. Memory device 104 may be any memory device disclosed in this disclosure.

According to some embodiments, memory controller 106 is coupled to memory devices 104 and host 108, and is configured to control memory devices 104. The memory controller 106 may be embodied by a microprocessor, microcontroller (a.k.a. Microcontroller unit (MCU)), central Processing Unit (CPU), digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), field Programmable Gate Array (FPGA), programmable Logic Device (PLD), state machine, gated logic unit, discrete hardware circuitry, or combinations thereof, as well as other suitable hardware, firmware, and/or software configured to perform the various functions described in detail below. The memory controller 106 may manage data stored in the memory devices 104 and communicate with the host 108 through its front-end interface. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) Flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 106 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data storage and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like. The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations.

The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory devices 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is also configured to process Error Correction Codes (ECCs) with respect to data read from the memory device 104 or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-express) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so on.

The memory controller 106 and the one or more memory devices 104 may be integrated into various types of memory systems, including, for example, in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 11A, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), personal computer memory card International Association), CF card, smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMC micro), SD card (SD, mini SD, micro SD, SDHC), UFS, and the like. The memory card 202 may also include a memory card connector 204, the memory card connector 204 configured to couple the memory card 202 to a host (e.g., host 108 in fig. 10). In another example as shown in fig. 11B, the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include an SSD connector 208, the SSD connector 208 configured to couple the SSD 206 to a host (e.g., host 108 in fig. 10). In some implementations, the storage capacity and/or operating speed of SSD 206 is greater than the storage capacity and/or operating speed of memory card 202.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (18)

1. A method of operating a memory controller,

performing read disturb processing on a first physical page of a first memory block, the read disturb processing comprising the steps of:

performing read disturb scanning on a first physical page of a first storage block to obtain the number N1 of storage units in an erasing state in the first physical page;

and if the N1 is smaller than the threshold of the number of the storage units, the data of the first physical page is transported to a second storage block.

2. The method of claim 1, wherein the memory controller further comprises a memory controller,

the read disturb scan is one time application of a single state read voltage V to the first physical page _SLR And performing a reading operation.

3. The method of claim 2, wherein the memory controller further comprises a memory controller,

the single state read voltage V _SLR A default read voltage V lower than the first physical page erase state _RL1 。

4. The method of claim 3, wherein the memory controller further comprises a memory controller,

when the memory page is not disturbed by reading, the maximum value V of the threshold voltage of the memory page in the erasing state is obtained _L0 (ii) a Obtaining the V _RL1 And V _L0 Difference value E of ₀ ；

Setting a single-state read voltage V _SLR The single-state read voltage V _SLR Is of value V _RL1 -E ₀ ≤V _SLR <V _RL1 。

5. The method of claim 4, wherein V is _RL1 -1/2E ₀ ≤V _SLR <V _RL1 。

6. The method of claim 1, wherein the memory controller further comprises a memory controller,

and after the reading interference processing is carried out on the first physical page, the reading interference processing is carried out on other physical pages of the first storage block until the reading interference processing of the first storage block is completed.

7. The method of claim 1, wherein the memory controller further comprises a memory controller,

before performing read disturb processing on the first memory block, the method further includes:

acquiring the reading times of the first storage block;

comparing the reading times of the first storage block with a reading time threshold;

and if the reading times of the first storage block are greater than the reading time threshold, performing reading interference processing on the first storage block.

8. The method of claim 7, wherein the memory controller,

after the read interference processing of the first storage block is finished, the number of times of reading the first storage block is reset to zero;

and when the reading times of the first storage block are larger than the reading time threshold, performing reading interference processing on the first storage block again.

9. The method of claim 6, wherein the memory controller further comprises a memory controller,

the read interference processing on the first storage block comprises recording the minimum value of the number of storage units which are larger than the threshold of the number of storage units in all storage pages of the first storage block as Nmin, and recording the address of the Nmin; and when the first storage block is subjected to read interference processing again, preferentially scanning or only scanning the physical page corresponding to the Nmin.

10. The method of operating a memory controller according to any one of claims 1 to 9,

the read disturb processing operation specifically includes:

setting a single-state read voltage V _SLR ；

Applying a single-state read voltage V once to the first physical page _SLR Performing a read operation;

recording the number N1 of memory units in an erasing state in the first physical page;

comparing N1 with a threshold of the number of storage units;

if N1 is smaller than the threshold of the number of the storage units, the data of the first physical page is transported to a second storage block;

and if the N1 is greater than the threshold of the number of the storage units, recording the N1 as the minimum number of the storage units Nmin, and recording the address of the first physical page.

11. The method of claim 10,

after the read disturb processing is performed on the first physical page, the read disturb processing is performed on the second physical page, and the method comprises the following steps:

applying a single-state read voltage V once to a second physical page _SLR Performing a read operation;

recording the number N2 of memory units in an erasing state in the second physical page;

comparing the N2 with a storage unit number threshold;

if the N2 is smaller than the threshold of the number of the storage units, the data of the second physical page is transported to a second storage block;

if N2 is greater than the threshold number of memory cells,

then the comparison of N2 to Nmin,

and if the N2 is less than the Nmin, replacing the N2 with the Nmin, and recording the address of the second physical page.

12. A memory controller, characterized in that,

the memory controller is configured to:

performing read disturb processing on a first physical page of a first memory block, the read disturb processing comprising the steps of:

performing read disturb scanning on a first physical page of a first storage block to obtain the number N1 of storage units in an erasing state in the first physical page;

and if the N1 is smaller than the threshold of the number of the storage units, the data of the first physical page is transported to a second storage block.

13. The memory controller of claim 12,

the read disturb scan is to apply a single-state read voltage V to the physical page once _SLR A read operation is performed.

14. The memory controller of claim 13,

when the memory page is not disturbed by reading, the maximum value V of the threshold voltage of the memory page in the erasing state is obtained _L0 (ii) a Obtaining the V _RL1 And V _L0 A difference value E0;

setting a single-state read voltage V _SLR The single-state read voltage V _SLR Is of value range V _RL1 -E ₀ ≤V _SLR <V _RL1 。

15. The memory controller of claim 12,

the memory controller is configured to, before performing read disturb processing on a first physical page of a first memory block, further include:

acquiring the reading times of the first storage block;

comparing the reading times of the first storage block with a reading time threshold;

and if the reading times of the first storage block are greater than the reading time threshold, performing reading interference processing on the first physical page of the first storage block.

16. The memory controller of claim 12,

the memory controller is configured to return the number of times of reading of the first memory block to zero after performing read disturb processing on the first memory block;

and when the reading times of the first storage block are larger than the reading time threshold again, performing the reading interference processing of the first storage block again.

17. A memory system comprising a memory device and a memory controller as claimed in claims 12 to 16 or a memory controller capable of performing the method of operations as claimed in claims 1 to 11.

18. An electronic device comprising the storage system of claim 17.

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