CN115221900A

CN115221900A - Real-time reconfigurable universal memristor simulation circuit

Info

Publication number: CN115221900A
Application number: CN202210826639.XA
Authority: CN
Inventors: 许波; 耿航; 陈凯; 白利兵; 黄肖宇
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-07-14
Filing date: 2022-07-14
Publication date: 2022-10-21

Abstract

The invention discloses a real-time reconfigurable general memristor simulation circuit, which is characterized in that a memristor mathematical model is subjected to nonlinear fitting through m-term polynomials, wherein m is related to the amplitude and frequency of an input signal and the fitting precision, so that the specified memristor model can be simply and quickly adapted. On the basis, a system state variable generating module is constructed on the basis of an FPGA and used for system state variables, namely magnetic flux or electric charge quantity, a calculating module is used for m-level pipeline mode reconfigurable calculation of polynomial coefficients and the system state variables to obtain a memristor value or a memristance value, a delay FIFO is used for delaying an input signal x [ n ] for 3m clock cycles, an output module is used for multiplying the input signal with the memristor value output by the calculating module after the input signal is delayed for 3m clock cycles through the FIFO to obtain an output signal, namely a current signal or a voltage signal, the polynomial memristor can be reconstructed in real time by changing the polynomial coefficients, so that the purpose of reconstructing in real time to adapt to different model memristors is achieved, the memristors with high working frequency can be simulated, meanwhile, a digital circuit is used for reconstruction simulation, and the experimental accuracy is improved.

Description

Real-time reconfigurable universal memristor simulation circuit

Technical Field

The invention belongs to the technical field of memristor simulation, and particularly relates to a real-time reconfigurable universal memristor simulation circuit.

Background

In 1971, professor Chuai begonia first proposed a theoretical model of a memristor according to the theorem of circuit completeness. Professor zeisnia thinks that the memristor is the fourth basic two-terminal circuit element, in addition to the resistance, capacitance, and inductance, that describes the nonlinear relationship between charge and magnetic flux. Meanwhile, professor Chua begonia also gives 3 basic characteristics of the memristor: (1) under the excitation of bipolar periodic electric signals, the curve of the device on a V-I plane is a pinching and hysteresis loop; (2) when the scanning frequency of the electric signal is increased, the lobe area of the pinching hysteresis loop is continuously reduced; (3) as the sweep frequency approaches infinity, the pinch loop will contract as a single valued function.

Until 2008, a Stan Williams team of Hewlett-packard laboratories realizes a physical memristor in a nanometer-scale film based on a titanium dioxide (TiO 2) material for the first time, and the characteristics of the memristor and the application research thereof are not concerned by a large number of scholars. At this time, the memristor proposed by professor zeiss is not a theoretical mathematical model any more, but an actually existing device. At present, memristor models are widely applied to the fields of neural networks, machine learning, chaos theory, secret communication, graph encryption, nonvolatile memories, filter circuits and the like. Unfortunately, on one hand, different preparation raw materials of the memristor correspond to different physical mechanisms, so that the characteristics of the memristor are different, and the wide popularization and application of the memristor are limited. For example, researchers have found the phenomenon of hysteresis loop in various materials such as binary oxides, complex perovskite oxides, solid electrolyte materials, amorphous carbon materials, organic polymer materials, etc., and propose various physical mechanisms to explain memristive characteristics thereof, such as formation and fracture of conductive channels due to oxygen vacancy migration, modulation of interfacial barriers, formation and fracture of metal conductive channels due to metallization reaction of active electrodes, capture and release of injected carriers, and metal-insulator transition mechanisms, etc. On the other hand, due to the fact that production cost of the memristor is too high, commercial memristors cannot be directly purchased in the market at present. For example, knowm memristors are implemented as commercial components, but are difficult to popularize on a large scale due to their complex structure and high cost. In the face of complicated and changeable physical mechanisms and high production cost of the memristor, it is still very urgent and important to design a real-time reconfigurable general memristor simulation circuit facing various physical models for analyzing relevant characteristics of the memristor through an experimental exploration method.

Related researchers have conducted a great deal of research to improve the bandwidth (frequency) of memristor emulation circuits. Methods such as analog, digital-analog hybrid and application-specific integrated circuits are used to build memristor simulation circuits and perform verification and bandwidth testing.

After extensive theoretical research and professional hardware debugging capability of a large number of scholars, the simulation method mainly uses a large number of passive devices (such as resistors, capacitors and inductors) and active devices (such as operational amplifiers, transconductance operational amplifiers (OTA), current Feedback Operational Amplifiers (CFOA), differential current transmitters (DDCC) and analog multipliers) to carry out breadboard or circuit board experiments. The experimental bandwidth of memristor simulation circuits has evolved from the early 500Hz to the current 1.3MHz. Meanwhile, the memristor simulation circuit is powered by a positive power supply and a negative power supply. In the simulation method, for different memristor models and bandwidths, a memristor simulation circuit is often required to be redesigned, and a large amount of time is spent for debugging the circuit, particularly for MHz input signals, the experimental result cannot be verified by adopting a bread board mode, because the problems of parasitic parameters of signal transmission lines, impedance matching and crosstalk among signals must be solved. The signal output by the circuit board can adopt the Lissajous diagram function of an oscilloscope to display a pinching loop. It should be noted that the simulation method usually has a large error, and the sources of the error are mainly as follows: the errors of most commercial resistors, capacitors and inductors are about 5%,20% and 20%, respectively. The operational amplifier input voltage offset (Vos) and input bias current (Ib) can produce errors in the results. The nonlinear characteristics of the analog bandwidth of the active device have a large influence on the amplitude frequency curves of different signals. At present, a memristor simulation circuit with the bandwidth of 10MHz or more is not realized in the simulation method.

This is very difficult for most researchers engaged in basic research, since circuit design and debugging require very specialized circuit knowledge. The relevant scholars have proposed digital-analog hybrid methods. The digital-analog hybrid method generally adopts an ADC (analog-to-digital converter), a programmable general-purpose processor and a DAC (digital-to-analog converter) to realize the memristor simulation circuit, wherein the ADC and the DAC are respectively used for analog-digital quantization of input signals and digital-to-analog conversion of output signals, and the programmable general-purpose processor is used for calculating memristors or memos in real time according to a digital model. The digital analog method is simpler and faster to implement than the analog method, but the digital analog method also has the following limitations. The calculation speed, ADC and DAC working frequency and analog bandwidth of the programmable general processor limit the digital-analog hybrid method, and the memristor with high working frequency cannot be simulated. The resolution of the ADC, the DAC and the digital oscilloscope and the range of the output signal of the DAC limit that the digital-analog hybrid method cannot perform high-precision hardware simulation on the memristor model.

For the known memristor model, the relevant scholars have proposed an application specific integrated circuit approach. In the literature u.e.ayten, s.minaei, and M.

In "memrisor circuits using single CBTA," AEU-int.j.electron.command, vol.82, pp.109-118, dec.2017, doi. In documents a.yesil, "a new group of resistor based on MOSFET-C," AEU-int.j.electron.commu., vol.91, pp.143-149, jul.2018, doi. The circuit adopts Cadence Environment layout with TSMC 0.18 μm process parameter, the layout size is only 12 μm x 38 μm, and the area of the capacitor is not included. The analog simulation of the memristor after the layout is very consistent with the theoretical analysis. Obviously, the size of the memristor simulation circuit can be greatly reduced and the realization precision can be improved by adopting the method of the special integrated circuit. However, the duplicated design flow and high circuit manufacturing cost are main factors preventing the popularization of the methodAnd (5) element. The asic approach is only suitable for one known model, and is not suitable for studying memristor characteristics under multiple models.

In summary, first, most existing memristor simulation circuits can only simulate the dynamic behavior of memristors at relatively low frequencies, i.e., they exhibit a contracting hysteresis loop below a critical frequency and become linear resistances above the critical frequency. This limits the application of memristor emulation circuit in high-speed high bandwidth occasions, such as high frequency random signal generation, high-speed data transmission, high-speed data storage. Secondly, the existing memristor simulation circuit is designed facing a fixed model. Considerable time and effort is required from the theoretical model to the actual circuit output results, and in most cases, an engineer with a professional circuit background is required to participate in the hardware debugging process. The existing three methods can not realize real-time dynamic reconfiguration according to a model, so that the realization of a memristor simulation circuit by hardware is a time-consuming and low-efficiency tedious process. Finally, inherent errors of components, circuit transmission loss and measuring instrument errors in the memristor simulation circuit are very important for realizing a high-precision circuit of a memristor theoretical model, but at present, the experimental precision of the memristor simulation circuit does not arouse the attention of relevant scholars.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, and provides a real-time reconfigurable general memristor simulation circuit, which can be reconfigured in real time to adapt to memristors of different models, can simulate a memristor with high working frequency, and simultaneously improves the experimental precision of the memristor simulation circuit.

In order to achieve the purpose, the invention discloses a real-time reconfigurable general memristor simulation circuit, which is characterized by being constructed based on an FPGA and comprising the following steps:

the system state variable generation module comprises a multiplier, an accumulator and an adder, wherein the multiplier completes input signals x [ n ]]Multiplying with the clock period Ts of the FPGA system to obtain Ts.x [ n ]]And output to the accumulator for accumulation to obtain an accumulated value

And output to the adder to obtain the system state variable h [ n ]]：

h 0 is the initial value of the system state variable, the input signal x n is the voltage signal or the current signal, the system state variable h n is the magnetic flux or the electric charge;

the computing module consists of m reconfigurable computing units which are cascaded and work in an m-level pipeline mode and are used for realizing m polynomial multiply-accumulate operations, and each reconfigurable computing unit consists of 2 multipliers, 1 adder and 1D trigger;

for the (i + 1) th reconfigurable computing unit, i =0,1,2,., m-1, the inputs of which are polynomial coefficients k [ i +1], adder inputs s [ i ], first multiplier inputs H [ i ] and d [ i ], outputs are adder outputs s [ i +1], multiplier outputs H [ i +1] and input signal delays d [ i +1], and the mathematical relationship between the input signal and the output signal is:

the first multiplier multiplies input H [ i ] and D [ i ] and outputs H [ i +1], the second multiplier multiplies output H [ i +1] of the first multiplier and polynomial coefficient k [ i +1], the adder adds input s [ i ] and output k [ i +1] & H [ i +1] of the second multiplier and outputs s [ i +1], and the D flip-flop delays the input D [ i ] by one sampling clock to obtain input signal delay D [ i +1];

for the 1 st reconfigurable computing unit, the input d [ i ] is the magnetic flux or the charge quantity at the time of n, which is the system state variable H [ n ] output by the system state variable generating module, H [0] =1 is input, and s [ i ] = polynomial coefficient k [0] is input;

wherein the number of polynomials, i.e. the order m, is determined in the following way:

from the input signal x [ n ]]Respectively determining the amplitude and frequency of the zero DC component AC signal _max And minimum frequency ω _min Further determining the system state variable h [ n ]]Has a value range of

In that

Using the Merwolin formula to pair the memory conductance or memory resistance f (h [ n ]]) Make an action on the system state variable h [ n ]]Is fitted to obtain a fitting function g (h (n)), wherein the maximum fitting error epsilon _M Comprises the following steps:

let ε ₀ For an acceptable maximum fitting error, the polynomial order m should be chosen to satisfy ε _M ≤ε ₀ ；

Wherein the coefficient k [ i ] of the ith order polynomial]，k _i I =0,1, 2.. Multidot.m, and the memory resistor mathematical model needing simulation, namely the memory conductance value or the memory resistance value f (h [ n ] at n moments) according to the Melaurin formula]) Unfolding:

obtaining;

the output s [ m ] of the mth reconfigurable computing unit is used as a memory conductance value or a memory resistance value f (h [ n ]) and is sent to an output module;

a FIFO, which is used to delay the input signal x [ n ] by m +39 clock cycles and send it to the output module;

and the output module is composed of a multiplier, the input signal x [ n ] is multiplied by the memristive value or the memristive value f (h [ n ]) output by the calculation module after FIFO delay of m +39 clock cycles to obtain an output signal y [ n ], and the output signal y [ n ] is a current signal or a voltage signal.

The object of the invention is thus achieved.

The invention discloses a real-time reconfigurable general memristor simulation circuit, which utilizes the Weierstrass theorem and the Meglanlin formula to carry out nonlinear fitting on a memristor mathematical model through an m-term polynomial, wherein m is related to the amplitude and frequency of an input signal and the fitting precision, so that the appointed memristor model can be simply and quickly adapted by updating the order, polynomial coefficient and sampling interval of the polynomial. On the basis, a system state variable generating module is constructed on the basis of an FPGA and used for system state variables, namely magnetic flux or electric charge quantity, a calculating module is used for m-level pipeline mode reconstruction calculation of polynomial coefficients and the system state variables to obtain a memristor value or a memristor value, a delay FIFO is used for delaying an input signal x [ n ] for m +39 clock cycles, an output module is used for multiplying the input signal with the memristor value or the memristor value output by the calculating module after the input signal passes through the FIFO delay for m +39 clock cycles to obtain an output signal, namely a current signal or a voltage signal, the polynomial coefficients are changed to reconstruct the memristor in real time, and therefore the purpose of adapting to memristors of different models through real-time reconstruction is achieved. The memristor with high working frequency can be simulated by equivalently verifying the memristor characteristics of the high-frequency signal through a low-frequency signal experiment, and the outstanding advantage that the simulation bandwidth of the simulation circuit is not particularly concerned when the characteristics of the memristor are researched is achieved, is very convenient for most researchers without professional circuit debugging capability. Meanwhile, the invention is constructed based on FPGA, and adopts a digital circuit to carry out reconstruction simulation, so that the experimental precision is improved.

Drawings

FIG. 1 is a second order memristor model different coefficients k _i Plotted q-f (q) graph, where (a) is the coefficient k ₂ ≠0,k ₁ ≠0,k ₀ Not equal to 0, f (q) a single polarity, (b) a coefficient k ₂ ≠0,k ₁ ≠0,k ₀ Not equal to 0, f (q) bipolar, (c) coefficient k ₂ ≠0,k ₁ And =0.f (q) mono/bi polarity, and d is a coefficient k ₂ ≠0,k ₁ ≠0,k ₀ Bipolar =0,f (q) and (e) coefficient k ₂ ＝0,k ₁ ≠0,k ₀ Not equal to 0, f (q) bipolar, (f) coefficient k ₂ ＝0,k ₁ ≠0,k ₀ =0,f (q) bipolar;

FIG. 2 is a graph of approximate variation of ω -l;

FIG. 3 shows a coefficient matrix K = K in a numerical simulation experiment 1 ₁ A time-voltage-current characteristic curve diagram, wherein, (a) is an input voltage time-domain waveform diagram, (b) is an output current time-domain waveform diagram, and (c) is a U-I curve;

fig. 4 is a comparison graph of characteristic curves formed by different excitation frequencies and amplitudes in the numerical simulation experiment 1, wherein (a) the input signal amplitude is 1V, (b) the input signal amplitude is 2V:

FIG. 5 is a comparison graph of hysteresis curves of different coefficients in the numerical simulation experiment 2, wherein (a) is coefficient matrix K = K ₂ And (b) is a coefficient k ₀ Magnification of 10 times, c) coefficient k ₁ Magnification of 10 times, (d) is coefficient k ₂ Amplifying by 10 times;

fig. 6 is a hysteresis loop diagram obtained by inputting different amplitude and frequency signals at sampling rates of 100MSa/s and 200GSa/s, respectively, in numerical simulation experiment 3, where (a) is a hysteresis loop diagram of five frequency signals at sampling rate of 100MSa/s and amplitude of 0.1V, (b) is a hysteresis loop diagram of five frequency signals at sampling rate of 100MSa/s and amplitude of 1V, (c) is a hysteresis loop diagram of five frequency signals at sampling rate of 100MSa/s and amplitude of 2V, (d) is a hysteresis loop diagram of five frequency signals at sampling rate of 200GSa/s and amplitude of 0.1V, (e) is a hysteresis loop diagram of five frequency signals at sampling rate of 200MSa/s and amplitude of 1V, and (f) is a hysteresis loop diagram of five frequency signals at sampling rate of 200MSa/s and amplitude of 2V;

FIG. 7 is a pinch-hysteresis plot based on oversampling, where (a) corresponds to a 500KHz sinusoidal input signal; (b) A sinusoidal input signal corresponding to 1MHz, (c) a sinusoidal input signal corresponding to 2 MHz;

FIG. 8 is a simulation of memristors with active characteristics in numerical simulation experiment 4, where (a) is a coefficient matrix K _4.0 Lower pinch hysteresis chart, (b) is coefficient matrix K _4.1 The lower pinch hysteresis chart (c) isCoefficient matrix K _4.2 A lower pinch hysteresis chart, and (d) a coefficient matrix K _4.3 Lower pinch hysteresis chart;

FIG. 9 is a graph comparing the effect of changing the coefficient K on the hysteresis loop area in the numerical simulation experiment 5, in which (a) is the coefficient matrix K _5.0 Lower pinch hysteresis chart, (b) is coefficient matrix K _5.1 Lower pinch hysteresis chart, (c) is coefficient matrix K _5.2 A lower pinch hysteresis chart, and (d) a coefficient matrix K _5.3 Lower pinch hysteresis chart;

FIG. 10 is a graph of the time domain waveforms and the comparison of the 200GSa/s and 100MSa/s parameters in the numerical simulation experiment 6, wherein (a) corresponds to 200GSa/s, (b) corresponds to 100MSa/, (c) is the combination of the two;

FIG. 11 is a schematic diagram of a specific embodiment of a real-time reconfigurable general memristor simulation circuit of the present invention;

FIG. 12 is a schematic diagram of one embodiment of the reconfigurable computing unit of FIG. 11;

FIG. 13 is a simulation timing diagram of a real-time reconfigurable universal memristor simulation circuit of the present invention;

fig. 14 is K = K ₀ And then, matlab software is adopted to realize a comparison graph of simulation results of the method, wherein (a) is a kneading hysteresis loop comparison graph, and (b) is an error local amplification comparison graph.

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

1. General mathematical model of memristor

Since professor zeisnia in 1971 deduces the constitutive relation of the memristor according to the circuit completeness theory, many scientists research the mathematical model of the memristor. The development of memristance was observed in the laboratory by the HP laboratory in 2008, and this finding realizes the advance of memristor mathematical models to physical implementation.

The memristor is essentially a nonlinear dynamical system, and a time-invariant x-controlled memristor system is also called a generalized memristor and is defined as:

where f (x (t), h) is a continuously bounded function with respect to an argument. Where x (t), y (t) are the input voltage (current) signal and the output current (voltage) signal of the generalized memristor system, respectively, f (h, m, t) represents the memristive value (memristance), h is the internal n-dimensional state variable,

is the time derivative of the state vector. If x = U (t), equation (1) is referred to as a generalized voltage controlled memristor. If x = I (t), then equation (1) is referred to as a generalized current-controlled memristor.

According to theorem 1, when f (x (t), h) is a polynomial function sequence f of order m _m (x (t), h) are consistent approximations, the generalized memristor model represented by equation (1) may be further expressed in the following form.

Wherein K = (K) ₀ ,k ₁ ,...,k _i ,...,k _m ) Is a coefficient matrix and K ≠ 0.h (x, t) represents a magnetic flux (charge amount), and h (t 0) represents an initial value of the magnetic flux (charge amount). The parameter α is the amplitude factor of y (t). When x (t) is a voltage (or a current), formula (2) represents a voltage-controlled memristor (or a current-controlled memristor). From the point of view of mathematical models, the two classes of memristors are only different in physical units of input variable x (t), output variable y (t) and system variable h (x, t). Therefore, for simplicity of expression, the present invention takes a voltage-controlled memristor model as an example for analysis, and fixes α =1.

Equation (2) is a continuous mode expression that presents a general mathematical model of memristors, andthe continuous model cannot be processed directly in a general-purpose digital processing circuit. At uniform time intervals T _s The formula (2) is quantized to obtain a corresponding memristor discrete model as follows:

wherein, T _s Is the step time, n is the time of day, and is the length of the digital integration window, k is the same for the expression form _i Re-note as k [ i ]]The other variables are consistent with equation (1). The discrete mathematical model of the 3 rd expression in formula (2) is the 3 rd expression of formula (3) according to the definition of Riemann Integral (Riemann Integral).

The riemann integral is defined as: function f (x) in a closed interval [ a, b ]]Has a definition in the interval [ a, b]Inserting n-1 points to divide them into n small regions [ x _i-1 ,x _i ]I =1,2,3,. Eta., n, arbitrarily take a point xi _i ∈[x _i-1 ,x _i ]The making and combining formula is as follows:

let λ be the maximum length between all cells, i.e. λ = max { Δ x ₁ ,Δx ₂ ,...,Δx _n }. When the segmentation becomes smaller, i.e., λ → 0, n → + ∞, each small bar after the segmentation can be regarded as a rectangle, considering the equation:

if the above formula value exists, and this limit is independent of the interval [ a, b ]]Is also independent of the point xi _i The method of (2) is said to be that the limit is f (x) in the interval [ a, b ]]The integral over, noted:

in practical engineering applications, an analog-to-digital converter (ADC) is used to sample the clock f _adc (1/f _adc ＝T _s ) To achieve uniform quantization of the continuous input signal x (t). When sampling clock f _adc The higher the frequency, the uniform time interval T _s The smaller. I.e. the segmentation step in the riemann integration becomes finer and finer. Setting FPGA system working clock to be f _FPGA . When equation (3) is implemented in an FPGA, if f _FPGA ≥f _adc And at the moment, the real-time calculation of the memristor model can be realized in the FPGA. When f is _FPGA ＜f _adc In the process, internal storage resources of the FPGA such as FIFO or an external memory such as DDR3 can be adopted, ADC quantized data are cached, and then hardware realization of the memristor model is carried out. According to the Nyquist sampling theorem there is f _adc ≥2f _in Therefore, the higher the sampling rate of the ADC, the larger the bandwidth of the input signal, and the larger the real-time data processing bandwidth in the FPGA.

2. General versatility of memristor general mathematical model

Weierstrass approximation theorem: let f (x) be [ a, b ]]The continuous function of (3) then exists as a polynomial function series { f _n (x) So that { f } _n (x) The x converges consistently to f (x). The following was demonstrated:

by definition of Bernstein polynomial, at [0,1], the error function satisfies:

since f (x) is ∈ C [0,1], so f (x) is bounded and consistently continuous over [0,1], given a positive number M, such that | f (x) | < M over [0,1], thus:

from f (x) in [0,1]It is continuously known that for any ε > 0, δ (ε) > 0 exists, such that when ε > 0

When the temperature of the water is higher than the set temperature,

splitting the formula (7) into two parts:

from the consistent continuity equation (9), we can derive:

then, the consistent bounded nature formula (8) is utilized when

When the utility model is used, the water is discharged,

therefore, when n satisfies

Then, from the equations (10) to (12), it can be found

This proves the first theorem of Weierstrass.

The taylor formula can approximately express a complex function f (x) as the sum of nth-order polynomial functions in a local part, and the taylor formula is a complicated and simple function, so that the taylor formula is a powerful tool for analyzing and researching a plurality of mathematical problems.

Taylor's formula: if the function f (x) includes x ₀ Has a certain opening range (a, b) ofWith a derivative of order (n + 1), then for any x e (a, b) there is:

wherein

Called Taylor polynomial of degree n, error term

Called the Taylor remainder of order n, with ε being x and x ₀ To some value in between.

If the derivative of the order N +1 of the function f (x) is at N (x) ₀ ) Upper bound, M, so that there is:

indicates R _n (x)＝o((x-x ₀ ) ⁿ ) In addition, it can also be demonstrated that for a fixed x, when n → ∞ R _n (x) → 0, i.e. to make f (x) and P _n (x) Error is reduced, then | x-x can be reduced ₀ If | is small, n may be large. In the Taylor equation of order n, if x ₀ =0, so that:

this equation is called the taylor equation of order n for the function f (x) at x =0, also called the Maclaurin (Maclaurin) equation of order n for f (x), the remaining terms being often written as o (x) ⁿ ) Or

Two forms, the remainder represented by the derivative of order n +1, lagrangian remainder, and o (x) ⁿ ) Or o ((x-x) ₀ ) ⁿ ) The remainder of the representation is called the Peano (Peano) remainder.

In the proposed memristor modelThe amplitude a and frequency ω of the input signal are known, so the range of values of h (t) is fixedly bounded. A polynomial fit can be used in conjunction with the Weierstrass first theorem f (h (t)). The taylor formula and the Maclaurin (Maclaurin) formula provide specific implementation methods of the m-order polynomial. The larger the value of the parameter m is, the higher the approximation accuracy of f (h (t)) is, and the higher the calculation complexity of f (h (t)) is. So when implemented in a general purpose processor such as an FPGA, a balance needs to be made in terms of accuracy, speed, and logic resources. For the discrete memristor model, the approximation may be made with equation (3). For example, when a is less than omega, the coefficient matrix K is approximated by a Maclaurin (Maclaurin) formula as shown in table 1. As can be seen from table 1, by configuring the coefficient matrix K = { K) not to be used _i The polynomial approximation to the common function memristive mathematical model can be realized.

TABLE 1

The proposed memristor model also exhibits good versatility to models in the existing literature. For example, in 2008, the HP team discovered a memristor model as shown in equation (17).

Where D is the thickness of the titanium dioxide film and w (t) is the thickness of the doped layer. By applying an external voltage, w (t) is also varied, R _on And R _off The minimum value (w (t) = D) and the maximum value (w (t) = 0) of the memristor resistance are separately accounted for. When the element K in the coefficient matrix K ₀ ＝R _off ，k ₁ ＝(R _on -R _off ) when/D, m =1, the proposed memristor model is the classic HP memristor model. In the same way, the universality of the coefficient matrix K and the polynomial coefficient m on other existing models is respectively configured as shown in the table 2, and the memristor model has compatibility with the existing models.

TABLE 2

3. The universality of the memristor model of the invention to active or passive memristors

The polarity of f (h (t)) in equation (1-2) is related to the values of the coefficient matrices K and h (t). To elaborate on the effect of each parameter on the q-f (q) curve, we chose a charge control memristor model at m =2 for detailed analysis, where q represents the magnetic flux. When m =2, the mathematical expression of f (q) is:

coefficient k ₁ 、k ₂ Cannot be 0 at the same time, otherwise the memristor would become a linear time invariant resistor. According to k ₀ ,k ₁ And k ₂ The values are different, and the q-f (q) curves have 24 graphs shown in the figure 1. As can be seen in FIG. 1, the curve q-f (q) may appear above, below, or at an intersection with the horizontal axis.

If a memristor is under the action of any zero direct current component periodic signal, the pinch hysteresis loop is only distributed in the first quadrant and the third quadrant, and the pinch hysteresis loop is called as passive. Otherwise, it is called active. The pinch-hysteresis line of the active memristor may not be zero-crossing. Because x (t) y (t) ≦ 0 when the hysteresis line falls in the second or fourth quadrant of the volt-ampere plane, the active memristor behaves like an energy source. In equation (2), the polarity of the independent variables f (q) and x (t) to the right of the equal sign determines the polarity of the dependent variable y (t) to the left of the equal sign. When a bipolar signal x (t) with zero DC component is inputted, the loop of the U-I plane has 3 cases as shown in Table 3. First, if f (q) is positive, the return line of the U-I plane passes through quadrant 1 and quadrant 3, when the proposed memristor belongs to a passive memristor. Second, if f (q) is negative, the return line of the U-I plane passes through the 2 nd and 4 th quadrants, and the proposed memristor belongs to an active memristor at this time. Third, if f (q) is bipolar, the return of the U-I plane passes through all quadrants, where the proposed memristor belongs to a local active memristor. The memristor models corresponding to curves (1), (2), (11) and curves (3), (4), (14) in fig. 1 belong to passive memristors and active memristors, respectively. And the memristor models corresponding to other curves are local active memristor models.

TABLE 3

4. Nonlinear characteristic analysis of memristor model

To verify the input signal bandwidth of the improved memristor mathematical model in equation (2), we performed theoretical bandwidth analysis using the cosine signal as input. Let the input signal be x (t) = acos (ω t), where a is the amplitude of the input signal and ω is the angular frequency of the input signal. Let the moment at which the signal starts to excite the system be t ₀ Also assume that x (t) is present ₀ )＝0，h(t ₀ ) And =0. The mathematical model for h (t) is as follows:

therein, there are

Because of the fact that

So we can easily calculate

Substituting equation (19) into equation (2), the expression for memristor h (t) is as follows:

substituting the formula (20) into the first expression of the formula (2), we can obtain the input-output signal expression of the memristor as follows:

in equation (22), the equation is represented by the linear term y with respect to x (t) ₁ (t) and the non-linear term y ₂ (t) composition. Wherein y is ₁ (t)＝k ₀ x(t)，

When k is ₀ When not equal to 0, in equation (22), the angular frequency ω of the input signal decreases at any time, then y ₂ The value of (t) will gradually increase, while the value of y (t) is dominated by the non-linear term y ₂ (t) determining. Conversely, as the frequency ω of the input signal increases, then y ₂ The value of (t) will gradually decrease to 0. The value of y (t) then depends primarily on the linear term y ₁ (t) size, and y ₁ (t) can be approximately understood as a standard linear device. For example, when the input is a voltage signal, y (t) is a standard admittance model.

Considering the practical application scenario, it is much easier to generate a higher frequency signal than a higher signal amplitude. For example, a common signal source can generate a sinusoidal signal with a frequency ω up to GHz, while the amplitude a is typically several tens of V. Thus, in equation (19) there is 0. Ltoreq. H (t). Ltoreq.1. Function (| h (t) |0 ^m (m.gtoreq.1) is a decreasing function with respect to the power exponent m, so that the coefficient k is varied ₀ The absolute value of (c), the amount of change in f (h (t)), and so onAnd maximum. Meanwhile, when n is more than or equal to 1, max { (| h (t) |) ^m H (t) | is less than or equal to the value of the equation. At coefficient k ₁ To k _m Of the m coefficients, the coefficient k is adjusted ₁ The amount of change in f (h (t)) can be maximized. In other words, to increase or decrease y rapidly ₂ (t) nonlinear characteristics, in practical engineering applications, we should adjust the coefficient k ₀ Or k ₁ The amount of change in (c). The other coefficients having the same variation amount hardly change the shape or area of the pinch curve.

There is a descending power formula according to the kerchien molefrees theorem (De Moivres theorem), and when m is an even number, there are:

when m is an odd number, there are:

and combining the product sum and difference formula of the trigonometric function:

from the formula (23) to the formula (25), the following expression holds in the formula (22). When m is an even number, there are:

when m is an odd number, there are:

according to the formula (26) and the formula (27), when the input is the single frequency signal x (t) = acos (ω t), the output signal y (t) is the input signal fundamental wave and each sub-harmonicSum of waves. Wherein the fundamental wave amplitude is ak ₀ ω, the amplitude of the individual harmonics is simultaneously subject to a polynomial coefficient k _i (i =1, m), the influence of m and a/ω.

Is provided with

Then there are:

the approximate change curve of ω -l is shown in fig. 2, and from the graph, we can find that when the angular frequency ω of the signal increases from 0 to infinity, the value of l decreases from large to small, and the mathematical model of equation (2) also changes from a nonlinear model to a linear model. In other words, it is the proposed memristor model that gradually changes from a nonlinear memristor (memristor) model to a linear resistance model as the angular frequency ω increases. Assuming that when the ratio l is less than or equal to the threshold δ, i.e., 0 < l ≦ δ, the improved memristor has become a resistive device. The value of δ can be selected according to the actual application to meet the accuracy requirement of the system.

In fig. 2, we refer to the input signal angular frequency ω for l = δ _max Referred to as the maximum theoretical bandwidth of the memristor. Therefore, to achieve the hysteretic loop characteristics of the memristor, the parameter settings must satisfy the constraints in equation (29).

The memory characteristics of the formula (29) for improving the improved memristor model include the following points: first, when k is ₀ Decrease of absolute value, k _i (i > 0) an increase in absolute value, an increase in the degree m of the polynomial, an increase in the amplitude a of the input sinusoidal signal or a decrease in the angular frequency ω, equation (2) more easily satisfies the nonlinear characteristics of the memristor. Secondly, when the input sinusoidal signal angular frequency ω is known, in order for the mathematical model of equation (2) to exhibit memristor behavior, we can increase the amplitude a of the input signal,increasing k _i (i > 0) absolute value or decreasing k ₀ The absolute value.

4. Commonality of proposed memristor model to broadband signals

According to the digital sampling principle, there are:

wherein f is _i And f _sap Respectively, the signal frequency and the sampling frequency. When the low frequency signal f is of the same amplitude _iL And a high frequency signal f _iH Using respective sampling rates of f _sL And f _sH The ADC of (1) quantizes and satisfies the constraint:

then there is a low sample rate quantized sequence x _L [n]And high sample rate quantized sequence x _H [n]The following relationship is satisfied:

x _L [n]＝x _H [n]。 (32)

let the corresponding coefficient matrixes in the two cases be K respectively _L And K _H . If the coefficient matrix K _L And K _H The constraint condition satisfying the formula (33) (i ∈ [0,m ]]) Then the hysteresis loop curve formed by the quantization of the low frequency samples and the quantization of the high frequency samples is exactly the same. The following was demonstrated:

k _iL ＝r ⁱ ·k _iH (33)

and (3) proving that: let r.f _iL ＝f _iH Then there is r ^-1 ·T _sL ＝T _sH . Wherein T is _sL And T _sH Are respectively f _sL And f _sH Corresponding to the sampling period. Further according to equation (3) there are:

h _L [n]＝r·h _H [n] (34)

wherein h is _L [n]And h _H [n]Are respectively f _sL And f _sH The corresponding magnetic flux. Further expanding equation (3) is:

f _L (h,m,n)＝k _0L +k _1L ·h _L [n]+...+k _iL ·(h _L [n]) ⁱ +k _mL ·(h _L [n]) ^m (35)

and

f _H (h,m,n)＝k _0H +k _1H ·h _H [n]+...+k _iH ·(h _H [n]) ⁱ +k _mH ·(h _H [n]) ^m (36)

substituting equations (33) - (34) into equation (35):

equation (36) and equation (37) are equal to the right, and therefore have:

f _L (h _L [n])＝f _H (h _H [n]) (38)

further, according to equation (3) there is:

y _L [n]＝y _H [n] (4)

so according to formula (32) and formula (39) there are: the hysteresis loop curve formed by the low-frequency sampling quantization and the high-frequency sampling quantization is the same. After the certification is completed!

According to the above conclusion, setting OSR =20, there is an input signal f _iH =10GHz and sampling rate f _sH Delay loop curve formed by =200GSPS and input signal f _iL =5MHz and sample rate f _sL =100MSPS form the hysteresis loop curve exactly the same. By configuring a polynomial coefficient K of the memristor model, the mathematical model with high frequency and high sampling rate is moved to low frequency and low sampling rate for processing and hardware verification, and the method has very important significance for engineering popularization and application of the memristor model. The reasons are mainly as follows: firstly, a GHz analog signal belongs to a microwave band high-frequency signal, parasitic parameters in the circuit have great influence on analog bandwidth and transmission of a signal circuit, the design and debugging difficulty of the analog circuit is very high, and most of the analog circuit is in theory unless professional companies with profound backgrounds can complete the realization of a hardware platformScientists reviewing the study are unable to perform hardware validation in the laboratory. Secondly, the sampling rate of the current commercial single-chip ADC can reach hundreds of GHz. Thirdly, the data bandwidth is rapidly increased due to the high sampling rate, and the back-end data processing FPGA cannot realize real-time operation. For example, the sampling rate real-time data bandwidth of 8bit 200GSPS reaches up to 200GSa/s, and the existing commercial FPGA cannot realize real-time operation.

5. Numerical simulation of improved memristor model

First, matlab is used to numerically simulate the proposed general mathematical model of memristors to prove the correctness of the proposed general mathematical model of memristors. We designed 6 numerical simulation experiments respectively, and the parameters and experimental results of each experiment are shown below.

Numerical simulation experiment 1

We set the polynomial coefficient matrix K ₁ ＝(-0.4,4e6,-1500,-1.25e-6,-3.125e-9)，m＝5，T _s =10ns. Consider the cosine excitation voltage signal amplitude a =1V and frequency f _i The time domain waveform curve obtained when =2MHz is shown in fig. 3. Fig. 3 (a) and (b) show time-domain waveforms of the input voltage x (t) and the output current y (t), respectively. FIG. 3 (c) depicts the characteristic curve of the improved memristor in the U-I plane, showing a typical pinch hysteresis loop.

The amplitudes (1V and 2V) and frequencies (1MHz, 2MHz,2.5MHz,5MHz and 10 MHz) of the cosine signals were changed again, and when the sampling rate was fixed at 100MSa/s, the simulation results were as shown in FIG. 4. Fig. 4 (a) and 4 (b) show a comparison of characteristic curves for different frequencies when the input signal amplitude is 1V and 2V, respectively. Obviously, with the increase of the excitation frequency, the area of the hysteresis loop is monotonously reduced, and the slope change of the hysteresis loop is gradually reduced to be more and more like a straight line. But the curve of the U-I plane is always a fixed hysteresis loop passing through the origin of coordinates and tightened at the origin. In addition, it can be seen from fig. 4 that: first, when the input signal amplitude is constant, the area of the hysteresis loop decreases with increasing frequency. Secondly, when the frequency of the input signal is constant, the area of the pinch hysteresis loop increases with increasing amplitude. Therefore, the area of the pinch hysteresis loop can be rapidly increased (reduced) by simultaneously increasing (reducing) the amplitude of the input signal or decreasing (increasing) the frequency of the input signal. Summarizing, the memristor model described in equation (2) may present fundamental features for identifying memristors.

Numerical simulation experiment 2

According to the formula (29), the coefficient k in the formula (2) _i Related to the hysteresis loop and the operating frequency bandwidth of the proposed memristor model. First, sinusoidal excitation voltages a =1V and f are set _i =5MHz, when the coefficient matrix K is ₂ In the case of = (1,5e6, 5e6,7,100,500,0, -10,0, 1), the hysteresis curve of the U-I plane is plotted as shown in fig. 5 (a). Then will respectively put k ₀ 、k ₁ And k ₂ The hysteresis curves are plotted as shown in FIGS. 5 (b) - (d), respectively, with 10-fold magnification. As can be seen from FIG. 5, increasing k ₀ The hysteresis loop will shrink to a linear function, where the linear portion of the memristor is larger. While increasing k ₁ The area of the hysteresis loop will increase, where the nonlinear portion of the memristor is relatively large. To increase k ₂ The area of the hysteresis loop is almost constant. This is consistent with the theoretical calculations of the second section.

Numerical simulation experiment 3

Setting coefficient matrixes as follows respectively:

K _3.0 ＝(-0.4,4*10^6,-1500,-1.26*10^-6,-20,0,0,0,0,0,0)

K _3.1 ＝(-0.40,8.0*10^9,-6*10^9,-10^4,-5*10^4,508,-1.25*10^5,-6*10^7,10^4,0,-200)

the sampling rates are 100MSa/s and 200GGSa/s, the amplitudes of the input signals are 0.1V,1V and 2V, and the frequencies of the simulation signals are 1MHz,2MHz,2.5MHz,50MHz,10MHz and 2GHz,4GHz,5GHz,10GHz and 20GHz respectively when the sampling frequencies are 100MSa/s and 200GSa/s respectively. The simulation results are shown in fig. 6. From the simulation results, it can be seen that: when the input signal amplitude is unchanged, the area of the pinch hysteresis loop decreases with increasing frequency. When the frequency of the input signal is constant, the area of the pinch hysteresis loop increases with increasing amplitude. Therefore, the area of the pinch hysteresis loop can be rapidly increased (reduced) by simultaneously increasing (reducing) the amplitude of the input signal or decreasing (increasing) the frequency of the input signal.

Keeping coefficient matrix K = K _2.0 The pinch-lag loops of the sinusoidal input signals with frequencies of 500KHz,1MHz and 2MHz at 10MSa/s,20MSa/s and 50MSa/s are shown in FIG. 7. The pinch-hysteresis loop is actually implemented by fitting a plurality of straight segments. The larger the number of piecewise linear functions, the smoother the curve. For example, when the oversampling rate is 10 (20), 10 (20) discrete data can be quantized for one signal period. The resulting hysteresis curve consisted of 9 (19) straight segments. The 9 (19) straight line segments may also be combined by 9 (19) piecewise linear functions. Compared with a discrete mathematical model method and a continuous mathematical model method, the piecewise linear function fitting method based on the Nyquist sampling theorem is simpler to realize, and the pinching hysteresis loop can be drawn only by setting a proper oversampling rate. The curves in fig. 6 also demonstrate the above conclusions.

Numerical simulation experiment 4

The experiment aims to set appropriate parameters so that the proposed memristive model can show abundant local active characteristics. The amplitude of the exciting sinusoidal voltage signal is 1V, and the frequency is 10Hz. The parameters of the matrix K are respectively set to K _4.0 ＝(0.9,-25,50)、K _4.1 ＝(0.9,-35,50)、K _4.2 = (-0.9, 25, 50) and K _4.3 (= -0.9,35,50). The hysteresis loops plotted in sequence are shown in fig. 8 (a) -8 (d). As can be seen from FIGS. 8 (a) - (b) (FIGS. 8 (c) - (d)), the coefficient k is increased ₁ The memristor is switched from a passive (active) memristor to a local active memristor. At the same time, the area of the hysteresis loop is also increased. Changing the coefficient k in comparison with FIG. 8 (a) and FIG. 8 (c) ₀ The switching from the passive memristor to the active memristor can be realized. In conclusion, the local active characteristics of the memristor can be easily and quickly enriched by changing the polarity and the absolute value of the coefficient matrix K in the formula (3). The correctness of the 3 rd section theoretical analysis is proved.

Numerical simulation experiment 5

The simulation parameters are as follows: m =10,T _s =1us, the amplitude and frequency of the input signal are 0.1V and 20KHz, respectively, set to:

K _5.0 ＝(10,10^5,10^5,10^5,7,100,500,0,-10^10,0,0)

K _5.1 ＝(10,10^6,10^5,10^5,7,100,500,0,-10^10,0,0)

K _5.2 ＝(10,10^5,10^6,10^5,7,100,500,0,-10^10,0,0)

K _5.3 ＝(10,10^5,10^5,10^6,7,100,500,0,-10^10,0,0)。

coefficient of sum K _5.0 In contrast (as shown in FIG. 9 (a)), at the coefficient K _5.1 ，K _5.2 And K _5.3 In (1), respectively adding k ₁ ，k ₂ And k ₃ The kneading hysteresis curves obtained by increasing the ratio by 10 are shown in FIGS. 9 (b), (c), and (d). From FIGS. 9 (a) - (d), we can clearly see the augmentation factor k ₁ The value of (2) can increase the area of the pinch hysteresis loop. While varying the coefficient k by the same order of magnitude ₂ And k ₃ The area of the pinch hysteresis loop is hardly affected, which also proves the correctness of the theoretical analysis.

Numerical simulation experiment 6

The simulation parameters are as follows: m =10.

The high sampling rate parameter configuration is as follows: f. of _sH ＝200GSa/s，T _sH ＝5ps，f _iH ＝20GHz，a＝1v，K _5.0 ＝(-0.4,8.0*10^9,-6*10^9,-10^4,-5*10^4,508,-1.25*10^5,-6*10^7,10^4,0,-200)。

The low sampling rate parameter configuration is as follows: f. of _sL ＝100MSa/s，T _sL ＝10ns，f _iL ＝1MHz，a＝1v，K _5.1 ＝(-0.4,8,-6*10^-9,-10^-23,-4*10^-5,5.08*10^-43,-1.25*10^-49,-6*10^-56,10^-68,0,-2*10^-88)。

The time-domain waveforms of the magnetic flux, the memory conductance, the pinch hysteresis loop, the input voltage and the output current obtained by simulation are shown in fig. 10. From fig. 10 we can see that all the simulation data are the same except for the magnetic flux. Therefore, when the coefficient matrix K satisfies the proportional relationship of the formula (33) and the oversampling ratio satisfies the formula (31), the pinch hysteresis loop formed by the high-frequency signal is identical to the pinch hysteresis loop formed by the low-frequency signal.

Through the numerical simulation experiment, the general memristor mathematical model provided by the invention can show an excellent shrinkage hysteresis loop. Notably, the improved memristor may exhibit a contracting hysteresis loop and appear anywhere in the coordinate region even at higher excitation frequencies by varying the different coefficients K.

FIG. 11 is a schematic diagram of a specific implementation mode of the real-time reconfigurable general memristor simulation circuit.

In this embodiment, as shown in fig. 11, the real-time reconfigurable general memristor simulation circuit is constructed based on an FPGA and includes a system state variable generation module 1, a calculation module 2, an FIFO3, and an output module 4.

The system state variable generation module 1 comprises a multiplier 101, an accumulator 102 and an adder 103, wherein the multiplier 101 completes input signals x [ n ]]Multiplying with the clock period Ts of the FPGA system to obtain Ts.x [ n ]]And output to the accumulator 102 for accumulation to obtain an accumulated value

And output to the adder 103 to obtain the system state variable h [ n ]]：

h 0 is the initial value of the system state variable, the input signal x n is a voltage signal or a current signal, and the system state variable h n is the magnetic flux or the amount of charge.

In this embodiment, a 48-bit adder is used to construct an accumulator for implementing the cumulative summation of the input signals x [ n ].

The computing module 2 composed of m reconfigurable computing units cascaded and operating in an m-stage pipeline mode is used for realizing m polynomial multiply-accumulate operations, as shown in fig. 11, each reconfigurable computing unit includes 2 multipliers 2011 2012, 1 adder 202 and 1D flip-flop 203.

As shown in fig. 12, for the i +1 th reconfigurable computing unit, i =0,1,2,. Ang., m-1, the inputs of which are respectively polynomial coefficients k [ i +1], adder 202 inputs s [ i ], first multiplier 2011 inputs are H [ i ] and d [ i ], outputs are respectively adder 202 output s [ i +1], second multiplier 2012 outputs H [ i +1] and input signal delay d [ i +1], and the mathematical relationship between the input signal and the output signal is:

the first multiplier 2011 multiplies the input H [ i ] and the input D [ i ] and outputs H [ i +1], the second multiplier 2012 multiplies the output H [ i +1] of the first multiplier 2011 by the polynomial coefficient k [ i +1], the adder 202 adds the input s [ i ] and the output k [ i +1]. H [ i +1] of the second multiplier 2012 and outputs s [ i +1], and the D flip-flop 203 delays the input D [ i ] by one sampling clock, so that the delay D [ i +1] of the input signal is obtained.

In that

let ε ₀ The polynomial order m should satisfy epsilon for acceptable maximum fitting error _M ≤ε ₀ 。

Wherein the coefficient k [ i ] of the ith order polynomial]，k _i I =0,1, 2.. Multidot.m, and the memory resistor mathematical model needing simulation, namely the memory conductance value or the memory resistance value f (h [ n ] at n moments) according to the Melaurin formula]) And (3) unfolding:

thus obtaining the product.

And the output s [ m ] of the mth reconfigurable computing unit is used as a memory conductance value or a memory resistance value f (h [ n ]) and is sent to an output module.

The FIFO3 is used to delay the input signal x [ n ] by 3m clock cycles and send it to the output module 4.

The output module 4 is composed of a multiplier, the input signal x [ n ] is multiplied by the memory conductance value or the memory resistance value f (h [ n ]) output by the calculation module after FIFO delay for 3m clock cycles to obtain the output signal y [ n ], and the output signal y [ n ] is a current signal or a voltage signal.

Function simulation

In order to fully evaluate the performance of the memristor model based on FPGA, namely the invention, a functional simulation experiment is carried out and compared with the existing method.

The Verilog hardware programming language, the software development environment Vivado 2020.1, and functional simulation software Xsim are used for hardware functional simulation of the proposed memristor model.

First, a 14-bit digital discrete sine signal with 4096 points in sign is generated using Matlab software. Meanwhile, the waveform sending module of the DDS principle is realized in the FPGA. By means of frequency control words K _f The sine wave with adjustable frequency can be output (the step value of the waveform ROM read address).

The coefficient matrix is:

K _1.0 ＝(0.4,-3.0*10^6,4.5*10^8,-10^2,1.5*10^6,50.8,-125,6,100,10,-200)。

sampling interval T _s =10ns. The FPGA simulation output data is in a double-precision floating point format so as to facilitate the comparison between hardware and software simulation results without analysis. The timing diagram of the hardware simulation is shown in fig. 13, and clk, rst _ n and ce in fig. 13 are respectively a system clock 100MHz, an active low reset signal and a module enable signal. The data dfx and dfy represent the input voltage signal and the output current signal of the memristor module, respectively. A dfx _ valid (dyx _ valid) being high indicates the output data dfx (dfy). Dfx _ valid and dyx _ valid are always high in the figure, which also proves that the proposed memristor module can realize real-time operation in the FPGA with the real-time operation speed of 12.8Gbps.

The double-precision floating point data output by the FPGA hardware simulation is imported into Matlab, and the pinch hysteresis loop line obtained by the Matlab software simulation is shown in fig. 14 (a). As can be seen, a hysteresis loop curve consists of 40 sampling rates, i.e. the oversampling is a multiple of 40. The error partial amplification for both implementations is shown in fig. 14 (b). The FPGA can complete data calculation of one period only in 400 ns.

Next, we linearly perform a 10-degree nonlinear polynomial in the FPGA to perform a fast reconfigurable experiment on 6 memristor models proposed in the prior literature, where the input parameters of the 6 memristor models and the frequency and amplitude (fixed 1V) of the input bipolar sinusoidal signal are shown in table 4.

We performed simulation experiments on the existing memristor model in the FPGA. Each model inputs a bipolar 1V sinusoidal signal. M =10 is fixed in the FPGA, polynomial coefficients, sampling rates, and input signal frequencies are configured as shown in table 4, and the obtained output signal amplitude and FPGA simulation time are shown in table 4. From table 4, we can find that the output amplitude of the proposed real-time reconfigurable memristor model is related to the input parameters.

TABLE 4

In table 4, the time required for one cycle of FPGA hardware implementation for different memristor models and different input signal frequencies is summarized (ignoring the fixed delay 390 ns). In Matlab, a data processing flow in an FPGA is simulated, specifically, fixed point number is converted into single-precision floating point number, and the single-precision floating point number is used for calculating magnetic flux and memory conductance. The time required to process the same amount of data as the FPGA is shown in table 4. From the table 4, it can be seen that, the real-time reconfigurable general memristor simulation circuit based on the method not only can simulate various existing memristor models, but also greatly reduces the calculation time compared with Matlab software simulation.

Although the illustrative embodiments of the present invention have been described in order to facilitate those skilled in the art to understand the present invention, it is to be understood that the present invention is not limited to the scope of the embodiments, and that various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined in the appended claims, and all matters of the invention using the inventive concepts are protected.

Claims

1. The utility model provides a real-time reconfigurable general memristor emulation circuit, characterized in that, based on FPGA construction, includes:

And output to the adder to obtain the system state variable h [ n ]]：

for the (i + 1) th reconfigurable computing unit, i =0,1, 2.. Multidot.m-1, the input of which is a polynomial coefficient k [ i +1], the adder input s [ i ], the first multiplier input is H [ i ] and d [ i ], the output is an adder output s [ i +1], the multiplier output is H [ i +1] and the input signal is delayed by d [ i +1], and the mathematical relationship between the input signal and the output signal is:

the first multiplier completes multiplication of input H [ i ] and D [ i ] and outputs H [ i +1], the second multiplier completes multiplication of output H [ i +1] of the first multiplier and polynomial coefficient k [ i +1], the adder completes addition of input s [ i ] and output k [ i +1]. H [ i +1] of the second multiplier and outputs s [ i +1], and the D trigger delays input D [ i ] by one sampling clock to obtain input signal delay D [ i +1];

for the 1 st reconfigurable computing unit, the input d [ i ] is the magnetic flux or the electric charge quantity at the time n, which is the system state variable H [ n ] output by the system state variable generating module, H [0] =1 is input, and s [ i ] = polynomial coefficient k [0] is input;

wherein, the number of the polynomial, namely the order m, is determined by adopting the following mode:

from the input signal x [ n ]]Respectively determining the amplitude and frequency of the zero DC component AC signal to determine the maximum amplitude a _max And minimum frequency ω _min Further determining the system state variable h [ n ]]Has a value range of

In that

Using the Maxolin formula to pair the memory conductance or resistance values f (h [ n ]]) Make an action on the system state variable h [ n ]]Is fitted to obtain a fitting function g (h (n)), wherein the maximum fitting error epsilon _M Comprises the following steps:

let ε ₀ The polynomial order m should satisfy epsilon for acceptable maximum fitting error _M ≤ε ₀ ；

Wherein coefficients k [ i ] of the ith order polynomial]，k _i I =0,1, 2.. Multidot.m, for the memristor mathematical model to be simulated, i.e. the memistor value or memistor value f (h [ n ] n) at n moments according to the meculine formula]) Unfolding:

obtaining;

a FIFO for delaying the input signal x [ n ] by m +39 clock cycles and sending to the output module;

and the output module is composed of a multiplier, the input signal x [ n ] is multiplied by the memory conductance value or the memory resistance value f (h [ n ]) output by the calculation module after FIFO delay of m +39 clock cycles to obtain an output signal y [ n ], and the output signal y [ n ] is a current signal or a voltage signal.