CN115221476A - Chip frame design method and system - Google Patents
Chip frame design method and system Download PDFInfo
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- CN115221476A CN115221476A CN202210718250.3A CN202210718250A CN115221476A CN 115221476 A CN115221476 A CN 115221476A CN 202210718250 A CN202210718250 A CN 202210718250A CN 115221476 A CN115221476 A CN 115221476A
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims abstract description 87
- 230000006399 behavior Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/12—Protecting executable software
- G06F21/121—Restricting unauthorised execution of programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/575—Secure boot
Abstract
The invention belongs to the field of electronic design, and particularly relates to a chip frame design method and a chip frame design system, wherein the method comprises the steps of determining user information of a chip; and configuring the peripheral address of the chip according to the user information. By determining the user information of the chip, the target client information of the chip can be determined so as to configure the peripheral address according to the information; by configuring the peripheral address of the chip, users of different chips cannot simply start the chip by recording the program, and the risk of illegal use of the program by other people can be reduced.
Description
Technical Field
The invention belongs to the field of electronic design, and particularly relates to a chip frame design method and a chip frame design system.
Background
Many electronic or mechanical devices require a controller to control their functions. The controller is generally a chip frame with a chip as a main body and keys, circuits, signal generators and other components as auxiliary components.
Due to the high development cost of the chip, the general chip can seek versatility to enlarge the potential customer layer. The other side of the hardware universality of the chip is that the program run by the chip is the link which really needs the next time of development. Some companies can read programs of other companies in the chip and then burn the programs on the same type of chip to be used as own products, and the action can have adverse effects on market competition. In the industry without technical barriers, competition among the same lines is strong, and places capable of saving cost are too few, so that the phenomenon of plagiarism is rare.
Disclosure of Invention
In order to solve or improve the above problems, the present invention provides a chip frame design method and system, and the specific technical solution is as follows:
the invention provides a chip frame design method, which is characterized by comprising the following steps: determining user information of the chip; and configuring the peripheral address of the chip according to the user information.
Preferably, the user information includes a user number; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and dividing and configuring the peripheral address of the chip according to the number of the users.
Preferably, the user information includes user requirements; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and configuring the peripheral address of the chip according to the user requirement.
Preferably, the configuring the peripheral address of the chip according to the user information includes: and configuring the value of an offset register according to the user information so as to configure the peripheral address of the chip.
Preferably, the configuring the peripheral address of the chip according to the user information includes: and opening bootloader configuration authority according to the user information so as to configure the peripheral address of the chip.
The invention provides a chip frame design system, comprising: a first unit for determining user information of the chip; and the second unit is used for configuring the peripheral address of the chip according to the user information.
Preferably, the user information includes a user number; correspondingly, the configuring the peripheral address of the chip according to the user information includes:
and dividing and configuring the peripheral addresses of the chips according to the number of the users.
Preferably, the user information includes user requirements; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and configuring the peripheral address of the chip according to the user requirement.
Preferably, the configuring the peripheral address of the chip according to the user information includes: and configuring the value of an offset register according to the user information so as to configure the peripheral address of the chip.
Preferably, the configuring the peripheral address of the chip according to the user information includes: and opening bootloader configuration authority according to the user information so as to configure the peripheral address of the chip.
The invention has the beneficial effects that: by determining the user information of the chip, the target client information of the chip can be determined so as to configure the peripheral address according to the information; by configuring the peripheral address of the chip, users of different chips cannot simply start the chip by recording the program, and the risk of illegal use of the program by other people can be reduced.
Drawings
FIG. 1 is a schematic diagram of a chip frame design method according to the present invention;
fig. 2 is a schematic diagram of a chip frame design system according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, fall within the scope of the present disclosure.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Bad enterprises can have bad influence on market competition by reading programs of other companies in the chip and then burning the programs on the chip of the same model to be used as own products. For example, in the application scheme of the current GPS positioning system, mostly one MCU manufactured by an intentional semiconductor, TM32F103 is used as a main control chip, and the design concept is to perform some slight changes on the basis of a prototype of the GPS positioning system developed by the intentional semiconductor to form different GPS positioning systems of each family. Each GPS positioning system production enterprise uses MCU of the same type, thus, GPS system manufacturers which enter the market can obtain programs of other GPS system manufacturers by various means; if a manufacturer who enters the market directly burns programs of other manufacturers into a public system, the product can be quickly put on the market. Because there is almost no research and development cost and the system functions are compatible with the current system functions, the market share of the original commodities of other manufacturers can be quickly eaten, and unfair competition is formed, so that the early system manufacturers with research and development capabilities are damaged.
In order to solve a part of the problems caused by the versatility of the chip, the invention provides a chip frame design method as shown in fig. 1, which is characterized by comprising the following steps: s1, determining user information of a chip; and S2, configuring the peripheral address of the chip according to the user information.
Customers wish to increase the protection of programs/code within the chip for the purpose of protecting their own intellectual property. As a supplier of chips, if the chip can meet the reasonable requirements of customers, the chip is helpful for improving the satisfaction degree of the customers, and simultaneously, the research atmosphere of the whole society can be improved by reducing the plagiarism behaviors.
Information of a client/user of the chip, i.e., user information, is acquired, and then a peripheral address of the chip is configured according to the user information, and then the chip is supplied to the corresponding user. The user information of the chip is set to describe the attribute and the label of a chip user different from other chip users, and the peripheral address of the chip is configured according to the attribute and the label of the chip user, so that the user receiving the chip and the chip can be ensured to be matched, and thus, other chip users cannot normally use the same program or burn the chip.
Even if the same MCU is configured into different address spaces, the peripheral addresses of the client A, the client B and the client C are different, and even if B takes the program data of A, C also takes the program data of A, B, the MCU cannot normally run on a product designed by the MCU. The same MCU produced by the same company but different client configurations cannot normally operate even if the MCU is taken to other households, and can be used for protecting programs and intellectual property rights of clients.
The user information comprises the number of users; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and dividing and configuring the peripheral addresses of the chips according to the number of the users.
The chip has a certain versatility for cost sharing, so that multiple users may be available for the same chip. The chip vendor sets the peripheral address to avoid theft for the purpose of preventing the chip's program from being used illegally. However, the peripheral addresses of the chip are not infinite, so that the peripheral addresses need to be divided, specifically, the peripheral addresses may be divided according to the number of users, for example, the peripheral addresses are evenly distributed. Further, the allocation may be based on specific attributes of the users, for example, a user purchases 10W chips, B user purchases 5W chips, and C user purchases 1W chip, so that a user may be considered as the largest client to allocate the most peripheral addresses. By dividing different peripheral addresses, the peripheral addresses can be matched with clients, and the possibility that programs of the chip are illegally used is reduced.
The user information includes user requirements; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and configuring the peripheral address of the chip according to the user requirement.
The chip has certain versatility for cost sharing, so that multiple users may be available for the same chip. The chip vendor sets the peripheral address to avoid theft for the purpose of preventing the chip's program from being used illegally. As a link of mutual cooperation, a chip supplier and a chip user can coordinate with each other, that is, the chip user can provide a certain requirement for the chip supplier, and the chip supplier configures a corresponding peripheral address of the chip according to the requirement of the chip user, so that the satisfaction of a customer can be improved, and the requirement provided by the customer is also the requirement obtained according to the purpose of the protection program of the customer, thereby helping to maintain the intellectual property of the program.
The configuring the peripheral address of the chip according to the user information comprises: and configuring the value of an offset register according to the user information so as to configure the peripheral address of the chip.
The Offset register can be used for configuring different values of the Offset register when an MCU (microprogrammed control Unit) original factory (namely a chip supplier) leaves a factory during bootloader, delivering the Offset register to different customers, and helping the different customers to protect various programs from the MCU original factory
The configuring the peripheral address of the chip according to the user information comprises: and opening bootloader configuration authority according to the user information so as to configure the peripheral address of the chip.
The client can also configure different offset addresses in the bootloader, so as to achieve the purpose of protecting own programs and intellectual property rights.
The present invention provides a chip frame design system as shown in fig. 2, including: a first unit 1 for determining user information of the chip; and the second unit 2 is used for configuring the peripheral address of the chip according to the user information.
Customers wish to increase the protection of programs/code within the chip for the purpose of protecting their own intellectual property. As a supplier of chips, if the chip can meet the reasonable requirements of customers, the chip is helpful for improving the satisfaction degree of the customers, and simultaneously, the research atmosphere of the whole society can be improved by reducing the plagiarism behaviors.
Information of a client/user of the chip, i.e., user information, is acquired, and then a peripheral address of the chip is configured according to the user information, and then the chip is supplied to the corresponding user. The user information of the chip is set to describe the attribute and the label of a chip user different from other chip users, and the peripheral address of the chip is configured according to the attribute and the label of the chip user, so that the user receiving the chip and the chip can be ensured to be matched, and thus, other chip users cannot normally use the same program or burn the chip.
Even if the same MCU is configured into different address spaces, the peripheral addresses of the client A, the client B and the client C are different, and even if B takes the program data of A, C also takes the program data of A, B, the MCU cannot normally run on a product designed by the MCU. The same MCU produced by the same company but different client configurations cannot normally operate even if the MCU is taken to other households, and can be used for protecting programs and intellectual property rights of clients.
The user information includes a user number; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and dividing and configuring the peripheral addresses of the chips according to the number of the users.
The chip has certain versatility for cost sharing, so that multiple users may be available for the same chip. The chip vendor sets the peripheral address to avoid theft for the purpose of preventing the chip's program from being used illegally. However, the peripheral addresses of the chip are not infinite, so that the peripheral addresses need to be divided, specifically, the peripheral addresses may be divided according to the number of users, for example, the peripheral addresses are evenly distributed. Further, the allocation may be based on specific attributes of the users, for example, a user purchases 10W chips, B user purchases 5W chips, and C user purchases 1W chip, so that a user may be considered as the largest client to allocate the most peripheral addresses. By dividing different peripheral addresses, the peripheral addresses can be matched with clients, and the possibility that programs of the chip are illegally used is reduced.
The user information includes user requirements; correspondingly, the configuring the peripheral address of the chip according to the user information includes: and configuring the peripheral address of the chip according to the user requirement.
The chip has certain versatility for cost sharing, so that multiple users may be available for the same chip. The chip vendor sets the peripheral address to avoid theft for the purpose of preventing the chip's program from being used illegally. As a link of mutual cooperation, a chip supplier and a chip user can coordinate with each other, that is, the chip user can provide a certain requirement for the chip supplier, and the chip supplier configures a corresponding peripheral address of the chip according to the requirement of the chip user, so that the satisfaction of a customer can be improved, and the requirement provided by the customer is also the requirement obtained according to the purpose of the protection program of the customer, thereby helping to maintain the intellectual property of the program.
The configuring the peripheral address of the chip according to the user information comprises: and configuring the value of an offset register according to the user information so as to configure the peripheral address of the chip.
The Offset register can be used for configuring different values of the Offset register when an MCU (microprogrammed control Unit) original factory (namely a chip supplier) leaves a factory during bootloader, delivering the Offset register to different customers, and helping the different customers to protect various programs from the MCU original factory
The configuring the peripheral address of the chip according to the user information comprises: and opening bootloader configuration authority according to the user information so as to configure the peripheral address of the chip.
The client can also configure different offset addresses in the bootloader, so as to achieve the purpose of protecting own programs and intellectual property rights.
The design idea of the scheme is as follows:
design of peripheral addresses involved in the original controller architecture (in the case of MCU-based):
SPI1_ADDRESS=（CPU_ADDRESS >=0x4000 3C00）&CPU_ADDRESS <=0x4000 3FFF）
RTC_ADDRESS=（CPU_ADDRESS >=0x4000 0000）&CPU_ADDRESS <=0x4000 03FF）。
design of peripheral addresses involved by the new MCU architecture:
SPI1_ADDRESS=（CPU_ADDRESS >=（0x4000 3C00+offset））&（CPU_ADDRESS <=（0x4000 3FFF+offset））
RTC_ADDRESS =（CPU_ADDRESS >=（0x4000 0000+offset））&（CPU_ADDRESS <=（0x4000 03FF+offset））。
(1) The Offset register is used for configuring different values of the Offset register when an MCU original factory (namely a chip supplier) leaves a factory during bootloader, and the Offset register is delivered to different clients, so that the MCU original factory helps the different clients to protect programs.
Different 3 customers:
the first client's offset register configuration =0x0000 \u0000;
the second client's offset register configuration = 0xn0002 \ u 0000;
the offset register configuration of the third client = 0xn0003 \ u 0000;
for example, the RTC address of the first client is 0x0000 \/u 0000_ -0 x0000 _/0 x03FF, and writing this address by the program configures the RTC of the clock chip. In case the program of the first client is stolen by the second client, the address is an invalid address for the MCU of the second client, and the clock chip RTC cannot be configured, so that the stolen program has no meaning. And vice versa, thereby protecting programs and intellectual property rights of different system manufacturers.
(2) Even the client can configure different offset addresses in the bootloader, so as to achieve the purpose of protecting own programs and intellectual property rights.
Those of ordinary skill in the art will appreciate that the elements of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components of the examples have been described above generally in terms of their functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present application, it should be understood that the division of a unit is only one logical function division, and in actual implementation, there may be another division manner, for example, multiple units may be combined into one unit, one unit may be split into multiple units, or some features may be omitted.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (10)
1. A chip frame design method, comprising:
determining user information of the chip;
and configuring the peripheral address of the chip according to the user information.
2. The chip frame design method according to claim 1, wherein the user information includes a user number;
correspondingly, the configuring the peripheral address of the chip according to the user information includes:
and dividing and configuring the peripheral address of the chip according to the number of the users.
3. The chip frame design method according to claim 1 or 2, wherein the user information includes user requirements;
correspondingly, the configuring the peripheral address of the chip according to the user information includes:
and configuring the peripheral address of the chip according to the user requirement.
4. The chip frame design method of claim 1, wherein the configuring the peripheral address of the chip according to the user information comprises:
and configuring the value of an offset register according to the user information so as to configure the peripheral address of the chip.
5. The chip frame design method of claim 1, wherein the configuring the peripheral address of the chip according to the user information comprises:
and opening bootloader configuration authority according to the user information so as to configure the peripheral address of the chip.
6. A chip frame design system, comprising:
a first unit for determining user information of the chip;
and the second unit is used for configuring the peripheral address of the chip according to the user information.
7. The chip frame design system of claim 6, wherein the user information includes a number of users;
correspondingly, the configuring the peripheral address of the chip according to the user information includes:
and dividing and configuring the peripheral addresses of the chips according to the number of the users.
8. The chip frame design system according to claim 6 or 7, wherein the user information comprises user requirements;
correspondingly, the configuring the peripheral address of the chip according to the user information includes:
and configuring the peripheral address of the chip according to the user requirement.
9. The chip frame design system of claim 6, wherein the configuring the peripheral address of the chip according to the user information comprises:
and configuring the value of an offset register according to the user information so as to configure the peripheral address of the chip.
10. The chip frame design system of claim 6, wherein the configuring the peripheral address of the chip according to the user information comprises:
and opening bootloader configuration authority according to the user information so as to configure the peripheral address of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210718250.3A CN115221476A (en) | 2022-06-23 | 2022-06-23 | Chip frame design method and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210718250.3A CN115221476A (en) | 2022-06-23 | 2022-06-23 | Chip frame design method and system |
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| CN115221476A true CN115221476A (en) | 2022-10-21 |
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| CN202210718250.3A Pending CN115221476A (en) | 2022-06-23 | 2022-06-23 | Chip frame design method and system |
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