CN115220564A

CN115220564A - Power consumption adjusting method and device, storage medium, processor and electronic equipment

Info

Publication number: CN115220564A
Application number: CN202110407899.9A
Authority: CN
Inventors: 王大宇
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2021-04-15
Filing date: 2021-04-15
Publication date: 2022-10-21

Abstract

The embodiment of the application discloses a power consumption adjusting method, a power consumption adjusting device, a storage medium, a processor and electronic equipment, wherein the power consumption adjusting method comprises the following steps: determining the delay requirement of task processing according to the current use scene; determining the system load within a preset time length taking the current time as the end time; determining a corresponding power consumption mode according to the delay requirement and the system load; the voltage and frequency of the processor are adjusted according to the power consumption mode to adjust the power consumption of the processor. According to the embodiment of the application, the voltage and the frequency of the power consumption mode automatic adjustment processor are determined according to the delay requirement and the system load, the automatic adjustment of the power consumption of the processor is realized through the automatic adjustment of the voltage and the frequency of the processor, and therefore the power consumption of the processor is effectively reduced on the premise that the normal work of the processor is guaranteed.

Description

Power consumption adjusting method and device, storage medium, processor and electronic equipment

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a power consumption adjustment method and apparatus, a storage medium, a processor, and an electronic device.

Background

The processor is an operation core and a control core of the product, and the performance of the processor directly influences the performance of the product. In the present day of the vigorous development of processor products, the performance of processors has become an important index for people to measure the quality of products, and along with the improvement of the requirements of people on the performance of related products, the improvement of the performance of processors becomes the direction of efforts of designers.

Designers currently employ various advanced techniques to design processors to improve their performance. However, as processor performance increases, its power consumption also increases significantly.

Disclosure of Invention

The embodiment of the application provides a power consumption adjusting method and device, a storage medium, a processor and an electronic device, which can reduce the power consumption of the processor.

The embodiment of the application provides a power consumption adjusting method, wherein the power consumption adjusting method comprises the following steps:

determining the delay requirement of task processing according to the current use scene;

determining the system load within a preset duration taking the current time as the end time;

determining a corresponding power consumption mode according to the delay requirement and the system load;

adjusting a voltage and a frequency of a processor according to the power consumption mode to adjust power consumption of the processor.

The embodiment of the present application further provides a power consumption adjusting device, where the power consumption adjusting device includes:

the delay determining module is used for determining the delay requirement of task processing according to the current use scene;

the load determining module is used for determining the system load within a preset time length taking the current time as the ending time;

the power consumption determining module is used for determining a corresponding power consumption mode according to the delay requirement and the system load;

and the power consumption adjusting module is used for adjusting the voltage and the frequency of the processor according to the power consumption mode so as to adjust the power consumption of the processor.

The embodiment of the present application further provides a storage medium, where the storage medium stores a computer program, and when the computer program runs on a computer, the computer is caused to execute the steps in any one of the power consumption adjusting methods provided in the embodiments of the present application.

The embodiment of the present application further provides a processor, configured to execute the steps in any one of the power consumption adjusting methods provided in the embodiments of the present application.

The embodiment of the present application further provides an electronic device, where the electronic device includes a processor and a memory, a computer program is stored in the memory, and the processor executes the steps in any one of the power consumption adjusting methods provided in the embodiment of the present application by calling the computer program stored in the memory.

In the embodiment of the application, firstly, the delay requirement of task processing is determined according to the current use scene; determining the system load within a preset duration taking the current time as the end time; then determining a corresponding power consumption mode according to the delay requirement and the system load; and adjusting the power consumption of the processor according to the voltage and the frequency of the processor in the power consumption mode. According to the embodiment of the application, the voltage and the frequency of the power consumption mode automatic adjustment processor are determined according to the delay requirement and the system load, the automatic adjustment of the power consumption of the processor is realized through the automatic adjustment of the voltage and the frequency of the processor, and therefore the power consumption of the processor is effectively reduced on the premise that the normal work of the processor is guaranteed.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic flowchart of a first power consumption adjusting method according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a processor cache according to an embodiment of the present disclosure.

Fig. 3 is a second flowchart of a power consumption adjustment method according to an embodiment of the present application.

Fig. 4 is a third flowchart schematic diagram of a power consumption adjusting method according to an embodiment of the present application.

Fig. 5 is a schematic flowchart of a temperature arbitration module according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of a first power consumption adjusting apparatus according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of a second power consumption adjusting apparatus according to an embodiment of the present application.

Fig. 8 is a schematic structural diagram of a first electronic device according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram of a second electronic device according to an embodiment of the present application.

Fig. 10 is a schematic structural diagram of an integrated circuit chip according to an embodiment of the present disclosure.

Detailed Description

The technical solution in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All embodiments obtained by a person skilled in the art based on the embodiments in the present application without any inventive step are within the scope of protection of the present application.

The terms "first," "second," "third," and the like in the description and claims of this application and in the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, or apparatus, processor, electronic device, system comprising a list of steps, or a list of modules or elements is not necessarily limited to those steps or modules or elements expressly listed, may include steps or modules or elements not expressly listed, and may include other steps or modules or elements inherent to such process, method, apparatus, processor, electronic device, or system.

The embodiment of the application provides a power consumption adjusting method which can be applied to a processor. The execution main body of the power consumption adjusting method may be the power consumption adjusting device provided in the embodiment of the present application, or a processor integrated with the power consumption adjusting device, where the power consumption adjusting device may be implemented in a hardware or software manner, and the processor may be configured in an electronic device such as a smart phone, a tablet computer, a palmtop computer, a notebook computer, or a desktop computer, or may be configured on an integrated circuit chip.

Referring to fig. 1, fig. 1 is a first flowchart illustrating a power consumption adjusting method according to an embodiment of the present disclosure. The execution subject of the power consumption adjusting method can be the power consumption adjusting device provided by the embodiment of the application, or a processor integrated with the power consumption adjusting device. The power consumption adjusting method provided by the embodiment of the application can comprise the following steps:

and 110, determining the delay requirement of task processing according to the current use scene.

In order to adjust the power consumption of a processor while guaranteeing the performance of the processor, it is necessary to make statistics on factors that affect the performance or power consumption of the processor. Latency is an important factor that affects processor performance.

Latency, i.e., clock latency, refers to the delay between the input data and the output result (the result of the data after a series of processing), e.g., the data is valid after 1 or more clocks relative to a certain clock start position. The delay is in clock units and determines the response speed of signal processing.

Delay requirements refer to how much delay a processor needs to respond to signal processing under a certain usage scenario. The delay requirement of the system is determined by the use scene of the system, the tasks corresponding to different use scenes are different, the delay requirement of the task processing requirement is different, and the use scenes of the system are various. In one embodiment, the current usage scenario needs to be obtained in real time, and the delay requirement of task processing is determined according to the current usage scenario.

For example, a user opens an application, and in order to ensure performance and avoid deadlock, the application needs to be opened in a very short time. Then the use scenario of "start application" requires fast processor response and low latency within this very short time. If the user is reading an electronic book, when the user reads a certain page but does not turn the page yet, the response speed of the processor does not affect the reading of the user, and at this time, low delay is not required for the use scene of 'reading the electronic book'.

Polling the current use scene at intervals, and determining the delay requirement of task processing according to the current use scene. The faster the demand, the lower the demand delay for the usage scenario of faster response speed.

In an embodiment, if a plurality of usage scenarios are found to be currently included after polling at a certain time, the delay requirement is determined according to the usage scenario with the lowest current delay requirement. For example, the screen may be in a split display state, and the user reads an electronic book in the first split display area and opens a new application in the second split display area. At this time, the current usage scenario includes both the usage scenario of "reading the electronic book" and the usage scenario of "opening the application", and the current delay requirement is determined to be a low delay requirement corresponding to the usage scenario of "opening the application", so that not only can the normal reading of the electronic book be ensured, but also the rapid opening of the application can be ensured.

And 120, determining the system load within a preset time length taking the current time as the end time.

The system load (workload) is the sum of the number of processes currently being executed by the processor and waiting to be executed by the processor, and is an important index reflecting the idle degree of the system. Since the processor incurs power consumption when executing a process, the system load is an important factor affecting the power consumption of the processor. The greater the system load, the greater the power consumption incurred.

The system load determined in the embodiments of the present application is the system load over a period of time. The period of time may be a preset time period with the current time as the end time. For convenience of description, the preset time period with the current time as the end time will be referred to as a preset time period hereinafter.

The system load of the preset time period is determined, namely the sum of the number of processes executed by the processor in the preset time period and waiting to be executed at the current time is determined.

In one embodiment, the system load may be calculated by adding a semaphore counter to the hardware, such as to predict the load of the processor for a predetermined period of time, and then a performance monitor may be added to the hardware processor to predict the system load. For example, when the processor accesses the cache, the counter is used to count the number of times of access of the processor, the number of times of access of the counter to the cache in a preset time period is obtained, an access count value of the preset time period is obtained, and the system load of the preset time period is obtained according to the access count value of the preset time period.

For example, the system load for a predetermined period of time is related to the frequency of processor accesses to the processor cache during the predetermined period of time.

A processor cache is a temporary storage between the processor and memory that is much smaller in capacity but faster in switching speed than memory. The data in the cache is a small part in the memory, but the small part is about to be accessed by the processor in a short time, and when the processor calls a large amount of data, the data can be called from the cache first, so that the reading speed is increased.

Referring to fig. 2, fig. 2 is a schematic diagram of a processor cache according to an embodiment of the present disclosure, where a process of data exchange between a processor and a cache and between a cache and a memory is shown. The processor cache can be divided into a first-level cache and a second-level cache according to the data reading sequence and the tightness degree of combination with the processor, part of the processor is also provided with three-level caches, and all data stored in each level of cache is part of the next-level cache. When a processor is going to read a datum, it first looks up from the first level cache, if it is not, then looks up from the second level cache, if it is, then looks up from the third level cache or the memory. The first level cache is the most important part of the whole processor cache architecture, and 80% of the whole data volume can be found in the first level cache. The data exchange speed between the processor and the first-level cache is the fastest of several data exchange modes.

The first-level cache is divided into a first-level instruction cache and a first-level data cache. The first level data cache is used for storing data, and the first level instruction cache is used for decoding instructions for executing the data, and the first level instruction cache and the second level instruction cache can be accessed by the processor at the same time.

In an embodiment, the number of times that the counter accesses the first-level instruction cache and the data cache in a preset time period may be obtained, so as to obtain an access count value in the preset time period, and obtain a system load in the preset time period according to the access count value in the preset time period.

In one embodiment, the load may also be calculated based on a ratio of idle to active time periods of the processor, such as a load of 1 when the processor is active for a predetermined time period, and a load of 0.5 when the processor is active for only 50% of the time for the predetermined time period. That is, the step of determining the system load for the preset time period may include:

the method comprises the steps that the idle time and the working time of a processor in a preset time period are obtained, the idle time is the time when the processor is in an idle state, the working time is the time when the processor is in a working state, when the processor processes tasks, the processor is in the working state, and when the processor finishes processing one task and does not receive the next task, the processor is in the idle state;

calculating to obtain the ratio of the idle time length to the working time length;

and determining the system load of a preset time period according to the ratio of the idle time length to the working time length.

And 130, determining a corresponding power consumption mode according to the delay requirement and the system load.

After the delay requirement and the system load in the preset time period are determined, the corresponding power consumption mode can be determined through table lookup. The table may be a first mapping table of power consumption modes and delay requirements, system load, defined in advance.

Referring to table 1, table 1 is a schematic diagram of a first mapping table provided in the embodiment of the present application.

Power consumption modes	Delay requirement, system load	Voltage of	Frequency of
				S1	L1、W1	V1	P1
S2	L2、W2	V2	P2
				S3	L3、W3	V3	P3
S4	L4、W4	V4	P4

TABLE 1

Table 1 shows 4 power consumption modes, S1, S2, S3 and S4, each corresponding to a combination of delay requirement and system load. The power consumption mode S1 corresponds to the delay requirement L1 and the system load W1, the power consumption mode S2 corresponds to the delay requirement L2 and the system load W2, the power consumption mode S3 corresponds to the delay requirement L3 and the system load W3, and the power consumption mode S4 corresponds to the delay requirement L4 and the system load W4.

Note that L1, W1, and the like may be not a specific numerical value but an interval. Wherein, L1, L2, L3, L4 are delay intervals, and W1, W2, W3, W4 are load intervals. When the delay interval in which the delay requirement is located is L1 and the load interval in which the system load in the preset time period is located is W1, determining that the corresponding power consumption mode is S1; when the delay interval where the delay requirement is located is L2 and the load interval where the system load in the preset time period is located is W2, determining that the corresponding power consumption mode is S2; and so on.

That is, the step of determining the corresponding power consumption mode according to the delay requirement and the system load in the preset time period may include:

determining a delay interval in which a delay requirement is located;

determining a load interval where a system load is located;

acquiring a preset first mapping table, wherein the first mapping table comprises corresponding relations between power consumption modes and delay intervals and between load intervals;

and determining the power consumption modes corresponding to the delay interval and the load interval according to the corresponding relation.

In one embodiment, the first mapping table is derived by training. The voltage and the frequency of the processor under different delay requirements and system loads can be collected in advance, the power consumption of the processor under different delay requirements and system loads is determined according to the voltage and the frequency of the processor, a plurality of power consumption modes are divided according to the power consumption, and then corresponding delay intervals and load intervals are determined for the divided power consumption modes.

And 140, adjusting the voltage and the frequency of the processor according to the power consumption mode to adjust the power consumption of the processor.

According to the training result, proper voltage and frequency can be set for different power consumption modes. When a certain power consumption mode is determined to be used, the voltage and the frequency corresponding to the power consumption mode are obtained, and the voltage and the frequency of the processor are adjusted to the voltage and the frequency corresponding to the power consumption mode.

Continuing to refer to table 1, according to table 1, when the delay interval of the delay requirement is L1 and the load interval of the system load is W1, determining that the corresponding power consumption mode is S1, adjusting the voltage of the processor to V1, and adjusting the frequency of the processor to P1; when the delay interval where the delay requirement is located is L2 and the load interval where the system load is located is W2, determining that the corresponding power consumption mode is S2, adjusting the voltage of the processor to be V1, and adjusting the frequency of the processor to be P1; and so on.

In an embodiment, the processor has different voltage steps and frequency steps, and when the voltage and the frequency of the processor are adjusted to the voltage and the frequency corresponding to the power consumption mode, the PMU may be controlled by software to switch the processor to the corresponding voltage step and frequency step. That is, the voltage and frequency (voltage and frequency corresponding to each power consumption mode) in the first mapping table are not values set at random, but correspond to the voltage step and frequency step of the processor, thereby facilitating adjustment. V1-V4 in Table 1 above may be the voltage steps of the processor, and P1-P4 may be the frequency steps of the processor.

Since the power consumption of the processor changes with the change of the voltage and the frequency, the higher the voltage or the higher the frequency means the higher the power consumption of the processor, and therefore, the adjustment of the power consumption of the processor can be realized by adjusting the voltage and the frequency of the processor.

It should be noted that the power consumption mode determined by the embodiment of the present application and the adjusted voltage and frequency are not fixed, but may change in real time according to the current practical situation. In an embodiment, the usage scenario and the system load in a preset time period are polled in real time every other preset time period, so as to switch to different power consumption modes at any time according to the usage situation, where the preset time period may be 1 second or shorter. For example, if the user reads an electronic book in the last second and starts a video application to watch a video in the next second, the processor finds that the current usage scene is changed from the previous preset time length compared with the system load through real-time polling, and accordingly switches the power consumption mode from S1 to S2 to balance performance and power consumption.

In an embodiment, the power consumption adjustment method provided by the present application may be implemented in a hardware manner, that is, the processor may be a hardware acceleration processor. Hardware acceleration processors have resorted to hardware acceleration techniques that allocate computationally expensive work to specialized hardware for processing to reduce the workload of the central processor. By implementing the power consumption adjusting method provided by the embodiment of the application in a hardware mode, high-speed power consumption adjusting processing can be realized.

The method described in the previous embodiment is described in further detail below.

Referring to fig. 3, fig. 3 is a second flowchart illustrating a power consumption adjusting method according to an embodiment of the present disclosure. The power consumption adjusting method can be applied to the processor provided by the embodiment of the application, and the power consumption adjusting method provided by the embodiment of the application can comprise the following steps:

201. the temperature of the processor is obtained.

In order to adjust the power consumption of a processor while guaranteeing the performance of the processor, it is necessary to make statistics on factors that affect the performance or power consumption of the processor. Where temperature is an important factor that can affect both processor performance and power consumption.

The processor has the limitation of the use temperature, the performance of the processor can be normally exerted within the normal use temperature, and when the temperature is too high, the processor can be forced to be shut down, so that the use is influenced. Therefore, the real-time temperature of the processor is acquired through the temperature sensor, and whether the voltage and the frequency of the processor are adjusted in any mode is determined according to the temperature.

202. It is determined whether the temperature of the processor is less than a temperature threshold. If yes, go to step 203. If not, go to step 210.

And acquiring a preset temperature threshold value, and judging whether the temperature of the processor is smaller than the temperature threshold value. Only when the temperature of the processor is less than the temperature threshold, the power consumption mode is determined according to the delay requirement and the system load, and the voltage and the frequency of the processor are correspondingly adjusted. And when the temperature of the processor is greater than or equal to the preset threshold, adjusting the voltage and the frequency of the processor according to the temperature of the processor.

203. And determining the delay requirement of task processing according to the current use scene.

Latency is also an important factor affecting processor performance.

Latency, i.e., clock latency, refers to the delay between the input data and the output result (the result after the data has undergone a series of processing), e.g., the data is valid after 1 or more clocks relative to the start of a clock. The delay is in units of clocks, and determines the response speed of signal processing.

Delay requirements refer to how much delay a processor needs in a certain usage scenario to respond to signal processing. The delay requirement of the system is determined by the use scene of the system, different use scenes correspond to different tasks, the delay requirement of the task processing requirement is different, and the use scene of the system is various. In an embodiment, when the temperature is less than the temperature threshold, the current usage scenario needs to be acquired in real time, and the delay requirement of the task processing is determined according to the current usage scenario.

For example, a user opens an application program, and in order to ensure performance and avoid the occurrence of jamming, the application program needs to be opened within a very short time. Then the use scenario of "start application" requires fast processor response and low latency within this very short time. If the user is reading the electronic book, when reading a certain page but not turning the page, the response speed of the processor does not affect the reading of the user, and at this time, the low delay is not required for the use scene of "reading the electronic book".

In one embodiment, if a plurality of usage scenarios are found to be currently included after polling at a certain time, the delay requirement is determined according to the usage scenario with the lowest current delay requirement. For example, the screen may be in a split-screen display state, and the user reads an electronic book in the first split-screen display area and opens a new application in the second split-screen display area. At this time, the current usage scenario not only includes a usage scenario of "reading an electronic book" but also includes a usage scenario of "opening an application program", and then it is determined that the current delay requirement is a low delay requirement corresponding to the usage scenario of "opening the application program", so that not only can the normal reading of the electronic book by the user be ensured, but also the rapid opening of the application program can be ensured.

204. And determining the system load within a preset time length taking the current time as the end time.

The system load (workload) is the sum of the number of processes currently being executed by the processor and waiting to be executed by the processor, and is an important index reflecting the idle degree of the system. Since the processor incurs power consumption when executing a process, the system load is an important factor that affects the power consumption of the processor. The greater the system load, the greater the power consumption incurred.

The system load determined in the embodiments of the present application is the system load over a period of time. The period of time may be a preset time period with the current time as the ending time, which is also called a preset time period. The system load of the preset time period is determined, namely the sum of the number of processes executed by the processor in the preset time period and waiting to be executed at the current time is determined.

In one embodiment, the system load may be calculated by adding a semaphore counter to the hardware, such as to predict the load of the processor for a predetermined period of time, and then a performance monitor may be added to the hardware processor to predict the system load. For example, when the processor accesses the cache, the counter is used to count the access times of the processor, the access times of the counter to the cache in a preset time period are obtained, an access count value of the preset time period is obtained, and the system load of the preset time period is obtained according to the access count value of the preset time period.

For example, the system load of the predetermined time period is related to the access frequency of the processor to the processor cache within the predetermined time period.

Referring to fig. 2, fig. 2 is a schematic diagram of a processor cache according to an embodiment of the present disclosure, which illustrates a data exchange process between a processor and a cache and between a cache and a memory. The processor cache can be divided into a first-level cache and a second-level cache according to the data reading sequence and the tightness degree of combination with the processor, part of the processor is also provided with three-level caches, and all data stored in each level of cache is part of the next-level cache. When a processor is going to read a datum, it first looks up from the first level cache, if it is not, then looks up from the second level cache, if it is, then looks up from the third level cache or the memory. The first level cache is the most important part of the whole processor cache architecture, and 80% of the whole data volume can be found in the first level cache. The data exchange speed between the processor and the first-level cache is the fastest of several data exchange modes.

the method comprises the steps that idle time and working time of a processor in a preset time period are obtained, the idle time is the time when the processor is in an idle state, the working time is the time when the processor is in a working state, when the processor processes tasks, the processor is in the working state, and when the processor finishes processing one task and does not receive the next task, the processor is in the idle state;

205. A delay interval in which the delay requirement is located is determined.

206. And determining a load interval in which the system load is positioned.

207. The method comprises the steps of obtaining a preset first mapping table, wherein the first mapping table comprises corresponding relations among power consumption modes, delay intervals and load intervals.

In one embodiment, the first mapping table is obtained by training. The voltage and the frequency of the processor under different delay requirements and system loads can be collected in advance, the power consumption of the processor under different delay requirements and system loads is determined according to the voltage and the frequency of the processor, a plurality of power consumption modes are divided according to the power consumption, corresponding delay intervals and load intervals are further determined for the divided power consumption modes, and the corresponding relation between the power consumption modes and the delay intervals and the load intervals is obtained.

It should be noted that the delay requirement and the system load included in the first mapping table may not be a specific value, but may be corresponding in an interval form.

208. And determining the power consumption modes corresponding to the delay interval and the load interval according to the corresponding relation.

Continuing to refer to the first mapping table shown in table 1, according to the corresponding relationship in the first mapping table, when the delay interval in which the delay requirement is located is L1 and the load interval in which the system load is located is W1, determining that the corresponding power consumption mode is S1; when the delay interval in which the delay requirement is located is L2 and the load interval in which the system load is located is W2, determining that the corresponding power consumption mode is S2; and so on.

209. And determining a corresponding power consumption mode according to the temperature of the processor.

And when the temperature of the processor is greater than or equal to the temperature threshold value, acquiring a second mapping table. The second mapping table is different from the first mapping table, and the corresponding relation between the temperature and the power consumption mode is reflected in the second mapping table. See also

Table 2, table 2 is a schematic diagram of a second mapping table provided in this embodiment of the present application.

Power consumption modes	Temperature of	Voltage of	Frequency of
				S5	T1	V5	P5
S6	T2	V6	P6
				S7	T3	V7	P7

TABLE 2

Table 2 shows power consumption modes corresponding to 3 temperatures, and voltages and frequencies in different power consumption modes. The power consumption mode corresponding to the temperature T1 is S5, the corresponding voltage is V5, the frequency is P5, the power consumption mode corresponding to the temperature T2 is S6, the corresponding voltage is V6, the frequency is P6, the power consumption mode corresponding to the temperature T3 is S7, the corresponding voltage is V7, and the frequency is P7.

Note that T1, T2, and T3 may not be specific numerical values, but may be intervals. When the temperature of the processor is greater than or equal to the temperature threshold, if the temperature interval where the temperature of the processor is located is T1, determining that the corresponding power consumption mode is S5; if the temperature interval of the temperature of the processor is T2, determining that the corresponding power consumption mode is S6; and if the temperature interval in which the temperature of the processor is located is T3, determining that the corresponding power consumption mode is S7.

210. The voltage and frequency of the processor are adjusted according to the power consumption mode to adjust the power consumption of the processor.

Referring to table 1 and table 2, according to the first mapping table provided in table 1, when the delay interval where the delay requirement is located is L1 and the load interval where the system load is located is W1, it is determined that the corresponding power consumption mode is S1, the voltage of the processor is adjusted to V1, and the frequency of the processor is adjusted to P1; when the delay interval where the delay requirement is located is L2 and the load interval where the system load is located is W2, determining that the corresponding power consumption mode is S2, adjusting the voltage of the processor to be V2, and adjusting the frequency of the processor to be P2; and so on.

According to a second mapping table provided by table 2, when the temperature interval in which the temperature is located is T1, it is determined that the corresponding power consumption mode is S5, the voltage of the processor is adjusted to V5, and the frequency of the processor is adjusted to P5; when the temperature interval in which the temperature is located is T2, determining that the corresponding power consumption mode is S6, adjusting the voltage of the processor to be V6, and adjusting the frequency of the processor to be P6; when the temperature interval in which the temperature is located is T3, the corresponding power consumption mode is determined to be S7, the voltage of the processor is adjusted to be V7, and the frequency of the processor is adjusted to be P7.

The second mapping table provided in table 2 may be preset by a developer according to the result of learning and training of the learning algorithm. In order to generate the second mapping table, the influence of different voltages and different frequencies on the performance of the processor when the temperature of the processor is unchanged can be evaluated in advance through a learning algorithm, so that suitable voltages and frequencies can be found for different temperatures. When the second mapping table is set, the temperature which is greater than or equal to the temperature threshold value is divided into temperature intervals, and appropriate voltage and frequency are set for the temperature intervals to correspond to the temperature intervals. When the voltage and the frequency of the processor are adjusted according to the temperature, the performance of the processor is not influenced, and the power consumption can be reduced as far as possible.

In an embodiment, the processor has different voltage steps and frequency steps, and when the voltage and the frequency of the processor are adjusted to the voltage and the frequency corresponding to the power consumption mode, the PMU can be controlled by software to switch the processor to the corresponding voltage step and frequency step. That is, the voltages and frequencies (voltages and frequencies corresponding to the respective power consumption modes) in the first and second mapping tables are not values set at random, but correspond to the voltage steps and frequency steps of the processor, thereby facilitating adjustment. V1 to V4 in table 1 and V5 to V7 in table 2 may be voltage steps of the processor, and P1 to P4 in table 1 and P5 to P7 in table 2 may be frequency steps of the processor.

Referring to fig. 4, fig. 4 is a third flowchart illustrating a power consumption adjusting method according to an embodiment of the present disclosure.

In an embodiment, the power consumption adjusting method provided by the embodiment of the application is applied to a hardware acceleration processor, and is matched with a main processor to adjust the voltage and the power of the processor.

Wherein the main processor first identifies the current usage scenario. This step can be performed in the host processor, since the calculations involved in identifying a scene are relatively complex. After the main processor identifies the current use scene, the main processor informs the hardware acceleration processor of which use scenes are currently available through data transmission with the hardware acceleration processor. A delay determining module in the hardware acceleration processor determines the delay requirement of task processing according to the current use scene, meanwhile, a load determining module determines the system load within a preset time length taking the current time as the end time, and the two modules jointly initiate a voltage and frequency switching request to a power management module. The power management module comprises a power consumption determining module and a power consumption adjusting module, wherein the power consumption determining module receives a voltage and frequency switching request, determines a corresponding power consumption mode according to the delay requirement determined by the delay determining module and the system load determined by the load determining module, and sends the determined power consumption mode to the power consumption adjusting module. The power consumption adjusting module adjusts the voltage and the frequency of the processor according to the power consumption mode so as to adjust the power consumption of the processor.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a working flow of a temperature arbitration module according to an embodiment of the present disclosure.

In addition to the above modules, the hardware acceleration processor may further include a temperature arbitration module. The working mode of the temperature arbitration module is as follows: the temperature acquisition system acquires the temperature of the processor according to the parameter change of the temperature sensor and inputs the acquired temperature of the processor into the temperature arbitration module. After the temperature arbitration module acquires the temperature of the processor, whether the temperature of the processor is smaller than a temperature threshold value or not is judged, and a judgment result is transmitted to the power management module, and the power management module determines the voltage and frequency regulation mode according to the temperature judgment result.

And when the judgment results of the temperatures are different, the adjustment modes of the voltage and the frequency are different. When the temperature of the processor is less than the temperature threshold, the voltage and frequency of the processor are adjusted according to the delay requirement and the system load in the manner described above. And when the temperature of the processor is greater than or equal to the temperature threshold, adjusting the voltage and the frequency of the processor according to the temperature. The specific adjustment manner is described in detail in the foregoing embodiments, and is not described in detail herein.

As can be seen from the above, in the power consumption adjustment method provided in the embodiment of the present application, the delay requirement of task processing is determined according to the current usage scenario; determining the system load within a preset duration taking the current time as the end time; then determining a corresponding power consumption mode according to the delay requirement and the system load; and further adjusting the voltage and frequency of the processor according to the power consumption mode to adjust the power consumption of the processor. According to the embodiment of the application, the voltage and the frequency of the power consumption mode automatic adjustment processor are determined according to the delay requirement and the system load, and the power consumption of the processor is automatically adjusted through the automatic adjustment of the voltage and the frequency of the processor, so that the power consumption of the processor is effectively reduced on the premise of ensuring the normal work of the processor. In addition, a temperature condition can be added, and the voltage and the frequency of the processor are adjusted together by combining three angles of system load, delay requirement and temperature, so that the purposes of optimal use of system resources and maximum saving of power consumption are achieved.

The embodiment of the application also provides a power consumption adjusting device. Referring to fig. 6, fig. 6 is a schematic view illustrating a first structure of a power consumption adjusting apparatus according to an embodiment of the present disclosure. Wherein the power consumption adjusting apparatus 300 is applicable to a processor, the power consumption adjusting apparatus 300 includes a delay determining module 301, a load determining module 302, a power consumption determining module 303, and a power consumption adjusting module 304, as follows:

a delay determining module 301, configured to determine a delay requirement of task processing according to a current usage scenario;

a load determining module 302, configured to determine a system load within a preset duration taking a current time as an end time;

a power consumption determining module 303, configured to determine a corresponding power consumption mode according to the delay requirement and the system load;

and a power consumption adjusting module 304, configured to adjust the voltage and the frequency of the processor according to the power consumption mode, so as to adjust the power consumption of the processor.

In an embodiment, when determining the system load within the preset duration with the current time as the end time, the load determining module 302 may be configured to:

when the processor accesses the cache, counting the access times of the processor;

acquiring the access times of the processor to the cache within a preset time length with the current time as the finishing time to obtain an access count value;

and obtaining the system load within the preset time length by taking the current time as the end time according to the access count value.

acquiring idle time and working time of a processor in preset time by taking the current time as an ending time, wherein the idle time is the time when the processor is in an idle state, the working time is the time when the processor is in a working state, when the processor processes a task, the processor is in the working state, and when the processor finishes processing one task and does not receive the next task, the processor is in the idle state;

and determining the system load within the preset time length by taking the current time as the ending time according to the ratio of the idle time length to the working time length.

In an embodiment, when determining the corresponding power consumption mode according to the delay requirement and the system load, the power consumption determining module 303 may be configured to:

determining a delay interval in which a delay requirement is located;

determining a load interval where a system load is located;

In an embodiment, the first mapping table further includes a voltage and a frequency corresponding to a preset power consumption mode, and when the voltage and the frequency of the processor are adjusted according to the power consumption mode, the power consumption adjusting module 304 may be configured to:

acquiring voltage and frequency corresponding to a power consumption mode;

the voltage and frequency of the processor are adjusted to the voltage and frequency corresponding to the power consumption mode.

Referring to fig. 7, fig. 7 is a schematic diagram of a second structure of a power consumption adjusting device 300 according to an embodiment of the present disclosure. In an embodiment, the power consumption adjusting apparatus 300 further includes a temperature arbitration module 305, and the temperature arbitration module 305 is configured to:

acquiring the temperature of a processor;

it is determined whether the temperature of the processor is less than a temperature threshold.

When determining the corresponding power consumption mode according to the delay requirement and the system load, the power consumption determining module 303 may be configured to:

and when the temperature of the processor is less than the temperature threshold value, determining a corresponding power consumption mode according to the delay requirement and the system load.

When the temperature of the processor is greater than or equal to the temperature threshold value, determining the corresponding power consumption mode according to the temperature of the processor.

The above modules can be implemented in the foregoing embodiments, and are not described in detail herein.

As can be seen from the above, in the power consumption adjusting apparatus provided in the embodiment of the present application, first, the delay determining module 301 determines the delay requirement of task processing according to the current usage scenario; the load determining module 302 determines the system load within a preset duration taking the current time as the end time; then, the power consumption determining module 303 determines a corresponding power consumption mode according to the delay requirement and the system load; the power consumption adjustment module 304, in turn, adjusts the voltage and frequency of the processor according to the power consumption mode to adjust the power consumption of the processor. According to the embodiment of the application, the voltage and the frequency of the power consumption mode automatic adjustment processor are determined according to the delay requirement and the system load, the automatic adjustment of the power consumption of the processor is realized through the automatic adjustment of the voltage and the frequency of the processor, and therefore the power consumption of the processor is effectively reduced on the premise that the normal work of the processor is guaranteed.

The embodiment of the application also provides the electronic equipment. The electronic device may be a smartphone, a tablet computer, a gaming device, an AR (Augmented Reality) device, an automobile, a vehicle peripheral obstacle detection apparatus, an audio playback apparatus, a video playback apparatus, a notebook, a desktop computing device, a wearable device such as a watch, glasses, a helmet, an electronic bracelet, an electronic necklace, an electronic garment, or the like.

Referring to fig. 8, fig. 8 is a schematic view of a first structure of an electronic device 400 according to an embodiment of the present disclosure. The electronic device 400 comprises, among other things, a processor 401 and a memory 402. The memory stores a computer program, and the processor executes the steps of any one of the power consumption adjusting methods provided by the embodiments of the present application by calling the computer program stored in the memory. The processor 401 is electrically connected to the memory 402.

The processor 401 is a control center of the electronic device 400, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and processes data by running or calling a computer program stored in the memory 402 and calling data stored in the memory 402, thereby performing overall monitoring of the electronic device.

In this embodiment, the processor 401 in the electronic device 400 may load instructions corresponding to one or more computer program processes into the memory 402 according to the steps in the power consumption adjustment method, and the processor 401 executes the computer program stored in the memory 402, so as to implement the steps in the power consumption adjustment method, such as:

determining the system load within a preset time length taking the current time as the end time;

the voltage and frequency of the processor are adjusted according to the power consumption mode to adjust the power consumption of the processor.

Referring to fig. 9, fig. 9 is a schematic structural diagram of an electronic device 400 according to an embodiment of the present disclosure. Wherein, the electronic device 400 further comprises: a display 403, a control circuit 404, an input unit 405, a sensor 406, and a power supply 407. The processor 401 is electrically connected to the display 403, the control circuit 404, the input unit 405, the sensor 406, and the power source 407.

The display screen 403 may be used to display information input by or provided to the user as well as various graphical user interfaces of the electronic device, which may be made up of images, text, icons, video, and any combination thereof.

The control circuit 404 is electrically connected to the display 403, and is configured to control the display 403 to display information.

The input unit 405 may be used to receive input numbers, character information, or user characteristic information (e.g., a fingerprint), and generate a keyboard, mouse, joystick, optical, or trackball signal input related to user setting and function control. For example, the input unit 405 may include a touch sensing module.

The sensor 406 is used to collect information of the electronic device itself or information of the user or external environment information. For example, the sensors 406 may include a plurality of sensors such as a distance sensor, a magnetic field sensor, a light sensor, an acceleration sensor, a fingerprint sensor, a hall sensor, a position sensor, a gyroscope, an inertial sensor, an attitude sensor, a barometer, a heart rate sensor, and the like.

The power supply 407 is used to power the various components of the electronic device 400. In some embodiments, the power supply 407 may be logically coupled to the processor 401 via a power management system, such that the power management system may perform functions of managing charging, discharging, and power consumption.

Although not shown in fig. 8 and 9, the electronic device 400 may further include a camera, a bluetooth module, and the like, which are not described herein again.

In this embodiment, the processor 401 in the electronic device 400 may load instructions corresponding to processes of one or more computer programs into the memory 402 according to the steps in the translation method, and the processor 401 executes the computer program stored in the memory 402, so as to implement the steps in the power consumption adjustment method, for example:

In one embodiment, when determining the corresponding power consumption mode according to the delay requirement and the system load, the processor 401 performs the following steps:

determining a delay interval in which a delay requirement is located;

determining a load interval where a system load is located;

acquiring a preset first mapping table, wherein the first mapping table comprises corresponding relations between power consumption modes and delay intervals and load intervals;

In an embodiment, the first mapping table further includes a voltage and a frequency corresponding to a preset power consumption mode, and when the voltage and the frequency of the processor are adjusted according to the power consumption mode, the processor 401 executes the following steps:

acquiring voltage and frequency corresponding to a power consumption mode;

In one embodiment, processor 401 further performs the following steps:

the temperature of the processor is obtained.

When determining the corresponding power consumption mode according to the delay requirement and the system load, the processor 401 performs the following steps:

and when the temperature of the processor is smaller than the temperature threshold value, determining a corresponding power consumption mode according to the delay requirement and the system load.

And when the temperature of the processor is greater than or equal to the temperature threshold value, determining the corresponding power consumption mode according to the temperature of the processor.

In one embodiment, in determining the system load within the preset duration with the current time as the end time, the processor 401 performs the following steps:

and obtaining the system load within the preset duration taking the current time as the end time according to the access count value.

acquiring the idle time and the working time of the processor within a preset time period taking the current time as an ending time, wherein the idle time is the time period when the processor is in an idle state, the working time is the time period when the processor is in a working state, when the processor processes a task, the processor is in the working state, and when the processor finishes processing one task and does not receive the next task, the processor is in the idle state;

As can be seen from the above, an embodiment of the present application provides an electronic device, where a processor in the electronic device performs the following steps: firstly, determining the delay requirement of task processing according to the current use scene; determining the system load within a preset time length taking the current time as the end time; then determining a corresponding power consumption mode according to the delay requirement and the system load; and further adjusting the voltage and the frequency of the processor according to the power consumption mode so as to adjust the power consumption of the processor. According to the embodiment of the application, the voltage and the frequency of the power consumption mode automatic adjustment processor are determined according to the delay requirement and the system load, and the power consumption of the processor is automatically adjusted through the automatic adjustment of the voltage and the frequency of the processor, so that the power consumption of the processor is effectively reduced on the premise of ensuring the normal work of the processor.

The embodiment of the application also provides an integrated circuit chip. The integrated circuit chip can be used for smart phones, tablet computers, game equipment, AR (Augmented Reality) equipment, automobiles, vehicle peripheral obstacle detection devices, audio playing devices, video playing devices, notebooks, desktop computing equipment, wearable equipment such as watches, glasses, helmets, electronic bracelets, electronic necklaces and the like.

In one embodiment, the integrated circuit chip provided by the embodiment of the present application adopts a hardware acceleration technique, and allocates a very large amount of computation work to special hardware for processing, so as to reduce the workload of the central processing unit. The processor provided by the embodiment of the present application may be integrated in such an integrated circuit chip, and the power consumption adjustment method provided by the embodiment of the present application may be implemented in a hardware acceleration manner, so as to implement high-speed power consumption adjustment processing.

Referring to fig. 10, fig. 10 is a schematic structural diagram of an integrated circuit chip 500 according to an embodiment of the present disclosure. Integrated circuit chip 500 includes a processor 501 and a power consumption adjustment device 300. The processor 501 is electrically connected to the power consumption adjusting apparatus 300.

Processor 501 is the control center for integrated circuit chip 500 and connects various portions of the entire integrated circuit chip using various interfaces and lines.

In this embodiment, the power consumption adjusting apparatus 300 may be responsible for implementing the steps in the power consumption adjusting method described above, so as to adjust the power consumption of the processor 501, for example:

The embodiment of the present application further provides a processor, which may be applied to the integrated circuit chip or the electronic device provided in the embodiment of the present application, and is responsible for implementing the steps in the power consumption adjustment method, for example:

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects.

That is, when the processor provided in the embodiment of the present application implements the steps in the power consumption adjusting method, the processor may be implemented in a hardware manner, a software manner, or a combination of the two manners. For example, the processor may be a main processor in the electronic device, and the steps in the power consumption adjusting method described above are implemented by calling a computer program in a memory of the electronic device. Alternatively, the processor may also be a hardware acceleration processor in an integrated circuit chip, and the steps in the power consumption adjustment method are implemented in a hardware manner by using a hardware acceleration technology.

It should be noted that, all or part of the steps in the methods of the above embodiments may be implemented in software functional modules and sold or used as independent products through a computer program to instruct related hardware to complete, and the computer program may be stored in a computer readable storage medium, including but not limited to: a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic or optical disk, and the like.

That is, an embodiment of the present application further provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer executes the power consumption adjusting method of any one of the above embodiments.

For example, in some embodiments, when the computer program is run on a computer, the computer performs the steps of:

In the above embodiments, the descriptions of the embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed description of the translation method, and are not described herein again.

The power consumption adjusting method, the power consumption adjusting device, the storage medium, the processor, and the electronic device provided in the embodiments of the present application are described in detail above. The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A method for adjusting power consumption, comprising:

2. The method of claim 1, wherein determining the corresponding power consumption mode according to the latency requirement and the system load comprises:

determining a delay interval in which the delay requirement is located;

determining a load interval where the system load is located;

3. The method according to claim 2, wherein the first mapping table further includes a voltage and a frequency corresponding to a preset power consumption mode, and the adjusting the voltage and the frequency of the processor according to the power consumption mode includes:

acquiring voltage and frequency corresponding to the power consumption mode;

and adjusting the voltage and the frequency of the processor to the voltage and the frequency corresponding to the power consumption mode.

4. The method of claim 1, wherein determining the corresponding power consumption mode according to the latency requirement and the system load comprises:

5. The power consumption adjustment method according to claim 4, wherein the method further comprises:

and when the temperature of the processor is greater than or equal to the temperature threshold value, determining a corresponding power consumption mode according to the temperature of the processor.

6. The power consumption adjustment method according to claim 1, wherein the determining the system load within the preset duration with the current time as the end time comprises:

when a processor accesses a cache, counting the access times of the processor;

acquiring the access times of the processor to the cache within a preset time length taking the current time as the finishing time to obtain an access count value;

7. The power consumption adjustment method according to claim 1, wherein the determining the system load within the preset duration with the current time as the end time comprises:

acquiring idle time and working time of the processor within preset time with the current time as an ending time, wherein the idle time is the time when the processor is in an idle state, the working time is the time when the processor is in a working state, when the processor processes a task, the processor is in the working state, and when the processor finishes processing one task and does not receive the next task, the processor is in the idle state;

and determining the system load in a preset time length taking the current time as the ending time according to the ratio of the idle time length to the working time length.

8. A power consumption adjustment apparatus, comprising:

9. A storage medium, having stored therein a computer program which, when run on a computer, causes the computer to execute the steps in the power consumption adjustment method according to any one of claims 1 to 7.

10. A processor for performing the steps in the power consumption adjustment method of any one of claims 1 to 7.

11. An electronic device, comprising: a processor and a memory, the memory having a computer program stored therein, the processor performing the steps in the power consumption adjustment method of any one of claims 1 to 7 by calling the computer program stored in the memory.