CN115208839A

CN115208839A - Data transmission system, method and device

Info

Publication number: CN115208839A
Application number: CN202110378029.3A
Authority: CN
Inventors: 陈玉杰; 郑述乾
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2022-10-18

Abstract

A data transmission system, method and device are used for flexibly realizing service data transmission. The system comprises: at least one source switching network interface circuit, at least one switching device, and a plurality of destination switching network interface circuits. The first source switching network interface circuit maps the first service data flow to a plurality of first data frames, and the destination address field of each first data frame comprises a load balancing domain; sending a plurality of first data frames to a first switching device according to a balancing sequence, wherein one element in the balancing sequence is inserted into a load balancing domain corresponding to each first data frame, the number of the elements in the balancing sequence is related to the number of first connecting channels, and the number of the first connecting channels is the number of the connecting channels between the first switching device and a first destination switching network interface circuit; the first switching equipment sends a plurality of first data frames to a first destination switching network interface circuit; the first destination switching network interface circuit sequences and de-encapsulates the plurality of first data frames to obtain a first service data stream.

Description

Data transmission system, method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data transmission system, method, and apparatus.

Background

At present, a dedicated switching chip is mostly used for a switching network of a Time Division Multiplexing (TDM) communication device, such as a Synchronous Digital Hierarchy (SDH) device or an Optical Transport Network (OTN) device. For example, an application-specific integrated circuit (ASIC) chip, etc. The TDM communication equipment realizes TDM service switching through a special switching chip. The special exchange chip needs to be specially customized, and the investment cost is high. And the internal protocol of the exchange chip is privatized, and various manufacturers can not exchange, so that the equipment application is limited, and the service data transmission can not be flexibly realized.

Disclosure of Invention

The application provides a data transmission method and device, which are used for flexibly realizing service data transmission.

In a first aspect, the present application provides a data transmission system. The system may include: at least one source switched network interface circuit, at least one switching device, and a plurality of destination switched network interface circuits. The first source switching network interface circuit maps the first service data stream to a plurality of first data frames, and a destination address field of each of the plurality of first data frames includes a load balancing domain for realizing load balancing of the first switching device. The first source switch network interface circuit sends the plurality of first data frames to the first switch device according to an equalization sequence. Wherein the load balancing field corresponding to each of the plurality of first data frames is interpolated with one element in the balancing sequence. The number of elements in the equalization sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit. The first switching device sends the plurality of first data frames to the first destination switching network interface circuit; and the first destination switching network interface circuit sequences the plurality of first data frames, and decapsulates the sequenced plurality of first data frames to obtain the first service data stream. The first source switching network interface circuit is any one of the at least one source switching network interface circuit, the first switching device is one or more of the at least one switching device, and the first destination switching network interface circuit is any one of the plurality of destination switching network interface circuits.

It should be understood that, when the first source switching network interface circuit sends the multiple first data frames to the first switching device according to the balancing sequence, the first source switching network interface circuit needs to determine, when sending a data frame, a destination switching device to send according to an element of the balancing sequence carried in a load balancing domain included in the data frame. That is, the first source switched network interface circuit transmits the first data frame according to the elements of the equalization sequence.

In the data transmission system, when the source exchange network interface circuit sends a data frame, an element in a balancing sequence is inserted into a load balancing domain of the data frame, so as to realize load balancing of the switching device. Therefore, the processing flow of the switching equipment does not need to be changed, so that the balanced distribution of the service data can be realized by adopting the universal switching equipment, the dependence of a data transmission system on a special chip can be avoided, the data transmission is more flexible, the interchange of various manufacturers can be realized, and the application is wide.

In a possible design, when the first switching device is a single-stage switching device, the number of elements in the equalization sequence is related to the number of the first connection channels, which may specifically be: the number of elements in the equalization sequence is equal to the number of first connection channels. Therefore, the exchange equipment can accurately realize the balanced transmission of the plurality of first data frames through the balancing sequence. In another possible design, when the first switch device is an N-stage switch device, the number of the first connection channels is the number of connection channels between the first switch device and the first destination switch network interface circuit, and specifically may be: the first number of the connection channels is the number of the connection channels between the nth stage switching device in the first switching device and the first destination switching network interface circuit. Further, the number of elements in the equalization sequence is related to the number of the first connection channels, which may specifically be: the number of elements in the equalization sequence is equal to a first value, and the first value is a common multiple of the number of the connection channels between each two stages of the N-stage switching devices and the number of the first connection channels. Wherein N is an integer greater than or equal to 2. Therefore, the exchange equipment can accurately realize the balanced transmission of the plurality of first data frames through the balancing sequence. In one possible design, the common multiple may be the smallest common multiple. Therefore, the implementation is simple, and the complexity is reduced.

In one possible design, the dropped element of the load balancing field corresponding to each of the plurality of first data frames is associated with a receiving port of the first destination switching network interface circuit. After a first data frame is inserted with an element, the value of the destination address field of the first data frame corresponds to the receiving port of the first destination switching network interface circuit. This allows accurate load balancing of the first switching device.

In a possible design, the load balancing field corresponding to each of the plurality of first data frames is interpolated by one element in the balancing sequence, which may specifically be: h first data frames in each first data frame in the first P groups of first data frames are respectively and sequentially inserted into elements in the equalization sequence; and the first Q elements in the equalization sequence are sequentially inserted into the Q first data frames in the (P + 1) th group of first data frames respectively. Wherein H is equal to the number of elements in the equalized sequence, P is an integer quotient of T divided by H, Q is a remainder of T divided by H, and T is the number of the first data frames. H is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H. Therefore, one element in the balancing sequence can be successfully inserted in the load balancing domain corresponding to each first data frame, and the implementation method is simple.

In one possible design, the source address field of each of the plurality of first data frames includes a first field to indicate an ordering of each of the plurality of first data frames. Before the first source switching network interface circuit sends the first data frames to a first switching device according to an equalization sequence, the first source switching network interface circuit interpolates a timestamp or a sequence number in a first domain corresponding to each of the first data frames according to a set sequence. Therefore, the service data frames can be kept in sequence, so that the service data flow can be accurately recovered subsequently. Illustratively, the set order may be an increasing order or the like.

In a possible design, the first destination switching network interface circuit may sequence the plurality of first data frames, and specifically may: and the first destination switching network interface circuit sequences the plurality of first data frames according to the time stamp or the sequence number in the first domain corresponding to each first data frame. This allows the first destination switch network interface circuit to accurately recover the traffic data stream. Illustratively, the first destination switched network interface circuit may incrementally order the plurality of first data frames according to a timestamp or sequence number in a first domain to which each of the first data frames corresponds.

In one possible design, at least one of the switch devices is a Local Area Network (LAN) switch (LSW) switch chip. Therefore, the universal Ethernet switching chip can be adopted to realize service data transmission, the realization is simple, and the data transmission is more flexible.

In a second aspect, the present application provides a data transmission method. The method can comprise the following steps: and mapping the first service data stream to a plurality of first data frames, wherein the destination address field of each first data frame of the plurality of first data frames comprises a load balancing domain, and the load balancing domain is used for realizing load balancing of the first switching equipment. And sending the plurality of first data frames to the first switching equipment according to the equalization sequence. Wherein the load balancing field corresponding to each of the plurality of first data frames is interpolated with one element in the balancing sequence. The number of elements in the equalization sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit. The method and the device can realize balanced distribution of the service data of the first exchange device, have flexible data transmission, can realize interchange of various manufacturers, and have wide application.

In a possible design, when the first switch device is a single-stage switch device, for specific description about the number of elements in the equalization sequence and the number of the first connection channels, reference may be made to the description in the possible design of the first aspect, and details are not repeated here.

In a possible design, when the first switch device is an N-stage switch device, the description of the specific scheme may refer to the description in the possible design of the first aspect, and details are not repeated here.

In a possible design, for a description of an element, in which a load balancing domain corresponding to each of the plurality of first data frames is inserted, reference may be made to the description in the possible design of the first aspect, and details are not repeated here.

In a possible design, the description of the source address field of each of the first data frames may be the description of the source address field in the possible design of the first aspect, and the description is not repeated here.

In a third aspect, the present application further provides a data transmission apparatus. The data transmission apparatus has a function of implementing the method in the second aspect described above or each of the possible design examples of the second aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.

In one possible design, the data transmission device includes a transceiver unit and a processing unit. These units may perform corresponding functions in the second aspect or each possible design example of the second aspect, which is specifically described in detail in the method example, and details are not repeated here.

In one possible design, the data transmission device includes a communication interface and a processor in its structure. Optionally, the data transmission device further comprises a memory. The communication interface is used for receiving and transmitting data and is used for carrying out communication interaction with other equipment in the data transmission system. The processor is configured to enable the data transmission apparatus to perform the corresponding functions in the second aspect or each possible design example of the second aspect. The memory is coupled to the processor and holds the program instructions and data necessary for the data transmission means.

In a fourth aspect, an embodiment of the present application provides a data transmission system. The data transmission system may include at least one source switching network interface circuit (e.g., a first source switching network interface circuit), at least one switching device (e.g., a first switching device), and a plurality of destination switching network interface circuits (e.g., a first destination switching network interface circuit, etc.) as mentioned above.

In a fifth aspect, embodiments of the present application provide a computer-readable storage medium. The computer-readable storage medium stores program instructions that, when executed on a computer, cause the computer to perform the method as described in the second aspect of the embodiments of the present application and any possible design thereof. By way of example, computer readable storage media may be any available media that can be accessed by a computer. Take this as an example but not limiting: a computer-readable medium may include a non-transitory computer-readable medium, a random-access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a CD-ROM or other optical disk storage, a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In a sixth aspect, embodiments of the present application provide a computer program product comprising computer program code or instructions. When run on a computer, cause the computer to carry out a method as set out in the second aspect or any one of the possible designs of the second aspect.

For each of the third to sixth aspects and possible technical effects of each aspect, please refer to the description of the possible technical effects for each possible solution in the first or second aspect, and no repeated description is given here.

Drawings

Fig. 1 is a schematic structural diagram of an OTN device provided in the present application;

fig. 2 is a schematic diagram of an architecture of a data transmission system provided in the present application;

FIG. 3 is a block diagram of another data transmission system according to the present application;

fig. 4 is a schematic diagram of an architecture of another data transmission system provided in the present application;

fig. 5 is a schematic structural diagram of a first data frame provided in the present application;

fig. 6 is a schematic diagram illustrating a first service data flow mapped to a plurality of first data frames according to the present application;

fig. 7 is a schematic diagram illustrating a completion location of service encapsulation/decapsulation in a data transmission system according to the present application;

FIG. 8 is a schematic diagram of a location where equalization is required according to the present application;

fig. 9 is a schematic diagram illustrating equalization processing of a unicast service provided in the present application;

fig. 10 is a schematic diagram illustrating an equalization position in a multi-stage multi-plane switching system according to the present application;

fig. 11 is a schematic diagram of an equalization process of a multi-stage switching device according to the present application;

FIG. 12 is a schematic diagram of an order preserving service provided by the present application;

FIG. 13 is a flow chart of a data transmission method provided herein;

fig. 14 is a schematic structural diagram of a data transmission device provided in the present application;

fig. 15 is a schematic structural diagram of another data transmission device provided in the present application.

Detailed Description

The present application will be described in further detail below with reference to the accompanying drawings.

The embodiment of the application provides a data transmission method and device, which are used for flexibly realizing service data transmission. The method and the device are based on the same technical concept, and because the principle of solving the problems of the method and the device is similar, the implementation of the device and the method can be mutually referred, and repeated parts are not described again.

In the description of the present application, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order.

In the description of the present application, "at least one" means one or more, and a plurality means two or more.

The data transmission method provided by the embodiment of the application can be applied to a communication system formed by data exchange equipment and the like. The communication system may be, but is not limited to, a data transmission system, a data switching system (network), an optical transmission network, a time division multiplexing system, etc. For example, in an optical transport network, the data switching device may be an Optical Transport Network (OTN) device. Fig. 1 is a schematic structural diagram of a possible OTN device. Illustratively, an OTN device may include a branch board, a line board, a cross board, and a system control and communication board, and may further include a power supply, a fan, an auxiliary board, and an optical layer processing board (not shown in fig. 1). It should be noted that, according to specific needs, the type and number of the single boards specifically included in each OTN device may be different. For example: OTN devices that are core nodes may not have a tributary board. An OTN device as an edge node may have multiple tributary boards. The power supply is used for supplying power to the OTN device, and may include an active power supply and a standby power supply. The fan is used for radiating heat for the equipment. The auxiliary single board is used for providing an external alarm or accessing an external clock and other auxiliary functions. The branch board, the cross board and the circuit board are mainly used for processing electric layer signals of the OTN. The branch circuit board is used for receiving and transmitting various client services, such as Synchronous Digital Hierarchy (SDH) service, packet service, ethernet service, and forwarding service. Further, the branch board may be divided into a client side optical module and a signal processor. The client side optical module may be an optical transceiver for receiving and/or transmitting traffic data. The signal processor is used for realizing mapping and demapping processing of the service data to the data frame. The cross board is used for realizing the exchange of data frames and completing the exchange of one or more types of data frames. The circuit board mainly realizes the processing of the data frame at the line side. Specifically, the wiring board may be divided into a line side optical module and a signal processor. The line-side optical module may be a line-side optical transceiver configured to receive and/or transmit data frames. The signal processor is used for realizing multiplexing and demultiplexing or mapping and demapping processing of data frames on the line side. The system control and communication single board is used for realizing system control and communication. Specifically, information may be collected from different boards through a backplane, or a control instruction may be sent to a corresponding board. It should be noted that, unless specifically stated otherwise, a specific component (e.g., a signal processor) may be one or more, and this application is not intended to be limiting. It should also be noted that, in the embodiments of the present application, no limitation is imposed on the types of the single boards included in the device, and the specific functional designs and numbers of the single boards.

At present, most of switching networks such as OTN devices use dedicated switching chips. For example, ASIC chips and the like, that is, OTNs and other devices implement service switching through a dedicated switching chip. However, the proprietary switch chip needs to be customized specially, so that the investment cost is high, the internal protocol of the switch chip is privatized, and manufacturers cannot interchange, so that the equipment application is limited, and the service data transmission cannot be realized flexibly. Based on this, the embodiments of the present application provide a data transmission system, method and apparatus. The method is used for realizing that equipment of each manufacturer can be universal and flexibly realize service data transmission.

Fig. 2 illustrates a data transmission system according to an embodiment of the present application. The data transmission system may include at least one source switched network interface circuit, at least one switching device, and a plurality of destination switched network interface circuits. Exemplarily, in fig. 2, at least one source switched network interface circuit is illustrated with a source switched network interface circuit 1 and a source switched network interface circuit 2. At least one switching device is shown with switching device 1 and switching device 2. The plurality of destination switch network interface circuits are illustrated as a destination switch network interface circuit 1, a destination switch network interface circuit 2, and a destination switch network interface circuit 3. It should be noted that the number of the source switch network interface circuit, the switch device, and the destination switch network interface circuit shown in fig. 2 is only an example, and is not intended to limit the data transmission system of the present application.

The source switching network interface circuit may be referred to as an uplink switching network interface circuit. For example, the uplink switch network interface circuit may be an uplink interface circuit (FIC) or the like. The destination switched network interface circuit may be referred to as a downstream switched network interface circuit. Such as a downlink FIC, etc. The switching device may be a chip. For example, the ethernet switch chip may be a general ethernet switch chip, such as a Local Area Network (LAN) switch chip (LSW) switch chip, etc. The switching device may also be a stand-alone device, which is not limited in this application.

In one embodiment, the switching devices in the data transmission system may be single stage switching devices. For example, in the data transmission system shown in fig. 3, the switching devices are a plurality of single-stage LSW switching chips, the source switching network interface circuit is an upstream FIC, and the destination switching network interface circuit is a downstream FIC. The data transmission system shown in fig. 3 can also be referred to as a single-stage multi-plane switching system, and a large-capacity switching system is constructed by extending multiple planes by using a general ethernet switching chip.

In another embodiment, the switching devices in the data transmission system may be multi-stage switching devices. For example, in the data transmission system shown in fig. 4, the switching device is taken as a multi-stage LSW switching chip, the source switching network interface circuit is taken as an uplink FIC, and the destination switching network interface circuit is taken as a downlink FIC. The data transmission system shown in fig. 4 can also be referred to as a multi-stage multi-plane switching system, and the system capacity is further expanded on the basis of the single-stage multi-plane switching system shown in fig. 3 by cascading multi-stage switching chips.

It should be noted that the numbers of the upstream FIC, the LSW switch chip, and the downstream FIC in fig. 3 and 4 are merely examples, and are not intended to limit the present application.

Service distribution, switching, equalization, etc. may be implemented by the data transmission systems shown in fig. 2 to 4. Specifically, a specific process of sending the service data (exemplified by the first service data stream) to any destination switching network interface circuit (exemplified by the first destination switching network interface circuit) through one or more switching devices (exemplified by the first switching device) by any source switching network interface circuit (exemplified by the first source switching network interface circuit) may be as follows:

the first source switch network interface circuit maps the first traffic data stream to a plurality of first data frames, the destination address field of each of the plurality of first data frames including a load balancing field. The load balancing domain is used for realizing the load balancing of the first switching equipment. The first source-switched network interface circuit may transmit a plurality of first data frames to the first switching device according to the equalization sequence. And the load balancing domain corresponding to each first data frame of the plurality of first data frames is inserted with one element in the balancing sequence. The number of elements in the equalization sequence is related to the number of first connection channels, which is the number of connection channels between the first switching device and the first destination switching network interface circuit. The first switching device sends the first plurality of data frames to the first destination switched network interface circuit. The first destination switching network interface circuit sequences the plurality of first data frames, and decapsulates the sequenced plurality of first data frames to obtain a first service data stream.

For example, the data structure of the traffic data stream map in the embodiment of the present application may be a general ethernet frame structure. That is, the structure of each of the plurality of first data frames may be a common ethernet frame structure. For example, the structure of the first data frame may be as shown in fig. 5. In the present application, the meaning of a Destination Address (DA) field and a Source Address (SA) field in an ethernet frame is redefined. Wherein the source switched network interface circuit and the destination switched network interface circuit process the data according to the redefined meaning of the DA field and the SA field. The switching device processes the data according to the current meaning of the DA field and the SA field in the ethernet frame. That is, the meaning of the DA field and the SA field is not redefined for the switching device, and the switching device can process data using the existing processing flow. This avoids changes to the processing flow of the current switching device.

Specifically, as shown in fig. 5, for unicast traffic, the redefined DA field may include a Multicast (MC) field, a Reserved (RES) field, a destination switch network interface circuit identification (DFIC _ ID) field, and a Load Balance (LB) field. For example, for unicast traffic, the specific meaning of the redefined DA field may be as shown in table 1. For multicast traffic, the redefined DA field may include an MC field, an RES field, a Multicast Identity (MID) field, and an LB field. For example, for multicast traffic, the specific meaning of the redefined DA field may be as shown in table 2. The redefined SA field may include a RES field, a source switch network interface circuit identification (SFIC _ ID) field, a FLOW identification (FLOW _ ID) field, and a timestamp _ serial number (TS _ SN) field. For example, the specific meaning of the redefined SA field may be as shown in table 3.

Table 1 specific meanings of redefined DA fields for unicast traffic

Domain name	Ethernet DA bit field	Description of the meanings
			MC	DA[47]	Unicast and multicast indication, 0 for unicast traffic and 1 for multicast traffic
RES	DA[46:16]	Reserved field
			DFIC_ID	DA[15:6]	Destination FIC, destination FIC for unicast service switching
LB	DA[5:0]	A load balancing field for realizing load balancing of the switching device

As can be seen from table 1, for the unicast traffic, the allocation of 48 bits occupied by the DA field (i.e., DA [47: the LB field occupies the first 6 bits, i.e., 0-5 bits, of the DA field. The DFIC _ ID field occupies the 7 th bit to the 16 th bit, i.e., 6-15 bits, of the DA field. The RES field occupies the 17 th bit to the 47 th bit, i.e., 16-46 bits, of the DA field. The MC field occupies the last bit (48 th bit), i.e. 47 bits, of the DA field.

Table 2 specific meanings of redefined DA fields for multicast traffic

Domain name	Bit field	Description of the preferred embodiments
			MC	DA[47]	Unicast and multicast indication, 0 for unicast traffic and 1 for multicast traffic
RES	DA[46:23]	Reserved field
			MID	DA[22:6]	Multicast ID, multicast service group number, for distinguishing different multicast groups
LB	DA[5:0]	A load balancing field for realizing load balancing of the switching device

As can be seen from table 2, for the multicast service, the allocation of 48 bits occupied by the DA field (i.e., DA [47: the LB field occupies the first 6 bits, i.e., 0-5 bits, of the DA field. The MID field occupies the 7 th bit to the 23 rd bit, i.e., 6-22 bits, of the DA field. The RES field occupies the 24 th bit to the 47 th bit, i.e., 23-46 bits, of the DA field. The MC field occupies the last bit (48 th bit), i.e. 47 bits, of the DA field.

TABLE 3 concrete meanings of redefined SA fields

As can be seen from table 3, the allocation of the 48 bits occupied by the SA field (i.e., SA [47: the TS _ SN field occupies the first 20 bits, i.e., 0-19 bits, of the SA field. The FLOW _ ID field occupies 21 st to 36 th bits, i.e., 20-35 bits, of the SA field. The SFIC _ ID field occupies the 37 th bit to the 46 th bit, i.e., 36-45, of the SA field. The RES field occupies the last two bits (47 th and 48 th bits), i.e., 46-47 bits, of the SA field.

The load balancing field included in the destination address field of each of the plurality of first data frames is the LB field included in the DA field in table 1 or table 2. The source address field of each of the plurality of first data frames includes a first field, which is the TS _ SN field included in the SA field in table 2.

The process of mapping the first service data stream to the plurality of first data frames by the first source switching network interface circuit is a process of completing the encapsulation of the service to the related first data frames by the first source switching network interface circuit. I.e. service encapsulation. Wherein a payload field in each of the plurality of first data frames carries a portion of the traffic data. For example, a schematic diagram of mapping a first traffic data stream to a plurality of first data frames may be as shown in fig. 6. In the present application, a service encapsulation based on a first data frame is performed in a source switching network interface circuit (e.g., an upstream FIC), and a corresponding service decapsulation is performed in a destination switching network interface circuit (e.g., a downstream FIC). For example, fig. 7 illustrates the completion location of traffic encapsulation/decapsulation in a data transfer system.

After the service encapsulation is completed, the service needs to be distributed in a balanced manner. In order to avoid unbalanced workload between multiple switching devices and different input/output (IO) ports of the same switching device, buffer overflow of the switching devices or jitter increase of transmission delay is caused. A first source-switched network interface circuit (e.g., an upstream FIC) may provide balanced distribution of traffic data. For example, the positions of (1) and (2) shown in fig. 8 are positions where equalization processing is required. (1) The data frame can be sent to different switching devices by using a Round Robin (RR) mode through the uplink FIC to achieve equalization. The equalization processing at (2) in the present embodiment is implemented in a dedicated switch chip. In the present application, since the switching device uses a general device or chip, in order to avoid changing the current hardware processing flow, the switching device may be indirectly implemented through a first source switching network interface circuit (e.g., an uplink FIC). That is, the first source switching network interface circuit can indirectly implement the balanced distribution of the switching device to the service data stream, so as to implement load balancing.

Specifically, because a load balancing field is added to the redefined DA field, the switching device can find the characteristics of the port according to the value corresponding to the DA field, and H DAs are allocated to the same destination switching network interface circuit. H is associated with the number of connection channels (e.g., media Access Control (MAC) channels) of the switching device and the destination switching network interface circuit. The load balancing field of each of the plurality of first data frames is independently dropped by an element in the balancing sequence when distributed by the source switched network interface circuit. For example, when H =4, the balancing sequence may be {0,1,2,3}, and the H =3 load balancing domain may be {0,1,2}. By uniformly inserting elements in the equalization sequence, the switching device can be controlled to uniformly distribute to different output IO. The value of the load balancing field in the first data frame, that is, the element in the load balancing sequence to be inserted, is related to the receiving port of the first destination switching network interface circuit to be sent. After the elements in the balancing sequence are inserted into the load balancing domain in the first data frame, the value of the DA field corresponding to the first data frame corresponds to the receiving port of the first destination switch network interface circuit.

The first source switching network interface circuit can insert the elements in the balancing sequence into the load balancing domain of the first data frames according to a preset rule. In an optional implementation manner, the load balancing field corresponding to each of the multiple first data frames is interpolated with an element in the balancing sequence, which may specifically be: the H first data frames in each of the first data frames in the first P groups of first data frames are respectively sequentially interpolated with elements in the equalized sequence. And the first Q elements in the equalization sequence are sequentially inserted downwards into the Q first data frames in the first data frame of the P +1 th group. Wherein H is equal to the number of elements in the equalized sequence, P is an integer quotient of T divided by H, Q is a remainder of T divided by H, and T is the number of the plurality of first data frames. H is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H. For example, there are 10 first data frames (i.e., T is 10), and the equalization sequence is {0,1,2,3} (i.e., H is 4), where P is 2 and Q is 2. That is, 10 first data frames may be divided into groups of 2+1, with two first data frames in group 3. The first source switch network interface circuit may insert a sequential loop of 0,1,2,3 sequentially down into the load balancing domain of the 10 first data frames as each of the 10 first data frames down inserts an element in the balancing sequence. That is, 0,1,2,3 is sequentially interpolated in the first data frame in the first 2 groups of 10 first data frames, respectively, and the first 2 elements of the equalization sequence, i.e., 0,1 is interpolated in the first data frame of group 3. That is, the elements inserted in the load balancing domain of the 10 first data frames are: 0,1,2,3,0,1,2,3,0,1.

It should be noted that the method for inserting the element into the load balancing field of the first data frame is only an example. The first source switch network interface circuit may also insert the element in the balancing into the load balancing domain of each first data frame by other methods, which are not listed here.

In a specific embodiment, when the first switching device is a single stage switching device, i.e. the data transmission system is a system as shown in fig. 3. The number of elements in the equalization sequence is related to the number of first connection channels, specifically: the number of elements in the equalized sequence is equal to the number of first connection channels.

For example, when the first switching device is a single-stage switching device, fig. 9 shows an equalization processing diagram of unicast traffic. Assume that the identification of the first destination switching network interface circuit is 5, i.e., DFIC _ ID =5. The number of connection channels from the first switching device to the first destination switching network interface circuit is 4, for example, the number of IO links is 4. The equalization sequence is {0,1,2,3}. At this time, the MAC address forwarding table of the first switching device may allocate 4 MAC addresses [ {0,5, 0}, {0,5, 1}, {0,5, 2}, {0,5, 3} ] to the FIC of DFIC _ ID =5. The corresponding first switching device has an egress IO of { IO _0, IO _1, IO _2, IO _3}. In each first data frame of the first traffic data flow map sent to the first destination switching network interface circuit of DFIC _ ID =5, the load balancing field may repeat one element of the sequence {0,1,2,3} in turn, except that the DFIC _ ID field is fixed to 5. As can be seen from fig. 9, by the above method, the MAC addresses corresponding to the first data frames transmitted from the IO _0, IO _1, IO _2, IO _3 ports to the first destination switching device by the first switching device are respectively {0,5, 0}, {0,5, 1}, {0,5, 2}, {0,5, 3}, which are cyclically repeated. That is, the MAC addresses corresponding to the first data frame sent by the first device from IO _0 are all {0,5, 0}, and the load balancing fields are all inserted with element 0. The MAC addresses corresponding to the first data frame sent from IO _1 are all {0,5, 1}, and the load balancing domain is inserted with element 1. The MAC addresses corresponding to the first data frame sent from IO _2 are all {0,5, 2}, and the element 2 is inserted in the load balancing domain. The MAC addresses corresponding to the first data frame sent from IO _3 are all {0,5, 3}, and the element 3 is inserted in the load balancing domain. Therefore, the first switching equipment can forward the first data frame according to the MAC address forwarding table in the current forwarding mode, and switching and load balancing are achieved.

In another specific embodiment, when the first switching device is an N-stage switching device, that is, when the data transmission system is the system shown in fig. 4. The first number of the connection channels is a number of connection channels between the first switch device and the first destination switch network interface circuit, and may specifically be: the first connection channel number is the number of connection channels between the nth stage switching device in the first switching device and the first destination switching network interface circuit. Further, the number of elements in the equalization sequence is related to the number of the first connection channels, which may specifically be: the number of elements in the equalization sequence is equal to a first value, and the first value is a common multiple of the number of the connection channels between each two stages of the N stages of the switching devices and the number of the first connection channels. Wherein N is an integer greater than or equal to 2.

Alternatively, the first value may be a least common multiple of the number of connection channels between each two stages of the N stages of switching devices and the number of first connection channels. For example, the first switching device is a three-stage switching device, such as shown in fig. 10. 1. The number of connecting channels between every two stages of the second-stage switching equipment and the third-stage switching equipment is respectively K, L and M. That is, the IO number output by each stage of switching device and connected to the downstream switching device is K, L, and M, respectively. Wherein M is the number of the first connecting channels. At this time, the number of elements of the equilibrium sequence may be the least common multiple of K, L, M W = LCM (K, L, M). The value range of the load balancing field in the first data frame may be LB = {0,1,2, \ 8230;, W-1}. I.e., the equalization sequence may be {0,1,2, \8230;, W-1}.

In the case of the three-stage switching device, in addition to the load balancing of the first-stage switching device through the first source switching network interface circuit, the output of the three-stage switching device still needs to be balanced three times, such as the positions of the second balancing, the third balancing, and the fourth balancing shown in fig. 10. For example, after determining the number of elements of the balancing sequence by the least common multiple determined above, the first source switch network interface circuit may insert an element of the balancing sequence independently in the load balancing domain of each first data frame. And the third-level switching equipment statically configures an MAC address forwarding table, and forwards the first data frame corresponding to the specified DA to the specified port to realize switching and load balancing processing.

As shown in fig. 11, it is assumed that the IO numbers of the outputs of the one, two, and three stage switching devices connected to the downstream device are { K, L, M } = {5, 4}, respectively. The number of equilibrium sequences can be LCM (K, L, M) = LCM (5,5,5) =20. The balancing sequence in which the first source switched network interface circuit is down-inserted into the load balancing domain of the plurality of first data frames may be LB = {0,1,2,3, \8230 =, 17, 18, 19}. The first source-switched network circuit sequentially and repeatedly interpolates one element of LB = {0,1,2,3, \8230;, 17, 18, 19} in a plurality of first data frames of the first traffic data stream. When the first-stage switching equipment outputs: the first data frames with LB = {0,5,10,15} respectively down-inserted in the load balancing domain are output from IO _0 of the first switching device. The first data frames with LB = {1,6,11,16} respectively down-inserted in the load balancing domain are output from IO _1 of the first switching device. The first data frames with LB = {2,7,12,17} respectively down-inserted in the load balancing domain are output from IO _2 of the first switching device. The first data frames with LB = {3,8,13,18} respectively down-inserted in the load balancing domain are output from IO _3 of the first switching device. The first data frames with LB = {4,9,14,19} respectively inserted in the load balancing domain are output from IO _4 of the first switching device. When the second-stage switching equipment outputs: the load balancing domain is respectively inserted with LB = {0,5,10,15} messages and output from IO _ 0. The first data frames with LB = {1,6,11,16} respectively down-inserted in the load balancing domain are output from IO _1 of the first switching device. The first data frames with LB = {2,7,12,17} respectively down-inserted in the load balancing domain are output from IO _2 of the first switching device. The first data frame with LB = {3,8,13,18} respectively inserted in the load balancing domain is output from IO _3 of the first switching device. The first data frames with LB = {4,9,14,19} respectively down-inserted in the load balancing domain are output from IO _4 of the first switching device. When the third stage switching equipment outputs: the load balancing domain is respectively inserted with LB = {0,4,8,12,16} first data frame output from IO _ 0. The first data frames with LB = {1,5,9,13,17} respectively down-inserted in the load balancing domain are output from IO _1 of the first switching device. The first data frame with LB = {2,6,10,14,18} respectively inserted in the load balancing domain is output from IO _2 of the first switching device. The first data frames with LB = {3,7,11,15,19} respectively down-inserted in the load balancing domain are output from IO _3 of the first switching device. By the method, the load balance of the switching equipment is realized.

In the above examples of the elements of the equalization sequence, the equalization sequence is an ordered sequence starting from element 0. It should be understood that the equalization sequence may have other possible compositions. For example, when the number of elements in the equalization sequence is 4, the equalization sequence may be {1,2,3,4} or {2,4,6,8} in addition to the above-listed equalization sequence {0,1,2,3}. Other compositions are of course possible and are not further listed here.

In order to implement lossless service switching, after a data frame is converged to a destination source switching network interface circuit, order-preserving recovery processing is required. That is, after the plurality of first data frames are gathered to the first destination source switch network interface circuit, the first destination source switch network interface circuit needs to perform an order preserving recovery process. For example, the order-preserving function of the service needs to be implemented in the uplink FIC and the downlink FIC separately. As shown in fig. 12, the uplink FIC is implemented in TS _ SN, and the downlink FIC implements sorting and reassembly.

In an optional implementation, before the first source switching network interface circuit sends the first data frames to the first switching device according to the equalization sequence, the first source switching network interface circuit interpolates the time stamps or the sequence numbers in a first domain corresponding to each of the first data frames in a set order. The setting sequence may be, for example, an increasing sequence or other sequences, which are not limited in this application. Wherein the sequence number may be an incremented sequence number. When the time stamp is inserted, the clocks of all source switch network interface circuits and destination switch network interface circuits in the data transmission system are required to be synchronized.

Further, the first destination switching network interface circuit may sequence the plurality of first data frames, specifically: the first destination switch network interface circuit orders (e.g., incrementally orders) the plurality of first data frames according to the timestamp or sequence number in the first field to which each first data frame corresponds. Thus, order-preserving recovery of the service can be completed.

Illustratively, when a first domain in the data frame inserts the timestamp, when the first destination switching network interface circuit receives the data frame from the plurality of services, the first destination switching network interface circuit does not distinguish the services, and performs global unified timestamp sorting. And sequencing the data frames of all the services according to the time sequence to finish the order-preserving recovery of the services.

By adopting the data transmission system provided by the embodiment of the application, the balanced distribution of the service data can be realized by adopting the universal switching equipment, the dependence of the data transmission system on a special chip can be avoided, the data transmission is more flexible, the interchange of various manufacturers can be realized, and the application is wide.

Based on the above embodiment, the embodiment of the present application further provides a data transmission method. As shown in fig. 13, a specific process of the method may include:

step 1301: the first source switched network interface circuit maps the first traffic data stream to a plurality of first data frames. The destination address field of each of the plurality of first data frames includes a load balancing field. The load balancing domain is used for realizing the load balancing of the first switching equipment.

Specifically, the implementation process of how the first source switch network interface circuit maps the first service data stream to the multiple first data frames may refer to the related description in the data transmission system, and details are not repeated here.

Step 1302: the first source switch network interface circuit transmits a plurality of first data frames to the first switch device according to the equalization sequence. And the load balancing domain corresponding to each first data frame of the plurality of first data frames is inserted with one element in the balancing sequence. The number of elements in the equalized sequence is related to the number of first connection channels. The first number of connection channels is the number of connection channels between the first destination switching network interface circuits of the first switching device.

In an alternative embodiment, when the first switching device is a single-stage switching device, the number of elements in the equalization sequence is related to the number of first connection channels, which may specifically be: the number of elements in the equalization sequence is equal to the number of first connection channels. In another optional implementation, when the first switching device is an N-stage switching device, the number of the first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit, and specifically may be: the first connecting channel number is the connecting channel number between the Nth stage switching device and the first destination switching network interface circuit in the first switching device. The number of elements in the equalization sequence is related to the number of the first connection channels, and may specifically be: the number of elements in the equalization sequence is equal to a first value, and the first value is a common multiple of the number of the connection channels between each two stages of the N stages of the switching devices and the number of the first connection channels. Wherein N is an integer greater than or equal to 2. Alternatively, the common multiple may be the least common multiple.

Specifically, for a specific introduction of one element in the sequence of the plurality of first data frames being interpolated and equalized, reference may be made to the related description referred to in the introduction of the transmission system, and details are not repeated here.

Step 1303: the first switching device sends the first plurality of data frames to the first destination switching network interface circuit.

Specifically, for an implementation process in which the first switch device sends the multiple first data frames to the first destination switch network interface circuit, reference may be made to relevant descriptions and examples in the above description of the data transmission system, and details are not repeated here.

Step 1304: the first destination switching network interface circuit sequences the plurality of first data frames, and decapsulates the sequenced plurality of first data frames to obtain a first service data stream.

Illustratively, the source address field of each of the plurality of first data frames includes a first field for indicating an ordering of each of the plurality of first data frames. Before the first source switching network interface circuit sends the first data frames to the first switching device according to the equalization sequence, the first source switching network interface circuit interpolates the time stamps or the sequence numbers in a first domain corresponding to each of the first data frames according to a set sequence (for example, an increasing sequence). Furthermore, the first destination switching network interface circuit may sequence the plurality of first data frames, specifically: the first destination switch network interface circuit sorts (e.g., incrementally sorts) the plurality of first data frames according to a timestamp or sequence number in the first field corresponding to each of the plurality of first data frames. Specifically, the above process may refer to the related description related to the introduction of the data transmission system, and will not be repeated herein.

By adopting the data transmission method provided by the embodiment of the application, data can be flexibly transmitted, and balanced distribution of the data can be realized without depending on special equipment during data transmission.

Based on the above embodiment, the embodiment of the application also provides a data transmission device. As shown in fig. 14, the data transmission apparatus 1400 includes a transceiving unit 1401 and a processing unit 1402. The transceiver unit 1401 is used for the data transmission apparatus 1400 to receive data and/or send data, and the processing unit 1402 is used for controlling and managing operations performed by the data transmission apparatus 1400. The processing unit 1402 may also control the data receiving/transmitting steps performed by the transceiving unit 1401.

The data transmission device 1400 is specifically a source switching network interface circuit in the above embodiment, or a processor, a chip system, or a functional module in the source switching network interface circuit.

For example, when the data transmission apparatus is used to implement the function of the first source switching network interface circuit in the embodiment of fig. 13, the processing unit 1402 is configured to execute the step 1301. The transceiving unit 1401 is configured to perform the step 1302. The repetition points are not repeated here.

It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation. The functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a portable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Based on the above embodiments, the embodiments of the present application further provide another data transmission apparatus. As shown in fig. 15, the data transmission apparatus 1500 includes a communication interface 1501 and a processor 1502. Optionally, the data transmission apparatus 1500 further includes a memory 1503. The memory 1503 may be disposed inside the data transmission device 1500 or disposed outside the data transmission device 1500. The processor 1502 controls the communication interface 1501 to receive and transmit data and the like.

Specifically, the processor 1502 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP. The processor 1502 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

Wherein, the communication interface 1501, the processor 1502 and the memory 1503 are connected to each other. Alternatively, the communication interface 1501, the processor 1502, and the memory 1503 may be connected to each other by a bus 1504. The bus 1504 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 15, but that does not indicate only one bus or one type of bus.

In an alternative embodiment, memory 1503 is used to store programs and the like. In particular, the program may include program code comprising computer operating instructions. Memory 1503 may include RAM, and may also include non-volatile memory, such as one or more disk memories. The processor 1502 executes the application program stored in the memory 1503 to implement the above functions, thereby implementing the functions of the data transmission device 1500.

Illustratively, the data transmission apparatus 1500 may specifically be the source switching network interface circuit in the foregoing embodiment. For example, when the data transmission device is used to implement the function of the first source switching network interface circuit in the embodiment of fig. 13, the communication interface 1501 may implement the transceiving operation performed by the first source switching network interface circuit in the embodiment shown in fig. 13. The processor 1502 may perform operations other than the transceiving operations performed by the first source-switched network interface circuit in the embodiment shown in fig. 13. The detailed description can be found in the embodiment shown in fig. 13, and will not be described in detail here.

Based on the above embodiments, the embodiments of the present application provide a data transmission system. The data transmission system includes at least one source switching network interface circuit (e.g., a first source switching network interface circuit), at least one switching device (e.g., a first switching device), a plurality of destination switching network interface circuits (e.g., a first destination switching network interface circuit), and so on, which are related to the above embodiments.

The embodiment of the application also provides a computer readable storage medium. The computer-readable storage medium is used for storing a computer program, and when the computer program is executed by a computer, the computer can implement the data transmission method provided by the above method embodiment.

The embodiment of the application also provides a computer program product. The computer program product is used for storing a computer program, and when the computer program is executed by a computer, the computer can realize the data transmission method provided by the method embodiment.

The embodiment of the application also provides a chip, which comprises a processor and a communication interface, wherein the communication interface is used for receiving and/or sending data; the processor is used for enabling the chip to achieve the data transmission method provided by the method embodiment.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A data transmission system, comprising: at least one source switched network interface circuit, at least one switching device, and a plurality of destination switched network interface circuits, wherein:

the first source switching network interface circuit maps the first service data flow to a plurality of first data frames, and the destination address field of each first data frame of the plurality of first data frames comprises a load balancing domain which is used for realizing the load balancing of the first switching equipment;

the first source switching network interface circuit sends the plurality of first data frames to the first switching device according to a balancing sequence, wherein a load balancing domain corresponding to each first data frame of the plurality of first data frames is down-inserted with one element in the balancing sequence, the number of elements in the balancing sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and a first destination switching network interface circuit;

the first switching device sends the plurality of first data frames to the first destination switching network interface circuit;

the first destination switching network interface circuit sequences the plurality of first data frames, and decapsulates the sequenced plurality of first data frames to obtain the first service data stream;

the first source switching network interface circuit is any one of the at least one source switching network interface circuit, the first switching device is one or more of the at least one switching device, and the first destination switching network interface circuit is any one of the plurality of destination switching network interface circuits.

2. The system of claim 1 wherein when said first switching device is a single stage switching device, the number of elements in said equalization sequence being related to the number of said first connection paths comprises:

the number of elements in the equalization sequence is equal to the number of first connection channels.

3. The system as claimed in claim 1, wherein when the first switch device is an N-stage switch device, the first connection channel number is a connection channel number between the first switch device and the first destination switch network interface circuit, and includes:

the first number of the connection channels is the number of the connection channels between the nth stage switching device in the first switching device and the first destination switching network interface circuit;

the number of elements in the equalization sequence is related to the number of the first connection channels, and the method comprises the following steps:

the number of elements in the equalization sequence is equal to a first value, and the first value is a common multiple of the number of connection channels between each two stages of switching equipment in the N stages of switching equipment and the number of the first connection channels;

wherein N is an integer greater than or equal to 2.

4. The system of claim 3, wherein the common multiple is a least common multiple.

5. The system according to any of claims 1-4, wherein the dropped element of the load balancing field corresponding to each of the plurality of first data frames is associated with a receive port of the first destination switch network interface circuit.

6. The system of any one of claims 1-5, wherein the load balancing field corresponding to each of the plurality of first data frames is down-inserted by one element of the balancing sequence, comprising:

the H first data frames in each first data frame in the first P groups of first data frames are respectively and sequentially inserted into the elements in the equalization sequence;

q first data frames in the P +1 th group of first data frames are respectively and sequentially inserted with the first Q elements in the equalization sequence;

wherein H is equal to the number of elements in the equalized sequence, P is an integer quotient of T divided by H, Q is a remainder of T divided by H, and T is the number of the first data frames;

h is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H.

7. The system of any one of claims 1-6, wherein the source address field of each of the plurality of first data frames includes a first field to indicate an ordering of each of the plurality of first data frames;

before the first source-switched network interface circuit transmits the first plurality of data frames to the first switching device according to an equalization sequence, the method further comprises:

the first source switching network interface circuit interpolates a time stamp or a sequence number in a first domain corresponding to each of the plurality of first data frames according to a set sequence.

8. The system of claim 7, wherein the first destination switch network interface circuit to order the first plurality of data frames comprises:

and the first destination switching network interface circuit sequences the first data frames according to the time stamps or the sequence numbers in the first domain corresponding to each first data frame of the first data frames.

9. The system of any of claims 1-8, wherein at least one of the switching devices is a local area network switch (LSW) switch chip.

10. A method of data transmission, comprising:

mapping a first service data stream to a plurality of first data frames, wherein a destination address field of each first data frame of the plurality of first data frames comprises a load balancing domain, and the load balancing domain is used for realizing load balancing of first switching equipment;

and sending the plurality of first data frames to the first switching device according to the balancing sequence, wherein one element in the balancing sequence is inserted into a load balancing domain corresponding to each of the plurality of first data frames, the number of elements in the balancing sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and a first destination switching network interface circuit.

11. The method of claim 10 wherein when the first switching device is a single stage switching device, the number of elements in the equalization sequence is related to the number of first connection channels, comprising:

the number of elements in the equalization sequence is equal to the number of the first connection channels.

12. The method as claimed in claim 10, wherein when the first switch device is an N-stage switch device, the first number of connection channels is a number of connection channels between the first switch device and the first destination switch network interface circuit, and includes:

the number of elements in the equalization sequence is equal to a first value, and the first value is a common multiple of the number of connection channels between each two stages of switching equipment in the N stages of switching equipment and the number of first connection channels;

wherein N is an integer greater than or equal to 2.

13. The method of claim 12, wherein the common multiple is a least common multiple.

14. The method of any of claims 10-13, wherein the dropped element of the load balancing field corresponding to each of the plurality of first data frames is associated with a receive port of the first destination switch network interface circuit.

15. The method of any one of claims 10-14, wherein the load balancing field corresponding to each of the plurality of first data frames is down-inserted by one element of the balancing sequence, comprising:

h first data frames in each first data frame in the first P groups of first data frames are respectively and sequentially inserted into elements in the equalization sequence;

16. The method of any one of claims 10-15, wherein the source address field of each of the plurality of first data frames includes a first field for indicating an ordering of each of the plurality of first data frames;

prior to transmitting the plurality of first data frames to the first switching device in accordance with the equalization sequence, the method further comprises:

and interpolating time stamps or sequence numbers in a first domain corresponding to each first data frame of the plurality of first data frames according to a set sequence.

17. A data transfer device comprising a memory, a processor, and a communication interface, wherein:

the memory is to store computer instructions;

the communication interface is used for receiving and sending data;

the processor is coupled to the memory for invoking computer instructions in the memory to cause the data transmission apparatus to perform the method of any of claims 10-16.

18. A data transmission device comprising a processor and a communication interface, wherein:

the communication interface is used for receiving and sending data;

the processor is configured to cause the data transmission apparatus to perform the method according to any one of claims 10 to 16.

19. A computer-readable storage medium having stored thereon computer-executable instructions for causing a computer to perform the method of any one of claims 10-16 when invoked by the computer.

20. A computer program product comprising instructions for causing a computer to perform the method of any one of claims 10 to 16 when the computer program product is run on the computer.