CN115208391A - Clock signal measuring circuit, clock signal processing device and chip - Google Patents

Abstract

The embodiment of the application discloses clock signal measurement circuit, clock signal processing apparatus and chip, clock signal measurement circuit includes: the device comprises a first counting unit, a counting control unit and a second counting unit; the first counting unit is used for starting to count the preset clock signal according to the updating signal to obtain and output a first period number; the counting control unit is used for sending a starting instruction to the control end of the second counting unit when the first counting unit starts to count the preset clock signals, and sending a stopping instruction to the control end of the second counting unit when the first period number reaches the preset value; and the second counting unit is used for responding to the starting instruction, starting to count the clock signal to be tested, responding to the stopping instruction, stopping counting the clock signal to be tested, and obtaining and outputting a final value of the second period number. The method and the device can realize accurate measurement of the clock frequency on the high-speed chip.

Description

Clock signal measuring circuit, clock signal processing device and chip

Technical Field

The present disclosure relates to the field of integrated circuits, and particularly to a clock signal measurement circuit, a clock signal processing apparatus and a chip.

Background

In an integrated circuit, a High-Speed On-Chip Clock (High Speed On-Chip Clock) is generated by a PLL (delay locked Loop) to perform At-Speed (full Speed) testing On a digital logic sequential circuit. In the related art, a method for measuring the frequency of a high-speed on-chip clock is lacking.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a clock signal measurement circuit, a clock signal processing apparatus, and a chip, which can implement accurate measurement of a clock frequency on a high-speed chip.

The technical scheme of the embodiment of the application is realized as follows:

the embodiment of the application provides a clock signal measurement circuit, including: the device comprises a first counting unit, a counting control unit and a second counting unit;

the input end of the first counting unit receives a preset clock signal, the control end of the first counting unit receives an updating signal, and the first counting unit is used for starting to count the preset clock signal according to the updating signal to obtain and output a first period number;

the input end of the counting control unit receives the first period number, and the counting control unit is used for sending a starting instruction to the control end of the second counting unit when the first counting unit starts counting the preset clock signals and sending a stopping instruction to the control end of the second counting unit when the first period number reaches a preset value;

the input end of the second counting unit receives a clock signal to be measured, and the second counting unit is used for starting to count the clock signal to be measured in response to the starting instruction, and stopping to count the clock signal to be measured in response to the stopping instruction, so as to obtain and output a final value of a second period number.

In the above solution, the clock signal measuring circuit further includes: a first register unit; the input end of the first register unit is electrically connected to the output end of the second counting unit, and the first register unit is used for registering the final value of the second period number and outputting the final value of the second period number through the first output end of the first register unit.

In the above solution, the clock signal measuring circuit further includes: a first control gate; a first input end of the first control gate receives the preset clock signal, and an output end of the first control gate is electrically connected with an input end of the first counting unit; the second output end of the first register unit is electrically connected with the second input end of the first control gate; the first register unit is further configured to output a first monitoring enable signal to a second input terminal of the first control gate through a second output terminal of the first register unit, so as to control the transmission of the preset clock signal to the first counting unit.

In the above solution, the clock signal measuring circuit further includes: a second control gate; a first input end of the second control gate receives the clock signal to be tested, and an output end of the second control gate is electrically connected with an input end of the second counting unit; the second output end of the first register unit is also electrically connected with the second input end of the second control gate; the first register unit is further configured to output the first monitoring enable signal to a second input end of the second control gate through a second output end of the first register unit, so as to control the clock signal to be tested to be transmitted to the second counting unit.

In the above solution, the clock signal measuring circuit further includes: a second register unit; the input end of the second registering unit is electrically connected to the output end of the second counting unit, and the second registering unit is used for registering and outputting the final value of the second cycle number.

In the above scheme, the final value of the second cycle number includes m bits of data, and the second register unit includes m registers; the data input ends of the m registers correspondingly receive the m bits of data one by one; the clock input ends of the m registers receive the preset clock signals; the output end of each register is electrically connected with the scanning input end of the next register, and the output end of the mth register outputs the final value of the second period number.

In the above solution, the clock signal measuring circuit further includes: m third control gates; the first input ends of the m third control gates correspondingly receive the m bits of data one by one; the output ends of the m third control gates are electrically connected with the data input ends of the m registers in a one-to-one correspondence manner; the third output end of the first register unit is electrically connected with the second input ends of the m third control gates; the first register unit is further configured to output a second monitor enable signal to second input terminals of the m third control gates through third output terminals thereof, so as to control a final value of the second cycle number to be transmitted to the second register unit.

An embodiment of the present application further provides a clock signal processing apparatus, where the clock signal processing apparatus includes: a frequency calculation unit; the frequency calculation unit is used for prestoring the frequency of a preset clock signal and a preset value corresponding to the first periodicity, receiving a final value of a second periodicity corresponding to the clock signal to be measured, and calculating the frequency of the clock signal to be measured according to the frequency of the preset clock signal, the preset value of the first periodicity and the final value of the second periodicity.

In the above solution, the clock signal processing apparatus further includes: a determination unit; the judging unit is used for receiving the final value of the second periodicity and judging whether the final value of the second periodicity meets a first judging condition; the first determination condition is set based on an expected value of the frequency of the clock signal under test.

In the above solution, the clock signal processing apparatus further includes: a screening unit; the screening unit is configured to receive a final value of the at least one second cycle number corresponding to the at least one chip to be tested, and determine the final value of the at least one second cycle number according to a second determination condition, so as to screen a compliant chip from the at least one chip to be tested; the second determination condition is set based on the first determination condition.

The embodiment of the application also provides a chip which comprises the clock signal measuring circuit in the scheme.

Therefore, the embodiments of the present application provide a clock signal measurement circuit, a clock signal processing apparatus and a chip, where the clock signal measurement circuit includes: the device comprises a first counting unit, a counting control unit and a second counting unit; the input end of the first counting unit receives a preset clock signal, the control end of the first counting unit receives an updating signal, and the first counting unit is used for starting to count the preset clock signal according to the updating signal to obtain and output a first period number; the counting control unit receives the first period number at the input end, and is used for sending a starting instruction to the control end of the second counting unit when the first counting unit starts counting the preset clock signals and sending a stopping instruction to the control end of the second counting unit when the first period number reaches the preset value; and the input end of the second counting unit receives the clock signal to be detected, and the second counting unit is used for starting to count the clock signal to be detected in response to the starting instruction and stopping to count the clock signal to be detected in response to the stopping instruction so as to obtain and output the final value of the second period number. In this way, the counting of the first counting unit is controlled according to the first period number counted by the first counting unit, and the final value of the second period number is obtained. Because a proportional relation exists between the preset value of the first period number and the final value of the second period number, the frequency of the clock signal to be measured can be obtained through the final value of the second period number, and therefore accurate measurement of the clock frequency on the high-speed chip can be achieved.

Drawings

Fig. 1 is a first schematic structural diagram of a clock signal measurement circuit according to an embodiment of the present disclosure;

fig. 2 is a first signal diagram of a clock signal measurement circuit according to an embodiment of the present disclosure;

fig. 3 is a second schematic structural diagram of a clock signal measurement circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a clock signal measurement circuit according to an embodiment of the present disclosure;

fig. 5 is a signal diagram illustrating a clock signal measurement circuit according to an embodiment of the present disclosure;

fig. 6 is a signal schematic diagram of a clock signal measurement circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a clock signal processing apparatus according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a chip provided in an embodiment of the present application.

Detailed Description

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further described in detail with reference to the drawings and the embodiments, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

The following description will be added if similar descriptions of "first/second" appear in the specification, and in the following description, reference is made to the term "first \ second \ third" merely for distinguishing between similar objects and not for representing a particular ordering for the objects, and it is to be understood that "first \ second \ third" may be interchanged under certain circumstances or a sequential order, so that the embodiments of the application described herein can be implemented in other than the order shown or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In Design-for-Test (Design-for-testability) field, a TDF (Transition-Delay-Fault) Pattern is generated by an ATPG Tool, and a High-Speed On-Chip Clock is generated by a PLL (Delay locked loop) to perform At-Speed (full-Speed) Test On a digital logic sequential circuit. The frequency of the high-speed on-chip clock needs to be converged during the design stage STA (static timing analysis), and the STA considers the influence of parameters such as PVT (Process-Voltage-Temperature) and the like within the range of Sign-off. However, in the Post-Silicon Test, the PVT influence cannot be predicted, so that Die-by-Die differences occur between chips on different wafers, even between chips at different positions on the same Wafer, and thus, the frequency of the high-speed on-chip clock varies in different degrees.

In addition, when the TDF Pattern is tested, the frequency of the high-speed on-chip clock may change when the power supply voltage of the chip changes, even if the same test vector is affected by IR-Drop at different time points. Therefore, an effective solution is needed to accurately measure the frequency of the high-speed on-chip clock and determine whether the frequency is within a desired frequency range. Therefore, the frequency of the clock on the high-speed chip in the chip cannot be tested by means of the TDF Pattern test, and even if the TDF Pattern test is passed, whether the frequency of the clock on the high-speed chip is within the expected frequency range cannot be described.

Fig. 1 is an alternative structural schematic diagram of a clock signal measurement circuit according to an embodiment of the present disclosure, and as shown in fig. 1, the clock signal measurement circuit 80 includes: a first counting unit 10, a second counting unit 20 and a counting control unit 30.

An input end of the first counting unit 10 receives a preset clock signal test _ clk, and a control end of the first counting unit 10 receives an update signal edt _ update; the first counting unit 10 is configured to start counting the preset clock signal test _ clk according to the update signal edt _ update, and obtain and output a first period count _1.

The input terminal of the count control unit 30 receives the first cycle number; the counting control unit 30 is configured to send a start instruction to the control terminal of the second counting unit 20 when the first counting unit 10 starts counting the preset clock signal test _ clk, and send a stop instruction to the control terminal of the second counting unit 20 when the first cycle count _1 reaches the preset value.

The input end of the second counting unit 20 receives a clock signal pll _ clk to be tested; the second counting unit 20 is configured to start counting the clock signal pll _ clk to be tested in response to the start instruction, and stop counting the clock signal pll _ clk to be tested in response to the stop instruction, so as to obtain and output a final value of the second cycle count _2.

The clock signal measurement circuit 80 provided in the embodiment of the present application may operate in the TDF Pattern test process. The preset clock signal Test _ clk may be a clock signal used in the TDF Pattern Test process and provided by Automatic Test Equipment (ATE). The frequency of the preset clock signal test _ clk may be set as needed, and in the embodiment of the present application, the frequency of the preset clock signal test _ clk is 25MHz for explanation.

In the embodiment of the present application, the clock signal to be tested pll _ clk is a high-speed on-chip clock provided by a delay locked loop in a chip to be tested, that is, the clock signal to be tested pll _ clk has a higher frequency than the preset clock signal test _ clk. In the embodiment of the present application, an expected value of the frequency of the clock signal pll _ clk to be tested is 500MHz. Here, the expected value of the frequency of the clock signal pll _ clk to be measured refers to a value to which the frequency of the clock signal pll _ clk to be measured should reach in chip design. In an actually produced chip, the frequency of the clock signal pll _ clk to be measured may deviate from an expected value, and if the deviation is too large, the chip may not work normally.

In the embodiment of the present application, the update signal edt _ update is derived from the chip scan compression circuit, which is automatically generated by the ATPG Tool during the TDF Pattern test. The length of the Scan chain (Scan Chains) of the chip Scan compression circuit can be determined according to the actual size of the chip, and is generally between 300 and 1000 orders of magnitude.

In this embodiment, the first counting unit 10 may count the preset clock signal test _ clk, and count the number of cycles in the preset clock signal test _ clk to obtain a first cycle number count _1. The second counting unit 20 may count the clock signal pll _ clk to be tested, and count the number of cycles in the clock signal pll _ clk to be tested to obtain a second cycle number count _2. Here, since the preset clock signal test _ clk and the clock signal pll _ clk to be tested are both square wave signals, and each rising edge in the square wave signals corresponds to each period, the first counting unit 10 and the second counting unit 20 may obtain the first period count _1 and the second period count _2 by counting the number of rising edges in the preset clock signal test _ clk and the clock signal pll _ clk to be tested.

Fig. 2 is a schematic diagram of alternative waveforms of the signals in fig. 1, and will be described with reference to fig. 1 and 2. It should be noted that, in fig. 2 and other waveform diagrams of the present application, the first period number count _1 and the second period number count _2 are shown as hexadecimal numbers, and a description thereof will not be repeated.

In the embodiment of the present application, referring to fig. 1 and fig. 2, when the update signal edt _ update is 1, the first counting unit 10 starts to clear the count triggered by the rising edge of the preset clock signal test _ clk, that is, the first period count _1 becomes 0. Then, the first counting unit 10 starts to count the preset clock signal test _ clk, counts the number of cycles in the preset clock signal test _ clk, and the first number of cycles count _1 is correspondingly accumulated. Meanwhile, the count control unit 30 receives the first cycle number count _1 from the first counting unit 10. When the count control unit 30 receives that the first number of cycles count _1 is accumulated to 1, that is, the first counting unit 10 starts to count the preset clock signal test _ clk, the count control unit 30 sends a start instruction to the control terminal of the second counting unit 20, so that the second counting unit 20 starts to count the clock signal pll _ clk to be tested.

In the embodiment of the present application, with reference to fig. 1 and fig. 2, when the first cycle count _1 received by the counting control unit 30 is accumulated to the preset value 80 (hexadecimal number), the counting control unit 30 sends a stop instruction to the control terminal of the second counting unit 20, so that the second counting unit 20 stops counting the clock signal pll _ clk to be tested. As shown in fig. 2, the second periodic number count _2 is accumulated to 9EC (hexadecimal number) and then stops, i.e. the final value of the second periodic number count _2 is 9EC (hexadecimal number).

It should be noted that, since the first counting unit 10 and the second counting unit 20 are clock domain crossing paths, there is a clock crossing synchronization circuit in the circuits. As shown in the waveform diagram, as shown in fig. 2, the time when the second periodic number count _2 starts to be accumulated lags behind the time when the first periodic number count _1 starts to be accumulated by one testing clock period; the time when the second cycle count _2 stops accumulating is also delayed by one test clock cycle with respect to the time when the first cycle count _1 stops accumulating. Here, the test clock period refers to a period in which the clock signal test _ clk is preset.

In the embodiment of the application, referring to fig. 1 and fig. 2, when the first period count _1 is accumulated to the predetermined value 80 (hexadecimal number), the first counting unit 10 stops counting the predetermined clock signal test _ clk, that is, the first period count _1 is not accumulated after being accumulated to the predetermined value 80 (hexadecimal number). In some embodiments, the count control unit 30 is further connected to the control terminal of the first counting unit 10, and the count control unit 30 is further configured to send a stop instruction to the control terminal of the first counting unit 10 when the first number of cycles count _1 reaches the preset value, so as to control the first counting unit 10 to stop counting the preset clock signal test _ clk. In other embodiments, the first counting unit 10 further includes a controller for controlling the first counting unit 10 to stop counting the preset clock signal test _ clk when the first period number count _1 reaches the preset value.

In the embodiment of the present application, while the first counting unit 10 starts counting the preset clock signal test _ clk, the second counting unit 20 starts counting the clock signal pll _ clk to be measured; while the first periodic number count _1 is accumulated to a predetermined value, the second periodic number count _2 is accumulated to a final value. Accordingly, the time taken for the first period number count _1 to be accumulated from 0 to the preset value is equal to the time taken for the second period number count _2 to be accumulated from 0 to the final value. That is, the product of the preset value of the first period count _1 and the period of the preset clock signal test _ clk is equal to the product of the final value of the second period count _2 and the period of the clock signal pll _ clk to be tested, that is:

C1×T1＝C2×T2 (1)；

in the above formula (1), C1 represents a preset value of the first period count _1, T1 represents a period of the preset clock signal test _ clk, C2 represents a final value of the second period count _2, and T2 represents a period of the clock signal pll _ clk to be measured.

However, in practice, since the clock phase relationship is uncertain, the second period count _2 usually has a count value deviation of one high-speed clock period (i.e. the period of the clock signal pll _ clk to be measured), as shown by a dashed line Syn (Synchronization) in fig. 2, and therefore, the above equation (1) needs to be corrected. Thus, the preset value 80 (hexadecimal) of the first period count _1 and the final value 9EC (hexadecimal) of the second period count _2 illustrated in fig. 2 satisfy the following equation:

(C1-1)×T1＝C2×T2 (2)；

in the above equation (2), 1 is subtracted from the predetermined value C1 of the first number of cycles count _1 to correct it. Thus, taking the values shown in fig. 2 as an example, the preset value C1 of the first cycle count _1 is 80 (hexadecimal), namely 128 (decimal); the final value C2 of the second periodic number count _2 is 9EC (hexadecimal), i.e., 2540 (decimal); if the frequency of the preset clock signal test _ clk is 25MHz, the period T1 of the preset clock signal test _ clk is 1000/25=40ns. Substituting C1, C2, and T1 into equation (2) can obtain that the period T2 of the clock signal pll _ clk to be measured is 2ns. Thus, the frequency of the clock signal pll _ clk to be tested is 1000/2=500mhz, that is, the clock signal pll _ clk to be tested illustrated in fig. 2 conforms to the expected value of the frequency of the clock signal pll _ clk to be tested.

It is understood that the counting of the first counting unit 20 is controlled according to the first period count _1 counted by the first counting unit 10, and the final value of the second period count _2 is obtained. Because a proportional relationship exists between the preset value of the first cycle count _1 and the final value of the second cycle count _2, the frequency of the clock signal pll _ clk to be measured can be obtained through the final value of the second cycle count _2, and thus, the accurate measurement of the clock frequency on the high-speed chip can be realized.

Fig. 3 is an alternative structural diagram of the clock signal measurement circuit 80 according to the embodiment of the present disclosure.

It should be noted that, in fig. 3, the PAD _ TEST _ CLK is an input port of the preset clock signal TEST _ CLK, and is provided by the tester ATE during the TDF Pattern TEST. The preset clock signal test _ clk may be adjusted as needed, and the preset clock signal test _ clk is 25MHz for explanation.

In addition, the delay locked loop PLL can provide a high-speed on-chip clock (i.e., the clock signal PLL _ clk to be tested), the frequency of which is precisely measured and measured in real time during the TDF Pattern test process, which is described herein with the expected value of the frequency of the clock signal PLL _ clk to be tested being 500 MH.

In addition, the PAD _ EDT _ UPDATE transmits an UPDATE signal EDT _ UPDATE of the scan compression circuit in the chip, which is automatically generated by the ATPG Tool during the generation of the TDF Pattern.

IN addition, the PAD _ SCAN _ IN and the PAD _ SCAN _ OUT are input ports and output ports of the SCAN chain, respectively, and can output register values on the SCAN chain inside the chip to the tester ATE for observation, wherein a logic value 1 is indicated if the voltage is high H, and a logic value 0 is indicated if the voltage is low L, and the length of the SCAN chain can be determined according to the actual size of the chip, and is generally 300 to 1000 orders of magnitude.

In addition, the PAD _ SCAN _ EN transmits a SCAN enable signal for driving the register in the second register unit 50.

In some embodiments of the present application, as shown in fig. 3, the clock signal measurement circuit 80 further includes: a first register unit 40. The input of the first register unit 40 is electrically connected to the output of the second counting unit 20. The first register unit 40 is configured to register the final value of the second periodic number count _2, and output the final value of the second periodic number count _2 through a first output terminal thereof.

In the embodiment of the present application, referring to fig. 3, the first Register unit 40 may be a Test Data Register (TDR) in a Joint Test Action Group (JTAG). One function of JTAG TDR is to observe the internal logic value of the chip, and output the logic value to the tester ATE through the PAD _ DFT _ TDO for observation, wherein if the voltage is high, the logic value is 1, and if the voltage is low, the logic value is 0. Accordingly, referring to fig. 3, the final value of count _2 output by the second counting unit 20 can be transmitted to the tester ATE through the first register unit 40 (i.e. JTAG TDR) to perform a ratio, and the value is accurate.

In some embodiments of the present application, as shown in fig. 3, the clock signal measuring circuit 80 further includes: the first control gate A1. A first input terminal of the first control gate A1 receives the preset clock signal test _ clk, and an output terminal of the first control gate A1 is electrically connected to an input terminal (i.e., data terminal) of the first counting unit 10. A second output terminal of the first register unit 40 is electrically connected to a second input terminal of the first control gate A1. The first register unit 40 is further configured to output the first monitor enable signal monitor _ en _1 to a second input terminal of the first control gate A1 through a second output terminal thereof, so as to control the transmission of the preset clock signal test _ clk to the first counting unit 10.

In the embodiment of the present application, referring to fig. 3, the first monitor enable signal monitor _ en _1 is controlled by the first register unit 40 (i.e., TDR), and the default value of the first monitor enable signal monitor _ en _1 is 0. When the test is not required, the first register unit 40 may turn off the transmission path of the preset clock signal test _ clk to the first counting unit 10 through the first monitor enable signal monitor _ en _1, thereby reducing power consumption.

In some embodiments of the present application, as shown in fig. 3, the clock signal measuring circuit 80 further includes: the second control gate A2. A first input terminal of the second control gate A2 receives the clock signal pll _ clk to be tested, and an output terminal of the second control gate A2 is electrically connected to an input terminal (i.e., data terminal) of the second counting unit 20. The second output terminal of the first register unit 40 is further electrically connected to a second input terminal of the second control gate A2. The first register unit 40 is further configured to output the first monitor enable signal monitor _ en _1 to the second input terminal of the second control gate A2 through the second output terminal thereof, so as to control the clock signal pll _ clk to be tested to be transmitted to the second counting unit 20.

In the embodiment of the present application, referring to fig. 3, the first monitor enable signal monitor _ en _1 is controlled by the first register unit 40 (i.e., TDR), and the default value of the first monitor enable signal monitor _ en _1 is 0. When the test is not required, the first register unit 40 may close the transmission channel from the clock signal pll _ clk to be tested to the second counter unit 20 through the first monitor enable signal monitor _ en _1, thereby reducing power consumption.

In some embodiments of the present application, as shown in fig. 3, the clock signal measurement circuit 80 further includes: a second register unit 50. An input terminal of the second register unit 50 is electrically connected to an output terminal of the second counting unit 20, and the second register unit 50 is used for registering and outputting the final value of the second period number count _2.

In the embodiment of the present application, referring to fig. 3, the second register unit 50 is electrically connected to the output terminal of the second counting unit 20 for receiving the final value of the second cycle count _2. The second register unit 50 registers the final value of the second cycle count _2, and outputs the result to the tester ATE through the SCAN chain output port PAD _ SCAN _ OUT for ratio calculation, where the result is accurate.

It is understood that, through the first register unit 40 or the second register unit 50, the final value of the second period count _2 can be registered and then output to the tester ATE for ratio, so that the frequency of the clock signal pll _ clk to be tested can be accurately measured.

In some embodiments of the present application, as shown in FIG. 4, the final value of the second cycle count _2 includes m bits of data, and the second register unit includes m registers (i.e., reg _0 to reg _ m-1). The data input ends D of the m registers receive m bits of data in a one-to-one correspondence, and the clock input ends CLK of the m registers receive a preset clock signal test _ CLK. The output terminal Q of each register is electrically connected to the scan input terminal SD of the next register, and the output terminal Q of the mth register outputs the final value of the second period count _2.

In the embodiment of the present application, the data bit numbers of the first period number count _1 and the second period number count _2 in the binary system may be preset, the first period number count _1 may be set to n-bit data, and the second period number count _2 may be set to m-bit data. Correspondingly, the output end of the first counting unit 10 includes n ports, and each port is used for correspondingly outputting each data bit of the first period number count _ 1; the output of the second counting unit 20 includes m ports, and each port is used for outputting each data bit of the second periodic number count _2.

In the embodiment of the application, the value of the data bit number n is based on a preset value which can include a first period number count _1, and a certain redundant bit can be reserved; the value of the data bit number m is based on the expected final value which can include the second period number count _2, and a certain redundant bit can be reserved. For example, if the preset value of the first cycle count _1 is 80 (hexadecimal), the data bit number n of the first cycle count _1 in the binary system may be set to be 9, that is, the first cycle count _1 is 9-bit wide; if the expected final value of the second period number count _2 is 9EC (hexadecimal), the data bit number m of the second period number count _2 in the binary system can be set to 13, i.e. the second period number count _2 is 13-bit width. If it is desired to measure a longer time period, i.e., the preset value of the first period count _1 and the expected final value of the second period count _2 are increased, the modifiable hardware circuit increases the data bits m and n.

In the embodiment of the present application, the second register unit includes m registers (i.e., reg _0 to reg _ m-1). The data input terminals D of the m registers are electrically connected to m ports of the output terminal of the second counting unit 20 in a one-to-one correspondence, so as to receive m bits of data of the final value of the second periodic number count _2. The m registers reg _0 to reg _ m-1 need to be chained into the scan chain without being chained into the compression circuit, so that the values output by the m registers reg _0 to reg _ m-1 can be directly observed from the tester ATE.

In some embodiments of the present application, as shown in fig. 4, the clock signal measurement circuit 80 further includes: m third control gates A3. First input terminals of the m third control gates A3 receive m-bit data of the second periodic number count _2 in a one-to-one correspondence. The output terminals of the m third control gates A3 are electrically connected to the data input terminals D of the m registers reg _0 to reg _ m-1 in a one-to-one correspondence. The third output terminal of the first register unit 40 is electrically connected to the second input terminals of the m third control gates A3; the first register unit 40 is further configured to output the second monitor enable signal monitor _ en _2 to second input terminals of the m third control gates A3 through a third output terminal thereof, so as to control a final value of the second period count _2 to be transmitted to the second register unit 50.

In the embodiment of the present application, referring to fig. 4, the second monitor enable signal monitor _ en _2 is controlled by the first register unit 40 (i.e., TDR), and the default value of the second monitor enable signal monitor _ en _2 is 0. When the data sampling by the second register unit 50 is not needed, the first register unit 40 may close the transmission path from the second period count _2 to the second register unit 50 by the second monitor enable signal monitor _ en _2, thereby reducing power consumption.

Fig. 5 and 6 are schematic diagrams of alternative waveforms of signals in fig. 4, which will be described in conjunction with fig. 4, 5 and 6.

Referring to fig. 4, 5 and 6, the first monitor enable signal monitor _ en _1 is controlled to be 1 by the first register unit 40, and the first monitor enable signal monitor _ en _2 is also controlled to be 1 by the first register unit 40, wherein the first monitor enable signal monitor _ en _1 and the first monitor enable signal monitor _ en _2 are shown in the same waveform, and thus, the first control gate A1, the second control gate A2 and the third control gate A3 are all in an on state to transmit signals.

Then, the ATPG generates TDF Pattern, which includes a period of 1 for the update signal edt _ update. In the Load/Unload phase, PAD _ SCAN _ EN is 1, and the first counting unit 10 and the second counting unit 20 operate until the first period count _1 reaches a predetermined value 80 (hexadecimal), and c the second period count _2 stops accumulating and keeps a fixed value, i.e. the final value 9EC (hexadecimal) of the second period count _2 is obtained. The final value of the second period count _2 may reflect the frequency of the clock signal pll _ clk to be tested.

Furthermore, the clock signal measurement circuit 80 can transmit the final value of the second period count _2 to the tester ATE to calculate the frequency of the clock signal pll _ clk to be tested, which will be described in the following.

In the first scheme, the frequency of the high-speed on-chip clock is accurately measured.

First, after the TDF Pattern Test is completed, a Test End to Read TDR operation may be added to Read the final value of the second cycle count _2, which is measured only once. The clock signal measurement circuit 80 transmits the final value of the second cycle count _2 to the JTAG TDR, for example, the desired value of the final value of the second cycle count _2 is 9ec =0 \u1001 \u1110 \1100, and the allowable values are 9EB, 9EC, and 9ED. Furthermore, the ratio of the final value of the second periodic number count _2 may be performed according to the allowable value, and if the TDR Bit ratio corresponding to the test equipment is incorrect, the corresponding bits indicating the actual final value of the second periodic number count _2 are opposite, and the conversion may be performed once, so as to obtain the actual final value of the second periodic number count _2 and calculate the clock frequency, for example, if Bit [2 ] is all incorrect, the actual value is 0_, 1001_, 1110_, 1011.

Further, for automation, the intersection of allowable values may be selected as a standard, for example, the intersection of 9EB, 9EC and 9ED is 0_1001_1110_1xxx, and the last three bits may be set not to be subjected to the ratio. Then, the Read TDR passing indicates that the final value of the actual second period count _2 is allowable at 0 \u1001 \u1110 \u1000 to 0_1001_1110_1111, and correspondingly, the frequency range of the clock signal pll _ clk to be measured is 499.21MHz to 500.59 MHz.

Furthermore, read TDR Expected Value:0 \u1001 \u1110 _1XXXcan be set as a judgment standard to realize mass production of sifting chips, and sifting out chips with clock frequency not conforming to expectation.

And secondly, measuring whether the clock frequency is within the expected minimum and maximum frequency ranges in real time.

First, the clock signal measuring circuit 80 can transmit the final value of the second cycle count _2 to the data input terminals D of a set of observation registers reg _ 0-reg _ m-1, and the set of observation registers reg _ 0-reg _ m-1 needs to be serially connected into the scan chain. When PAD _ SCAN _ EN =0, the final value of the second periodic number count _2 is sampled to the set of registers; when PAD _ SCAN _ EN =1, i.e. the next Pattern Unload, the values stored in the set of registers are transmitted to the tester ATE via PAD _ SCAN _ OUT for ratio, i.e. referring to fig. 6, in the Unload phase of Pattern N, the values stored in registers reg _0 to reg _ m-1 (corresponding to the final value of the second period count _2 counted in Pattern N-1) are transmitted to the tester ATE. Here, registers included in the first counting unit 10 and the second counting unit 20 cannot be connected in series into a scan chain, so that the counting function is prevented from being disabled due to a value change in the Load/Unload phase. It should be noted that the TDF Pattern is automatically generated by ATPG Tool according to digital logic circuit, and the number of TDF Pattern is thousands, so that it is necessary to automatically realize the function of observing the ATE of the tester.

Further, ATPG Tool may be instructed to perform the following instruction operations: add _ input _ constraints icl _ dft _ clock _ frequency _ monitor/counter _ pll _ clk [12 ].

Further, a clock frequency range, such as 0 \u1001 \u1110 \u1XXX, with values between 0 \u1001 \u1110 \u1000 and 0 \u1001 \u1110 _1111, and a practical clock frequency range between 499.21MHz and 500.59MHz, needs to be selected. If the ratio of the test equipment ATE passes, the actual clock frequency is from 499.21MHz to 500.59MHz, which is expected. By the method, mass production of the screen slices can be realized, and chips with clock frequencies which are not in line with expectation can be screened out. Accordingly, if the ratio is not required, the monitor _ en _2 can be controlled to 0 by TDR to close the transmission channel of the third control gate A3.

It can be understood that the second scheme is to measure the clock frequency for each TDF Pattern. If the hardware value at which the first counting unit 10 stops is close to the scan chain length, it can be measured in real time whether the clock frequency is within the expected minimum and maximum frequency range. Thus, the variation trend of the frequency of the high-speed on-chip clock (i.e., the frequency of the clock signal pll _ clk to be tested) during the TDF Pattern test can be intuitively reflected. As shown in FIG. 6, the frequency of the high-speed on-chip clock can be measured in real time in both Pattern N-1 and Pattern N.

Referring to fig. 4, 5 and 6, the first cycle number count _1 output by the first counting unit 10 is exemplified as 9-bits. When edt _ update =1 and triggered by a rising edge of the clock, the first counting unit 10 starts to count to zero, and remains unchanged after counting to a preset value 80 (hexadecimal) of the first cycle count _1.

In addition, the second period count _2 output by the second counting unit 20 is exemplified by 13-bits. When edt _ update =1, the second count unit 20 maintains a clear state. When edt _ update becomes 0 and is triggered on the rising edge of the high speed clock, the second counting unit 20 starts counting. When the enable condition of whether the second counting unit 20 continues counting is count _1< =9' h080, that is, when the first counting unit 10 stops counting, the second counting unit 20 simultaneously stops counting.

Fig. 7 is a schematic diagram of an alternative structure of a clock signal processing apparatus according to an embodiment of the present application, as shown in fig. 7,

in some embodiments of the present application, as shown in fig. 7, the clock signal processing device 90 includes: a frequency calculation unit 901. The frequency calculating unit 901 is configured to pre-store the frequency of the preset clock signal test _ clk and the corresponding preset value of the first period count _1, receive the final value of the second period count _2 corresponding to the clock signal pll _ clk to be tested, and calculate the frequency of the clock signal pll _ clk to be tested according to the frequency of the preset clock signal test _ clk, the preset value of the first period count _1, and the final value of the second period count _2.

In this embodiment, the frequency calculating unit 901 may pre-store the frequency of the preset clock signal test _ clk and the preset value of the first period number count _1, and after receiving the final value of the second period number count _2, may calculate the frequency of the clock signal pll _ clk to be measured by presetting the frequency of the clock signal test _ clk, the preset value of the first period number count _1, and the final value of the second period number count _2 according to the above expression (2).

Taking the values shown in fig. 2 as an example, the preset value C1 of the first cycle number count _1 is 80 (hexadecimal), namely 128 (decimal); the final value C2 of the second periodic number count _2 is 9EC (hexadecimal), i.e., 2540 (decimal); if the frequency of the preset clock signal test _ clk is 25MHz, the period T1 of the preset clock signal test _ clk is 40ns. The frequency calculation unit 901 can calculate the period T2 of the clock signal pll _ clk to be measured to be 2ns, that is, the frequency of the clock signal pll _ clk to be measured is 500MHz.

It can be understood that, because a proportional relationship exists between the preset value of the first period count _1 and the final value of the second period count _2, the frequency of the clock signal pll _ clk to be measured can be obtained through the final value of the second period count _2, and thus, the accurate measurement of the clock frequency on the high-speed chip can be realized.

In some embodiments of the present application, as shown in fig. 7, the clock signal processing apparatus 90 further includes: a decision unit 902. A determining unit 902, configured to receive a final value of the second periodic number count _2, and determine whether the final value of the second periodic number count _2 meets a first determination condition; the first determination condition is set based on an expected value of the frequency of the clock signal pll _ clk to be measured.

In this embodiment, the determining unit 902 may determine the final value of the second periodic number count _2, and determine whether the final value of the second periodic number count _2 meets the first determination condition. Here, the first determination condition is set based on the expected value of the frequency of the clock signal pll _ clk to be measured.

Taking the expected value of the frequency of the clock signal pll _ clk to be measured as 500MHz for example, the second cycle number count _2 corresponding to the expected value of the frequency of the clock signal pll _ clk to be measured is 2540 (decimal) as calculated by the above equation (2). 2540 The (decimal) notation is 0_1001_1110 _1100for binary numbers and 9EC for hexadecimal numbers. Furthermore, a certain margin may be set on the basis of 9EC (hexadecimal), a first determination condition is defined, and if the final value of the second periodic number count _2 satisfies the first determination condition, the frequency of the clock signal pll _ clk to be measured meets the expectation; if the final value of the second period count _2 does not satisfy the first determination condition, the frequency of the clock signal pll _ clk to be tested is faster or slower.

For example, 1 may be added or subtracted from 9EC (hexadecimal) to obtain an upper limit 9ED and a lower limit 9EB of the first determination condition. If the final value of the second period number count _2 is between 9EB (hexadecimal) and 9ED (hexadecimal), the frequency of the clock signal pll _ clk to be tested is in accordance with the expectation; if the final value of the second cycle number count _2 is less than 9EB (hexadecimal), the frequency of the clock signal pll _ clk to be tested is slower; if the final value of the second period count _2 is greater than 9ED (hexadecimal), the frequency of the clock signal pll _ clk to be tested is faster. The upper limit 9ED (hexadecimal) is 0_1001 \u1110 \u1101 when marked as binary, and is 2541 when marked as decimal, which can be calculated by the above formula (2), and the cycle of the clock signal to be tested pll _ clk corresponding to the upper limit 9ED is 1.99992ns, and the frequency of the clock signal to be tested pll _ clk corresponding to the upper limit 9ED is 500.20MHz; the lower limit 9EB (hexadecimal) is 0 \u1001 _1110 _1011when recorded as binary, and is 2539 when recorded as decimal, and it can be calculated by the above formula (2), the period of the clock signal to be measured pll _ clk corresponding to the lower limit 9EB is 2.00079ns, and the frequency of the clock signal to be measured pll _ clk corresponding to the lower limit 9EB is 499.80MHz, so that the frequency of the clock signal to be measured pll _ clk is slower when the frequency of the clock signal to be measured pll _ clk is less than 499.80MHz, and faster when the frequency of the clock signal to be measured pll _ clk is greater than 500.20 MHz.

It is understood that the first determination condition may be set according to the expected final value of the second periodic number count _2, and the obtained final value of the second periodic number count _2 may be determined, so that it may be measured whether the clock frequency is within the expected lowest and highest frequency ranges in real time during the scan test TDF Pattern.

In some embodiments of the present application, as shown in fig. 7, the clock signal processing apparatus 90 further includes: a screening unit 903. The screening unit 903 is configured to receive a final value of the at least one second periodic number count _2 corresponding to the at least one chip to be tested, and determine the final value of the at least one second periodic number count _2 according to a second determination condition, so as to screen a compliant chip from the at least one chip to be tested; the second determination condition is set based on the first determination condition.

In the embodiment of the present application, the clock signal processing apparatus 90 may measure the clock signal pll _ clk to be tested in the at least one chip to be tested, and output the final value of the at least one second period count _2 corresponding to the at least one chip to be tested through the second counting unit 20. The screening unit 903 may receive the final values of the at least one second period number count _2 corresponding to the at least one chip to be tested, respectively, and determine the final values of the at least one second period number count _2 according to a second determination condition, so as to screen a compliant chip from the at least one chip to be tested.

In the embodiment of the present application, the second determination condition may be set based on the first determination condition. The intersection of the allowed values in the first decision condition may be selected as the allowed value of the second decision condition. For example, the first determination condition is 9EB (hexadecimal) to 9ED (hexadecimal), the intersection of 9EB, 9EC, and 9ED is 0_, 1001, 1110, 1xxx (binary), where X represents any value of 1 or 0, i.e., the other bits of 9EB, 9EC, and 9ED except the last three bits are the same. In this way, the second determination condition can be set as to whether 0 \u1001 \u1110 \u1xxx is satisfied, that is, the second determination condition is set as between 0 _u1001 \u1110 _ (binary) and 0 _u1001 _1110_ (binary), and correspondingly, the frequency range of the clock signal pll _ clk to be measured should be between 499.21MHz and 500.59 MHz. In this way, if the final value of the second cycle count _2 satisfies 0 \u1001 \u1110 \u1xxx, the screening unit 903 may determine that the corresponding chip to be tested is a compliant chip, and otherwise, the corresponding chip is a non-compliant chip.

It can be understood that the final value of the second period number count _2 corresponding to the chip to be tested is determined by setting the second determination condition, so that the chip to be tested can be screened during mass production, unqualified chips with clock frequencies which are not in line with expectations are screened out, and the chip testing process is completed.

It can be understood that, because a proportional relationship exists between the preset value of the first period count _1 and the final value of the second period count _2, the frequency of the clock signal pll _ clk to be measured can be obtained through the final value of the second period count _2, and thus, the accurate measurement of the clock frequency on the high-speed chip can be realized.

It should be noted that, with reference to fig. 4 and fig. 7, the final value of the second periodic number count _2 may be output to the tester ATE by the clock signal measuring circuit 80 for observation, and then the frequency calculating unit 901, the determining unit 902 and the screening unit 903 acquire the final value of the second periodic number count _2 from the tester ATE.

Fig. 8 is an alternative structural schematic diagram of a chip according to an embodiment of the present disclosure, and as shown in fig. 8, the chip 100 includes the clock signal measurement circuit 80 according to the embodiment.

It should be noted that, in conjunction with fig. 4 and fig. 8, the chip 100 shown in fig. 8 further includes the PADs (PADs) and the delay locked loop PLL shown in fig. 4.

In the embodiment of the present application, the clock signal measuring circuit 80 may be designed in the chip 100, so that in the chip 100, the frequency of the high-speed on-chip clock PLL _ clk output by the delay locked loop PLL can be accurately measured.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in a process, method, article, or apparatus comprising the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description, and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to arrive at new method embodiments. Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict. The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A clock signal measurement circuit, comprising: the device comprises a first counting unit, a counting control unit and a second counting unit;

the input end of the first counting unit receives a preset clock signal, the control end of the first counting unit receives an updating signal, and the first counting unit is used for starting to count the preset clock signal according to the updating signal to obtain and output a first period number;

the input end of the counting control unit receives the first period number, and the counting control unit is used for sending a starting instruction to the control end of the second counting unit when the first counting unit starts counting the preset clock signals and sending a stopping instruction to the control end of the second counting unit when the first period number reaches a preset value;

the input end of the second counting unit receives a clock signal to be measured, and the second counting unit is used for starting to count the clock signal to be measured in response to the starting instruction, and stopping to count the clock signal to be measured in response to the stopping instruction, so as to obtain and output a final value of a second period number.

2. The clock signal measurement circuit of claim 1, further comprising: a first register unit;

the input end of the first register unit is electrically connected to the output end of the second counting unit, and the first register unit is used for registering the final value of the second period number and outputting the final value of the second period number through the first output end of the first register unit.

3. The clock signal measurement circuit of claim 2, further comprising: a first control gate;

a first input end of the first control gate receives the preset clock signal, and an output end of the first control gate is electrically connected with an input end of the first counting unit;

the second output end of the first register unit is electrically connected with the second input end of the first control gate; the first register unit is further configured to output a first monitoring enable signal to a second input terminal of the first control gate through a second output terminal of the first register unit, so as to control the transmission of the preset clock signal to the first counting unit.

4. The clock signal measurement circuit of claim 3, further comprising: a second control gate;

a first input end of the second control gate receives the clock signal to be tested, and an output end of the second control gate is electrically connected with an input end of the second counting unit;

the second output end of the first register unit is also electrically connected with the second input end of the second control gate; the first register unit is further configured to output the first monitoring enable signal to a second input end of the second control gate through a second output end of the first register unit, so as to control the clock signal to be tested to be transmitted to the second counting unit.

5. The clock signal measurement circuit of claim 2, further comprising: a second register unit;

the input end of the second registering unit is electrically connected to the output end of the second counting unit, and the second registering unit is used for registering and outputting the final value of the second cycle number.

6. The clock signal measurement circuit of claim 5, wherein the final value of the second cycle number comprises m bits of data, the second register unit comprises m registers;

the data input ends of the m registers correspondingly receive the m bits of data one by one; the clock input ends of the m registers receive the preset clock signals;

the output end of each register is electrically connected with the scanning input end of the next register, and the output end of the mth register outputs the final value of the second period number.

7. The clock signal measurement circuit of claim 6, further comprising: m third control gates;

the first input ends of the m third control gates correspondingly receive the m bits of data one by one; the output ends of the m third control gates are electrically connected with the data input ends of the m registers in a one-to-one correspondence manner;

the third output end of the first register unit is electrically connected with the second input ends of the m third control gates; the first register unit is further configured to output a second monitor enable signal to second input terminals of the m third control gates through third output terminals thereof, so as to control a final value of the second cycle number to be transmitted to the second register unit.

8. A clock signal processing apparatus, characterized in that the clock signal processing apparatus comprises: a frequency calculation unit;

the frequency calculation unit is used for prestoring the frequency of a preset clock signal and a preset value corresponding to the first periodicity, receiving a final value of a second periodicity corresponding to the clock signal to be measured, and calculating the frequency of the clock signal to be measured according to the frequency of the preset clock signal, the preset value of the first periodicity and the final value of the second periodicity.

9. The clock signal processing apparatus of claim 8, further comprising: a determination unit;

the judging unit is used for receiving the final value of the second periodicity and judging whether the final value of the second periodicity meets a first judging condition or not; the first determination condition is set based on an expected value of the frequency of the clock signal to be measured.

10. The clock signal processing apparatus of claim 9, further comprising: a screening unit;

the screening unit is configured to receive a final value of at least one second cycle number corresponding to at least one chip to be tested, and determine the final value of the at least one second cycle number according to a second determination condition, so as to screen a compliance chip from the at least one chip to be tested; the second determination condition is set based on the first determination condition.

11. A chip comprising the clock signal measurement circuit of any one of claims 1 to 7.

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