CN115207054A - Display panel - Google Patents
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- CN115207054A CN115207054A CN202210793443.5A CN202210793443A CN115207054A CN 115207054 A CN115207054 A CN 115207054A CN 202210793443 A CN202210793443 A CN 202210793443A CN 115207054 A CN115207054 A CN 115207054A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The application discloses a display panel, which comprises a display area. The display panel includes a signal transmission layer and a display function layer. Wherein, the signal transmission layer is positioned in the display area. The signal transmission layer includes a gate driving circuit. The display function layer includes a pixel driving circuit layer and a light emitting function layer. The pixel driving circuit layer is disposed above the signal transmission layer. The light emitting function layer is arranged on one surface of the pixel driving circuit layer, which is far away from the signal transmission layer. The signal transmission layer used for transmitting signals to the display function layer is arranged below the display function layer, the signal transmission layer corresponds to the display area, the signal transmission layer does not occupy the space of a non-display area, the occupation ratio of the display area of the display surface of the display panel is improved, the narrow-frame or frameless design is achieved, and user experience is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
With the continuous update of electronic products, electronic products with large screens are more and more favored by users. At present, electronic products in the market always have larger or smaller peripheral frames, and the development trend of the electronic products requires that the peripheral frames of the electronic products are narrower so as to achieve the effect of no peripheral frame. The full-screen electronic product is one of the most popular technologies at present due to its ultra-high screen occupation ratio and excellent user experience. However, in the actual production process, the borderless requirement is difficult to meet, so that the occupation ratio of the screen display area to the front of the machine body is small, and the experience of a user is influenced.
Disclosure of Invention
The embodiment of the application provides a display panel, which is used for improving the proportion of a display area of a front body of the display panel.
The embodiment of the present application provides a display panel, display panel includes:
the signal transmission layer is positioned in the display area and comprises a grid driving circuit;
the display function layer comprises a pixel driving circuit layer and a light emitting function layer, the pixel driving circuit layer is arranged on the signal transmission layer, and the light emitting function layer is arranged on one surface, far away from the signal transmission layer, of the pixel driving circuit layer.
Optionally, in some embodiments provided in the present application, the display panel further includes a first signal connection line, where the first signal connection line is located in the display area, and the first signal connection line is used to connect the pixel driving circuit layer and the signal transmission layer.
Optionally, in some embodiments provided herein, the first signal connection line includes a first signal connection segment, a second signal connection segment and a third signal connection segment connected; the display panel comprises a first through hole, a second through hole and a third through hole, the first signal connection section is arranged in the first through hole, the second signal connection section is arranged in the second through hole, and the third signal connection section is arranged in the third through hole.
Optionally, in some embodiments provided in the present application, the signal transmission layer further includes a plurality of first power traces, a plurality of second power traces, a plurality of reset signal traces, an array test pad, and a plurality of sector traces; wherein
The first signal connecting section is connected with the gate driving circuit, the first power supply wire, the second power supply wire, the reset signal wire, the array testing pad or the fan-shaped wire, and the third signal connecting section is connected with the pixel driving circuit layer.
Optionally, in some embodiments provided in the present application, the display panel further includes a second signal connection line, where the second signal connection line is located in the display area, and the second signal connection line is used to connect the pixel driving circuit layer and the signal transmission layer.
Optionally, in some embodiments provided herein, the second signal connection line includes a fourth signal connection segment, a fifth signal connection segment and a sixth signal connection segment connected; the display panel comprises a fourth through hole, a fifth through hole and a sixth through hole, the fourth signal connection section is arranged in the fourth through hole, the fifth signal connection section is arranged in the fifth through hole, and the sixth signal connection section is arranged in the sixth through hole.
Optionally, in some embodiments provided in the present application, the signal transmission layer further includes a plurality of first power traces, a plurality of second power traces, a plurality of reset signal traces, an array test pad, and a plurality of sector traces; wherein
The fourth signal connection section is connected with the gate driving circuit, the first power supply wire, the second power supply wire, the reset signal wire, the array test pad or the fan-shaped wire, and the sixth signal connection section is connected with the pixel driving circuit layer.
Optionally, in some embodiments provided herein, the display panel further includes a first connection terminal and a second connection terminal; the gate driving circuit includes a first thin film transistor including a first active layer, a first gate electrode, a second gate electrode, a first source electrode, and a first drain electrode, and the signal transmission layer further includes:
a substrate on which the first active layer is disposed;
the first grid electrode insulating layer is arranged on the substrate, the first grid electrode is arranged on the substrate, and the first connecting terminal and the first grid electrode are arranged on the same layer and are made of the same material;
the second grid electrode insulating layer is arranged on the first grid electrode insulating layer, the second grid electrode insulating layer covers the first grid electrode and the first connecting terminal, the second grid electrode and the second connecting terminal are arranged on the second grid electrode insulating layer, and the second grid electrode and the second connecting terminal are arranged on the same layer and are made of the same material;
a first interlayer insulating layer disposed on the second gate insulating layer, the first interlayer insulating layer covering the second gate and the second connection terminal, the first via hole penetrating the first interlayer insulating layer and the second gate insulating layer, the first signal connection section being connected to the first connection terminal through the first via hole, the fourth via hole penetrating the first interlayer insulating layer, the fourth signal connection section being connected to the second connection terminal through the fourth via hole, the first source and the first drain being connected to the first active layer through the first contact hole and the second contact hole, respectively;
the second interlayer insulating layer is arranged on the first interlayer insulating layer, the second via hole penetrates through the second interlayer insulating layer, the second signal connection section is connected with the first signal connection section through the second via hole, the fifth via hole penetrates through the second interlayer insulating layer, and the fifth signal connection section is connected with the fourth signal connection section through the fifth via hole.
Optionally, in some embodiments provided herein, the display panel further includes a third connection terminal and a fourth connection terminal; the pixel driving circuit layer includes:
a base layer disposed on the second interlayer insulating layer;
a second active layer disposed on the base layer;
the insulating layer is arranged on one surface, far away from the substrate layer, of the second active layer, the sixth via hole penetrates through the insulating layer and the substrate layer, and the sixth signal connecting section is connected with the fifth signal connecting section through the sixth via hole;
the third connecting terminal is connected with the sixth signal connecting section, is the same as the third gate electrode in layer and is made of the same material;
the interlayer dielectric layer is arranged on one surface, far away from the insulating layer, of the third grid electrode, the third via hole penetrates through the interlayer dielectric layer, the insulating layer and the basal layer, and the third signal connecting section is connected with the second signal connecting section through the third via hole;
the second source electrode and the second drain electrode are arranged on the interlayer dielectric layer and are respectively connected with the second active layer through a third contact hole and a fourth contact hole, the fourth connecting terminal and the second source electrode are made of the same layer and material, and the fourth connecting terminal is connected with the third signal connecting section;
and the planarization layer is arranged on the interlayer dielectric layer.
Optionally, in some embodiments provided by the application, the signal transmission layer further includes a light shielding layer, the light shielding layer is disposed on the second interlayer insulating layer, the light shielding layer is connected to the first drain electrode through a via hole, and an orthographic projection of the light shielding layer on the substrate covers an orthographic projection of the second active layer on the substrate.
Optionally, in some embodiments provided in the present application, the display panel further includes a seventh via hole, where the seventh via hole penetrates through a part of the insulating layer of the signal transmission layer; the signal transmission layer further comprises a connecting wire and a connecting pad, the connecting pad is arranged on one surface, far away from the first interlayer insulating layer, of the substrate, the connecting wire is arranged in the seventh through hole, one end of the connecting wire is connected with the connecting pad, and the other end of the connecting wire is connected with the pixel driving circuit layer.
Optionally, in some embodiments provided by the present application, the display panel further includes a driving chip, the driving chip is disposed on a surface of the substrate away from the first interlayer insulating layer, and the driving chip is connected to the connection pad.
Optionally, in some embodiments provided herein, the pixel driving circuit layer includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and an organic light emitting diode; the first transistor and the second transistor, wherein the first transistor is a driving thin film transistor.
The embodiment of the application provides a display panel, which comprises a display area. The display panel includes a signal transmission layer and a display function layer. Wherein, the signal transmission layer is positioned in the display area. The signal transmission layer includes a gate driving circuit. The display function layer includes a pixel driving circuit layer and a light emitting function layer. The pixel driving circuit layer is disposed on the signal transmission layer. The light-emitting function layer is arranged on one surface of the pixel driving circuit layer, which is far away from the signal transmission layer. The signal transmission layer that this application embodiment will be used for showing the functional layer transmission signal sets up in the below that shows the functional layer, and the signal transmission layer is corresponding to the display area, that is to say, this application embodiment will be used for providing the metal of signal for the pixel drive circuit of display area and walk the line setting in the display area, consequently, the signal transmission layer does not occupy the space in non-display area, improves the proportion of the display area of display panel's display surface, thereby realize narrow frame or frameless's design, improve user experience.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a signal transmission layer according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display functional layer provided in an embodiment of the present application;
fig. 5 is a circuit diagram of a pixel driving circuit layer according to an embodiment of the present disclosure.
Fig. 6 is a schematic view illustrating a manufacturing method of a display panel according to an embodiment of the present disclosure.
Detailed Description
For purposes of clarity, technical solutions and advantages of the present application, the present application will be described in further detail with reference to the accompanying drawings, wherein like reference numerals represent like elements throughout the several views, and the following description is based on the illustrated embodiments of the present application and should not be construed as limiting the other embodiments of the present application which are not detailed herein. The word "embodiment" as used herein means an example, instance, or illustration.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
The embodiment of the application provides a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The embodiment of the application provides a display panel, which comprises a display area. The display panel includes a signal transmission layer and a display function layer. Wherein, the signal transmission layer is positioned in the display area. The signal transmission layer includes a gate driving circuit. The display function layer includes a pixel driving circuit layer and a light emitting function layer. The pixel driving circuit layer is disposed on the signal transmission layer. The light emitting function layer is arranged on one surface of the pixel driving circuit layer, which is far away from the signal transmission layer. The signal transmission layer used for transmitting signals to the display function layer is arranged below the display function layer, the signal transmission layer corresponds to the display area, the signal transmission layer does not occupy the space of a non-display area, the occupation ratio of the display area of the display surface of the display panel is improved, the narrow-frame or frameless design is achieved, and user experience is improved.
The display panel provided by the present application is explained in detail by specific embodiments below.
In the prior art, a frame region of a display panel is provided with a gate driving circuit and metal routing lines, and the gate driving circuit and the metal routing lines occupy a large area ratio of a front screen of the display panel, so that the area ratio of a display region of the screen of the display panel is small, and a real narrow frame design cannot be realized.
The embodiment of the application provides a display panel for improve the proportion of the display area of the display surface of the display panel, thereby realizing the design of narrow frame or no frame and improving the user experience.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. Fig. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure. The display panel 100 includes a display area AA. The display panel 100 includes a signal transmission layer 10, a display function layer 20, and a first signal connection line 40. Wherein the signal transmission layer 10 is located in the display area AA. The signal transmission layer 10 includes a gate driving circuit 102. The display function layer 20 includes a pixel driving circuit layer 20a and a light emitting function layer 20b, the pixel driving circuit layer 20a is disposed above the signal transmission layer 10, and the light emitting function layer 20b is disposed on a side of the pixel driving circuit layer 20a away from the signal transmission layer 10. The first signal connection line 40 is for connecting the signal transfer layer 10 and the pixel driving circuit layer 20a.
The signal transmission layer 10 used for transmitting signals to the display function layer 20 is arranged below the display function layer 20, so that the signal transmission layer 10 is located in the display area AA, therefore, the signal transmission layer does not occupy the space of a non-display area, the occupation ratio of the display area AA of the display panel 100 is improved, the design of a narrow frame or no frame is realized, the taste of the display panel 100 is improved, and the user experience is improved.
The first signal connecting line 40 is located in the display area AA.
In some embodiments, the display panel 100 further includes a second signal connection line 50, and the second signal connection line 50 is located in the display region. The second signal connection line 50 is for connecting the pixel driving circuit layer 20a and the signal transmission layer 10.
Specifically, the first signal connection line 40 includes a first signal connection segment 401, a second signal connection segment 402 and a third signal connection segment 403. The second signal connection line 50 includes a fourth signal connection segment 501, a fifth signal connection segment 502 and a sixth signal connection segment 503 connected.
The display panel 100 includes a first via hole h1, a second via hole h2, a third via hole h3, a fourth via hole h4, a fifth via hole h5, and a sixth via hole h6. The first signal connection section 401 is disposed in the first via hole h1, the second signal connection section 402 is disposed in the second via hole h2, and the third signal connection section 403 is disposed in the third via hole h 3. The fourth signal connection section 501 is disposed in the fourth via hole h4, the fifth signal connection section 502 is disposed in the fifth via hole h5, and the sixth signal connection section 503 is disposed in the sixth via hole h6.
The display panel 100 further includes a first connection terminal a1, a second connection terminal a2, a third connection terminal a3, and a fourth connection terminal a4. The first connection terminal a1 is connected to the first signal connection section 401, the fourth connection terminal a4 is connected to the third signal connection section 403, the second connection terminal a2 is connected to the fourth signal connection section 501, and the third connection terminal a3 is connected to the sixth signal connection section 503.
The signal transmission layer 10 further includes a plurality of first power traces 110, a plurality of second power traces 111, a plurality of reset signal traces 113, an array test pad 114, and a plurality of sector traces 115. The first signal connection segment 401 is connected to the gate driving circuit 102, the first power trace 110, the second power trace 111, the reset signal trace 113, the array test pad 114, or the sector trace 115. The third signal connection segment 403 is connected to the pixel driving circuit layer 20a. Specifically, the output ends of the gate driving circuit 102, the first power trace 110, the second power trace 111, the reset signal trace 113, the array test pad 114 or the sector trace 115 are connected to the first connection terminal a1, so that the corresponding signal is transmitted through the first signal connection line 40, and the fourth connection terminal a4 is connected to the transistor or the metal trace corresponding to the pixel driving circuit layer 20a, thereby implementing signal transmission.
In some embodiments, the fourth signal connection segment 501 is connected to the gate driving circuit 102, the first power trace 110, the second power trace 111, the reset signal trace 113, the array test pad 114, or the sector trace 115. The sixth signal connection segment 503 is connected to the pixel driving circuit layer 20a. Specifically, the output ends of the gate driving circuit 102, the first power trace 110, the second power trace 111, the reset signal trace 113, the array test pad 114 or the sector trace 115 are connected to the second connection terminal a2, so that the corresponding signal is transmitted through the second signal connection line 50, and the third connection terminal a3 is connected to the transistor or the metal trace corresponding to the pixel driving circuit layer 20a, thereby implementing signal transmission.
In this embodiment of the application, the first power trace 110, the second power trace 111, the reset signal trace 113, the array test pad 114, and the plurality of fan-shaped traces 115 are all disposed below the display function layer 20 and all correspond to the display area AA, and at this time, a non-display area for placing metal traces does not need to be disposed, so that a frameless design of the display panel 100 is realized, a real full-face screen is realized, and user experience is greatly improved.
It should be noted that, in the embodiment of the present application, the sector trace 115 may be a metal trace for leading out a data line of the pixel driving circuit layer, but is not limited thereto.
Specifically, please refer to fig. 3, wherein fig. 3 is a schematic structural diagram of a signal transmission layer according to an embodiment of the present disclosure. The gate driving circuit 102 includes a first thin film transistor structure 102a. The first thin film transistor structure 102a includes a first active layer 1021, a first gate electrode 1022, a second gate electrode 1023, a first source electrode 1024, and a first drain electrode 1025. The signal transfer layer 10 further includes a substrate 101, a first gate insulating layer 103, a second gate insulating layer 104, a first interlayer insulating layer 105, and a second interlayer insulating layer 106.
A first gate insulating layer 103 is disposed on the substrate 101. The first gate 1022 is disposed on the substrate 101, and the first connection terminal a1 and the first gate 1022 are at the same layer and are made of the same material.
The second gate insulating layer 104 is disposed on the first gate insulating layer 103. The second gate insulating layer 104 covers the first gate electrode 1022 and the first connection terminal a1. The second gate electrode 1023 and the second connection terminal a2 are disposed on the second gate insulating layer 104, and the second gate electrode 1023 and the second connection terminal a2 are in the same layer and material.
The first interlayer insulating layer 105 is disposed on the second gate insulating layer 104, and the first interlayer insulating layer 105 covers the second gate electrode 1023 and the second connection terminal a2. The first via hole h1 penetrates the first interlayer insulating layer 105 and the second gate insulating layer 104, and the first signal connection section 401 is connected to the first connection terminal a1 through the first via hole h 1. The fourth via hole h4 penetrates the first interlayer insulating layer 105, and the fourth signal connection section 501 is connected to the second connection terminal a2 through the fourth via hole h 4.
The first source 1024 and the first drain 1025 are connected to the first active layer 1021 through first and second contact holes cnt1 and cnt2, respectively.
The second interlayer insulating layer 106 is disposed on the first interlayer insulating layer 105, and the second via hole h2 penetrates the second interlayer insulating layer 106. The second signal connection section 402 is connected to the first signal connection section 401 through a second via h 2. The fifth via hole h5 penetrates through the second interlayer insulating layer 106, and the fifth signal connection section is connected to the fourth signal connection section through the fifth via hole.
In the embodiment of the present application, the thin film transistor of the gate driving circuit 102 may be a bottom gate thin film transistor, a top gate thin film transistor, or a dual gate thin film transistor, and the application takes the gate driving circuit 102 as the dual gate thin film transistor as an example for illustration, but is not limited thereto.
In some embodiments, the first active layer 1021 is a Low Temperature Polysilicon (LTPS) active layer, and Low Temperature Polysilicon (LTPS) technology is yet another new technology in the field of flat panel displays, next generation technology following amorphous Silicon (a-Si). The low-temperature polysilicon display panel has the advantages of faster electron mobility, smaller thin film circuit area, higher resolution, lower power consumption, higher stability and the like.
Referring to fig. 2 and fig. 4, fig. 4 is a schematic structural diagram of a display functional layer according to an embodiment of the present disclosure. The pixel driving circuit layer 20a includes a base layer 201, a second active layer 202, a third gate 204 insulating layer 203, a third gate 204, an interlayer dielectric layer 205, a second source 206, a second drain 207, and a planarization layer 208.
The base layer 201 is provided on a surface of the second interlayer insulating layer 106 remote from the first interlayer insulating layer 105. The second active layer 202 is disposed on a surface of the base layer 201 away from the second interlayer insulating layer 106, and an orthographic projection of the second active layer 202 on the substrate 101 is located within an orthographic projection of the light-shielding layer 108 and the substrate 101.
The insulating layer 203 is disposed on a side of the second active layer 202 away from the base layer 201. The sixth via h6 penetrates the insulating layer 203 and the base layer 201, and the sixth signal connecting section 503 is connected through the sixth via h6 and the fifth signal connecting section 502.
The third gate electrode 204 is disposed on a side of the insulating layer 203 away from the second active layer 202. The third connection terminal a3 and the sixth signal connection section 503 are connected and are in the same layer and material as the third gate electrode 204.
An interlayer dielectric layer 205 is disposed on a side of the third gate 204 away from the insulating layer 203. The third via hole h3 penetrates through the interlayer dielectric layer 205, the insulating layer 203 and the base layer 201, and the third signal connection section 403 is connected to the second signal connection section 402 through the third via hole h 3.
The pixel driving circuit layer 20a has a third contact hole cnt3 and a fourth contact hole cnt4. The third contact hole cnt3 and the fourth contact hole cnt4 penetrate the interlayer dielectric layer 205.
The second source electrode 206 and the second drain electrode 207 are disposed on the interlayer dielectric layer 205 and connected to the second active layer 202 through the third contact hole cnt3 and the fourth contact hole cnt4, respectively. The fourth connection terminal a4 and the second source 206 are formed of the same layer and material, and the fourth connection terminal a4 and the third signal connection section 403 are connected.
A planarization layer 208 is disposed on the interlayer dielectric layer 205 and covers the second source electrode 206 and the second drain electrode 207.
In this application embodiment, punch to different retes respectively for form the connecting signal section that corresponds in the via hole of difference when forming the metal level, constitute signal connection by a plurality of signal connection section connection and walk the line. That is, the first signal connection lines 40 and the second signal connection lines 50 of the embodiment of the present disclosure are formed in the process of forming the metal traces required by the display panel 100, and no additional process is required, thereby reducing the production cost of the display panel 100.
In some embodiments, the second active layer 202 is a metal oxide active layer. The material of the second active layer 202 may be selected from indium gallium zinc oxide.
The metal oxide semiconductor has the characteristics of high mobility, high on-state current, better switching characteristic and better uniformity, and can be suitable for applications requiring quick response and larger current, such as high-frequency, high-resolution and large-size displays, organic light emitting displays and the like.
The light emitting functional layer 20b includes an anode 210, a pixel defining layer 209, a light emitting layer 211, and a cathode 212. Wherein the anode 210 is connected to the second drain electrode 207 through a via hole. The pixel defining layer 209 has an opening, and the opening of the pixel defining layer 209 exposes a surface of the anode 210. The light emitting layer 211 is disposed in the opening of the pixel defining layer 209. The cathode 212 is disposed on a side of the light-emitting layer 211 remote from the anode 210.
In some embodiments, the signal transmission layer 10 further includes a light shielding layer 108. The light shielding layer 108 is disposed on a surface of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105, and the light shielding layer 108 is connected to the first drain electrode 1025 through a via hole. The orthographic projection of the light shielding layer 108 on the substrate 101 covers the orthographic projection of the second active layer 202 on the substrate 101. In the embodiment of the present application, by providing the light shielding layer 108 connected to the first drain 1025, the light shielding layer 108 can be used to reduce the electromagnetic interference of the signal transmission layer 10 to the display function layer 20, and can shield the external light incident from the substrate 101 side, thereby improving the stability of the display panel 100.
In some embodiments, the display panel 100 further includes a seventh via hole h7, and the seventh via hole h7 penetrates through a portion of the insulating layer of the signal transmission layer 10. The signal transmission layer 10 further includes a connection trace 107 and a connection pad 109, and the connection pad 109 is disposed on a side of the substrate 101 away from the first interlayer insulating layer 105. The connection trace 107 is disposed in the seventh via hole h7, one end of the connection trace h7 is connected to the connection pad 109, and the other end of the connection trace 107 is connected to the pixel driving circuit layer 20a.
In some embodiments, the seventh via hole h7 penetrates the first interlayer insulating layer 106, the second gate insulating layer 104, the first gate insulating layer 103, and the substrate 101.
In some embodiments, the connection traces 107 are used to connect data lines on the pixel driving circuit layer 20a to the connection pads 109, but are not limited thereto.
The display panel 100 further includes a driving chip 30. The driver chip 30 is provided with a connection pad 109 on a side away from the substrate 101. The driving chip 30 is used for driving the display panel 100 to emit light.
In the embodiment of the present application, the driving chip 30 is bound to the side of the signal transmission layer 10 away from the display function layer 20, that is, the driving chip 30 is bound to the back side, compared with the prior art in which the driving chip is bound to the back side of the display panel by bending, the frame of the display panel 100 is further reduced, and the ratio of the display area AA of the display surface of the display panel 100 is increased.
It is noted that in some embodiments, connection pads 109 include chip connection pads and test connection pads. The arrangement mode of the connection pads and the test connection pads is not limited in the embodiment of the application.
Referring to fig. 1, the gate driving circuit 102 corresponds to an outer edge of the display area AA. The first power trace 110 is disposed outside the gate driving circuit 102. The second power trace 111 is disposed on a side close to the connection pad 109. The reset signal trace 113 is disposed inside the gate driving circuit 102. The array test pad 114 is disposed on a side of the second power trace 111 away from the connection pad 109. The sector trace 115 is disposed between the second power trace 111 and the connection pad 109 for connecting the second power trace 111 and the connection pad 109.
In some embodiments, the substrate 101 includes an inorganic layer 1011, a first flexible substrate layer, a first barrier layer 1013, and a second barrier layer 1014 disposed in a sequential stack. The first active layer 1021 is disposed on the second barrier layer 1014. The connection pads 109 are arranged on the side of the inorganic layer 1011 remote from the first flexible substrate layer 1012.
In some embodiments, the material of the first flexible substrate layer 1012 may include at least one of PI (polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene with polyarylate), or PCO (polycyclic olefin). The inorganic layer 1011, the first barrier layer 1013, and the second barrier layer 1014 are formed of a stacked structure of one or two or more of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride.
In some embodiments, the pixel driving circuit layer 20a includes a pixel driving circuit, and the pixel driving circuit may include a 3T1C type pixel driving circuit, a 4T2C type pixel driving circuit, a 5T2C type pixel driving circuit, or a 6T1C type pixel driving circuit.
Referring to fig. 5, fig. 5 is a circuit diagram of a pixel driving circuit layer according to an embodiment of the present disclosure. The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and an organic light emitting diode OLED. Each transistor is a P-type thin film transistor. The first transistor T1 is a driving thin film transistor, a gate of the first transistor T1 is electrically connected to one end of the first capacitor (C1) through the first node (a), and a source of the first transistor T1 is connected to a positive voltage of the second power trace 111. The drain of the first transistor T1 is electrically connected to the anode of the organic light emitting diode OLED. The gate of the second transistor T2 is connected to the nth SCAN signal SCAN (n) corresponding to the row where the pixel driving circuit is located, the source of the second transistor T2 is connected to the data signal data, and the drain of the second transistor T2 is electrically connected to the other end of the first capacitor C1 through the second node B. The gate of the third transistor T3 is connected to the (n + 1) th SCAN signal SCAN (n + 1) corresponding to the next row of the pixel driving circuit, the source of the third transistor T3 is electrically connected to the second node B, and the drain is connected to the reference voltage Vref. The gate of the fourth transistor T4 is connected to the nth SCAN signal SCAN (n) corresponding to the row of the pixel driving circuit, the source of the fourth transistor T4 is electrically connected to the first node a, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode OLED.
One end of the first capacitor C1 is electrically connected to the first node a, and the other end is electrically connected to the second node B. One end of the second capacitor C2 is electrically connected to the first node a, and the other end is electrically connected to the second power trace 111. The anode of the organic light emitting diode OLED is electrically connected to the drain of the first transistor T1 and the drain of the fourth transistor T4, and the cathode is electrically connected to the first power trace 110.
Compared with the existing pixel driving circuit, the pixel driving circuit provided by the invention has the advantages that only the scanning signal is needed to be set to control the corresponding thin film transistor, so that the compensation effect is realized, the number of control signals is reduced, the circuit structure is simplified, and the cost is reduced.
Accordingly, an embodiment of the present application further provides a method for manufacturing a display panel, please refer to fig. 6. The manufacturing method of the display panel comprises the following steps:
and step B001, providing a signal transmission layer, wherein the signal transmission layer is positioned in the display area of the display panel.
Wherein the step of providing a signal transmission layer comprises providing a flexible substrate and then providing connection pads 109 on the flexible substrate.
Next, an inorganic layer 1011 and a first flexible substrate layer 1012 are provided in this order over the flexible substrate 1015.
Subsequently, the gate driver circuit 102 is disposed on the first flexible substrate layer 1012, thereby forming a signal transmission layer.
In some embodiments, the signal transmission layer further includes a plurality of first power traces, a plurality of second power traces, a plurality of reset signal traces, an array test pad, and a plurality of sector traces.
And step B002, arranging a display function layer on the signal transmission layer, wherein the display function layer comprises a pixel driving circuit layer and a light-emitting function layer. The pixel driving circuit layer is disposed on the signal transmission layer. The light emitting function layer is arranged on one surface of the pixel driving circuit layer, which is far away from the signal transmission layer.
Step B003, the flexible substrate 1015 is peeled off by laser peeling, mechanical peeling, solvent peeling, or the like, thereby exposing the connection pads.
And step B003, binding the driving chip on the connecting bonding pad so as to finish the manufacture of the display panel.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application is defined by the appended claims.
Claims (13)
1. A display panel, comprising a display region, the display panel comprising:
the signal transmission layer is positioned in the display area and comprises a grid driving circuit;
the display functional layer comprises a pixel driving circuit layer and a light-emitting functional layer, the pixel driving circuit layer is arranged above the signal transmission layer, and the light-emitting functional layer is arranged on one surface, far away from the signal transmission layer, of the pixel driving circuit layer.
2. The display panel according to claim 1, further comprising a first signal connection line in the display region, the first signal connection line connecting the pixel driving circuit layer and the signal transmission layer.
3. The display panel according to claim 2, wherein the first signal connection line includes a first signal connection section, a second signal connection section, and a third signal connection section connected; the display panel comprises a first through hole, a second through hole and a third through hole, the first signal connection section is arranged in the first through hole, the second signal connection section is arranged in the second through hole, and the third signal connection section is arranged in the third through hole.
4. The display panel of claim 3, wherein the signal transmission layer further comprises a plurality of first power traces, a plurality of second power traces, a plurality of reset signal traces, an array test pad, and a plurality of sector traces; wherein
The first signal connection section is connected with the gate driving circuit, the first power supply wire, the second power supply wire, the reset signal wire, the array test pad or the fan-shaped wire, and the third signal connection section is connected with the pixel driving circuit layer.
5. The display panel according to claim 3, further comprising a second signal connection line in the display region, the second signal connection line connecting the pixel driving circuit layer and the signal transmission layer.
6. The display panel according to claim 5, wherein the second signal connection line comprises a fourth signal connection segment, a fifth signal connection segment and a sixth signal connection segment connected; the display panel comprises a fourth through hole, a fifth through hole and a sixth through hole, the fourth signal connection section is arranged in the fourth through hole, the fifth signal connection section is arranged in the fifth through hole, and the sixth signal connection section is arranged in the sixth through hole.
7. The display panel according to claim 6, wherein the signal transmission layer further comprises a plurality of first power traces, a plurality of second power traces, a plurality of reset signal traces, an array test pad, and a plurality of sector traces; wherein
The fourth signal connection section is connected with the gate driving circuit, the first power supply wire, the second power supply wire, the reset signal wire, the array test pad or the fan-shaped wire, and the sixth signal connection section is connected with the pixel driving circuit layer.
8. The display panel according to claim 6, wherein the display panel further comprises a first connection terminal and a second connection terminal; the gate driving circuit includes a first thin film transistor including a first active layer, a first gate electrode, a second gate electrode, a first source electrode, and a first drain electrode, and the signal transmission layer further includes:
a substrate on which the first active layer is disposed;
the first grid electrode insulating layer is arranged on the substrate, the first grid electrode is arranged on the substrate, and the first connecting terminal and the first grid electrode are arranged on the same layer and are made of the same material;
the second grid electrode insulating layer is arranged on the first grid electrode insulating layer, the second grid electrode insulating layer covers the first grid electrode and the first connecting terminal, the second grid electrode and the second connecting terminal are arranged on the second grid electrode insulating layer, and the second grid electrode and the second connecting terminal are arranged on the same layer and are made of the same material;
a first interlayer insulating layer disposed on the second gate insulating layer, the first interlayer insulating layer covering the second gate and the second connection terminal, the first via hole penetrating the first interlayer insulating layer and the second gate insulating layer, the first signal connection section being connected to the first connection terminal through the first via hole, the fourth via hole penetrating the first interlayer insulating layer, the fourth signal connection section being connected to the second connection terminal through the fourth via hole, the first source and the first drain being connected to the first active layer through the first contact hole and the second contact hole, respectively;
the second interlayer insulating layer is arranged on the first interlayer insulating layer, the second via hole penetrates through the second interlayer insulating layer, the second signal connection section is connected with the first signal connection section through the second via hole, the fifth via hole penetrates through the second interlayer insulating layer, and the fifth signal connection section is connected with the fourth signal connection section through the fifth via hole.
9. The display panel according to claim 8, wherein the display panel further comprises a third connection terminal and a fourth connection terminal; the pixel driving circuit layer includes:
a base layer disposed on the second interlayer insulating layer;
a second active layer disposed on the base layer;
the insulating layer is arranged on one surface, far away from the substrate layer, of the second active layer, the sixth via hole penetrates through the insulating layer and the substrate layer, and the sixth signal connecting section is connected with the fifth signal connecting section through the sixth via hole;
the third connecting terminal is connected with the sixth signal connecting section, is the same as the third gate electrode in layer and is made of the same material;
the interlayer dielectric layer is arranged on one surface, far away from the insulating layer, of the third grid electrode, the third via hole penetrates through the interlayer dielectric layer, the insulating layer and the basal layer, and the third signal connecting section is connected with the second signal connecting section through the third via hole;
the second source electrode and the second drain electrode are arranged on the interlayer dielectric layer and are respectively connected with the second active layer through a third contact hole and a fourth contact hole, the fourth connecting terminal and the second source electrode are made of the same layer and material, and the fourth connecting terminal is connected with the third signal connecting section;
a planarization layer disposed on the interlayer dielectric layer.
10. The display panel according to claim 9, wherein the signal transmission layer further includes a light shielding layer, the light shielding layer is disposed on the second interlayer insulating layer, the light shielding layer is connected to the first drain electrode through a via hole, and an orthographic projection of the light shielding layer on the substrate covers an orthographic projection of the second active layer on the substrate.
11. The display panel according to claim 8, wherein the display panel further comprises a seventh via hole penetrating a part of the insulating layer of the signal transmission layer; the signal transmission layer further comprises a connecting wire and a connecting pad, the connecting pad is arranged on one surface, far away from the first interlayer insulating layer, of the substrate, the connecting wire is arranged in the seventh through hole, one end of the connecting wire is connected with the connecting pad, and the other end of the connecting wire is connected with the pixel driving circuit layer.
12. The display panel according to claim 11, wherein the display panel further comprises a driver chip disposed on a side of the connection pad away from the substrate.
13. The display panel according to claim 1, wherein the pixel driving circuit layer comprises a pixel driving circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and an organic light emitting diode; the first transistor and the second transistor, wherein the first transistor is a driving thin film transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210793443.5A CN115207054A (en) | 2022-07-05 | 2022-07-05 | Display panel |
| PCT/CN2022/115997 WO2024007435A1 (en) | 2022-07-05 | 2022-08-30 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210793443.5A CN115207054A (en) | 2022-07-05 | 2022-07-05 | Display panel |
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| Publication Number | Publication Date |
|---|---|
| CN115207054A true CN115207054A (en) | 2022-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210793443.5A Pending CN115207054A (en) | 2022-07-05 | 2022-07-05 | Display panel |
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| Country | Link |
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| CN (1) | CN115207054A (en) |
| WO (1) | WO2024007435A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010627B (en) * | 2019-04-12 | 2021-02-02 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111341814A (en) * | 2020-03-11 | 2020-06-26 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN111768700B (en) * | 2020-06-22 | 2021-10-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| KR20220021966A (en) * | 2020-08-13 | 2022-02-23 | 삼성디스플레이 주식회사 | Display panel, manufacturing method for the same, and display device including the same |
| KR20220078932A (en) * | 2020-12-04 | 2022-06-13 | 엘지디스플레이 주식회사 | Display device |
| CN113013209A (en) * | 2021-02-19 | 2021-06-22 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN114203778A (en) * | 2021-11-30 | 2022-03-18 | 长沙惠科光电有限公司 | Active matrix OLED display panel and preparation method thereof |
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- 2022-07-05 CN CN202210793443.5A patent/CN115207054A/en active Pending
- 2022-08-30 WO PCT/CN2022/115997 patent/WO2024007435A1/en unknown
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| WO2024007435A1 (en) | 2024-01-11 |
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