CN115206358A - Sense amplifier and memory - Google Patents

Sense amplifier and memory Download PDF

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Publication number
CN115206358A
CN115206358A CN202210901507.9A CN202210901507A CN115206358A CN 115206358 A CN115206358 A CN 115206358A CN 202210901507 A CN202210901507 A CN 202210901507A CN 115206358 A CN115206358 A CN 115206358A
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transistor
state
stage input
signal
unit
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Chinese (zh)
Inventor
许明鑫
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

The embodiment of the disclosure discloses a sense amplifier and a memory, wherein the sense amplifier comprises: a first amplification module comprising: a first-stage input unit; the first end of the first-stage input unit is used for receiving a first-stage input signal, and the second end of the first-stage input unit is used for outputting a second-stage input signal; a second amplification module comprising: a second-stage input unit; the first end of the second-stage input unit is used for receiving a second-stage input signal; the second end of the second amplifying module is used for outputting a sensing amplifying signal; the first end of the second-stage input unit is the first end of the second amplification module; and the third end of the feedback module is connected with the third end of the first-stage input unit, the first end of the feedback module is used for receiving the first-stage input signal, and the second end of the feedback module is connected with the second end of the second-stage input unit and outputs a supplementary signal to the second end of the second-stage input unit.

Description

Sense amplifier and memory
Technical Field
The disclosed embodiments relate to the field of semiconductor technology, and relate to, but are not limited to, a sense amplifier and a memory.
Background
With the popularization of electronic devices such as mobile phones, tablets, personal computers, and the like, semiconductor memory technology has also been rapidly developed. Such as DRAM (Dynamic Random Access Memory), has been widely used in various electronic devices due to its advantages of high density, low power consumption, low price, etc.
A Sense Amplifier (SA) is an important component of a semiconductor memory, and has a main function of amplifying a small signal on a bit line to perform a read or write operation.
Sense amplifiers may also be used in other scenarios for comparing the magnitude between two slightly different signals.
The sensing speed of the sense amplifier is used as an important index for evaluating the performance of the sense amplifier, and the application scene of the memory is directly influenced. How to improve the sensing speed of the sense amplifier becomes a problem to be solved urgently.
Disclosure of Invention
Accordingly, the disclosed embodiments provide a sense amplifier and a memory.
In a first aspect, an embodiment of the present disclosure provides a sense amplifier, including:
a first amplification module comprising: a first-stage input unit; the first end of the first-stage input unit is used for receiving a first-stage input signal, and the second end of the first-stage input unit is used for outputting a second-stage input signal;
a second amplification module comprising: a second-stage input unit; the first end of the second-stage input unit is used for receiving the second-stage input signal; the second end of the second amplifying module is used for outputting a sensing amplifying signal; the first end of the second-stage input unit is the first end of the second amplification module;
and the third end of the feedback module is connected with the third end of the first-stage input unit, the first end of the feedback module is used for receiving the first-stage input signal, and the second end of the feedback module is connected with the second end of the second-stage input unit and outputs a supplementary signal to the second end of the second-stage input unit.
In some embodiments, the sense amplifier further comprises:
and the equalizing signal output end of the decision feedback equalizing module is connected with the first end of the second-stage input unit and is used for equalizing the second-stage input signal.
In some embodiments, the second amplification module further comprises:
the sensing amplification unit is connected with the second end of the second-stage input unit; the first end of the sensing amplification unit is used for receiving a signal of the second end of the second-stage input unit, and the second end of the sensing amplification unit is used for outputting the sensing amplification signal; the second end of the sensing amplifying unit is the second end of the second amplifying module.
In some embodiments, the sense amplifying unit includes:
a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; the second end of the second amplification module comprises a first output node and a second output node;
a second end of the first P-type transistor is connected with a second end of the first N-type transistor to serve as the first output node;
a second end of the second P-type transistor is connected with a second end of the second N-type transistor to serve as the second output node;
the first end of the first P-type transistor and the first end of the first N-type transistor are both connected to the second output node;
a first end of the second P-type transistor and a first end of the second N-type transistor are both connected to the first output node;
the third end of the first N-type transistor and the third end of the second N-type transistor are respectively connected with the second end of the second-stage input unit;
and the third ends of the first P-type transistor and the second P-type transistor are both connected with a first power supply end.
In some embodiments, a balancing unit is further connected between the third terminal of the first N-type transistor and the third terminal of the second N-type transistor; and when the balancing unit is in a conducting state, the third end of the first N-type transistor and the third end of the second N-type transistor are equipotential.
In some embodiments, the balancing unit includes a third P-type transistor in a conductive state when the sense amplifier is in a precharge state.
In some embodiments, the second amplification module further comprises:
the first state control unit is connected between the first power supply end and the second end of the second amplification module; the first end of the first state control unit is used for receiving a first control signal; the first control signal is used for enabling the first state control unit to be switched on or switched off;
when the first state control unit is in a conducting state, the sensitive amplifier is in a pre-charging state.
In some embodiments, the first state control unit comprises a first state transistor and a second state transistor;
the third end of the first state transistor is connected with the first power supply end; the second end of the first state transistor is connected with the second end of the first N-type transistor; the second end of the first state transistor is also connected with the first end of the second N-type tube; the first end of the first state transistor is used for receiving the first control signal;
the third end of the second state transistor is connected with the first power supply end; a second end of the second state transistor is connected with a second end of the second N-type transistor; the second end of the second state transistor is also connected with the first end of the first N-type tube; the first end of the second state transistor is used for receiving the first control signal.
In some embodiments, the first amplification module further comprises:
a second state control unit connected between the first-stage input unit and a first power source terminal; the first end of the second state control unit is used for receiving a second control signal; the second control signal is used for enabling the second state control unit to be switched on or switched off;
and when the second state control unit is in a conducting state, the sensitive amplifier is in a sampling state.
In some embodiments, the first amplification module further comprises:
a third state control unit connected between the first-stage input unit and a second power supply terminal; the first end of the third state control unit is used for receiving the second control signal; the second control signal is also used for enabling the third state control unit to be switched on or switched off;
the third state controls the transistor to be in a conducting state, and the sensitive amplifier is in a pre-charging state; the second state control unit and the third state control unit are not conducted at the same time.
In some embodiments, the third state control unit comprises: a third state transistor and a fourth state transistor;
a first end of the third state transistor is connected with a first end of the fourth state transistor;
a second terminal of the third state transistor is connected with a second terminal of the first stage input unit;
a second terminal of the fourth state transistor is connected to a second terminal of the first stage input unit.
In some embodiments, the first stage input signal comprises: sensing an input signal and a reference signal;
the first-stage input unit includes: a first input transistor and a second input transistor;
a first terminal of the first input transistor is to receive the sense input signal; the first terminal of the second input transistor is used for receiving the reference signal.
In some embodiments, the second-stage input unit includes: a third input transistor and a fourth input transistor;
a first terminal of the third input transistor is connected with a second terminal of the first input transistor;
a first terminal of the fourth input transistor is connected to a second terminal of the second input transistor.
In some embodiments, the feedback module comprises:
a first feedback transistor and a second feedback transistor;
the first end of the first feedback transistor is used for receiving the sensing input signal, and the second end of the first feedback transistor is connected with the second end of the fourth input transistor;
the first end of the second feedback transistor is used for receiving the reference signal, and the second end of the second feedback transistor is connected with the second end of the third input transistor.
In a second aspect, an embodiment of the present disclosure further provides a memory including the sense amplifier according to any of the above embodiments.
The sense amplifier in the disclosed embodiment comprises a first-stage amplification module and a second-stage amplification module. The first-stage amplification module converts the first-stage input signals with small difference into second-stage input signals, and the second-stage amplification module senses the second-stage input signals and outputs sensing amplification signals. The embodiment of the disclosure further includes a feedback module, where the feedback module also receives the first-stage input signal and feeds back the result to the inside of the second-stage amplification module, for example, the output end of the second-stage input unit, but not the input end of the second-stage amplification module, so as to accelerate the sensing speed of the second-stage amplification module, save the time of the sense amplifier in the sampling stage, and thus improve the sensing margin.
Drawings
FIG. 1 is a schematic diagram of a sense amplifier in some embodiments;
FIG. 2 is a block diagram of a sense amplifier according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of yet another sense amplifier in an embodiment of the present disclosure;
fig. 4 is a circuit connection diagram of a sense amplifier in an embodiment of the disclosure.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In some embodiments, as shown In fig. 1, the sense amplifier 10 includes an input pair of NMOS (N-Metal-Oxide-Semiconductor) transistor N1 and an NMOS transistor N2, wherein a drain of the NMOS transistor N1 is connected to a first Node1, a drain of the NMOS transistor N2 is connected to a second Node2, a gate of the NMOS transistor N1 is configured to receive a first input signal In1, a gate of the NMOS transistor N2 is configured to receive a second input signal In2, a PMOS transistor (P-Metal-Oxide-Semiconductor) P2 and an NMS transistor N3 connected In series are provided between the first Node1 and the power supply terminal VDD, wherein a gate of the PMOS transistor P2 is connected to a gate of the NMOS transistor N3, a drain of the PMOS transistor P2 is connected to a drain of the NMOS transistor N3, the drain of the PMOS transistor P2 and the drain of the NMOS transistor N3 can also be used as the first output terminal Out1, a source of the PMOS transistor P2 is connected to the power supply terminal VDD, and a source of the NMOS transistor N3 is connected to the first Node1. A PMOS tube P3 and an NMS tube N4 which are connected in series are arranged between the second Node2 and a power supply end VDD, wherein a grid electrode of the PMOS tube P3 is connected with a grid electrode of the NMOS tube N4, a drain electrode of the PMOS tube P3 is connected with a drain electrode of the NMOS tube N4, the drain electrode of the PMOS tube P3 and the drain electrode of the NMOS tube N4 can also be used as a second output end Out2, a source electrode of the PMOS tube P3 is connected with the power supply end VDD, and a source electrode of the NMOS tube N4 is connected with the second Node2. A PMOS tube P4 is arranged between the first Node1 and a power supply end VDD, the grid electrode of the PMOS tube P4 is used for receiving a clock signal, the source electrode of the PMOS tube P4 is used for being connected with the power supply end VDD, and the drain electrode of the PMOS tube P4 is connected with the first output end Out1 and also connected with the grid electrode of the PMOS tube P3 and the grid electrode of the NMOS tube N4. A PMOS tube P5 is arranged between the second output end Out2 and a power supply end VDD, the grid electrode of the PMOS tube P5 is used for receiving a clock signal, the source electrode of the PMOS tube P5 is used for being connected with the power supply end VDD, and the drain electrode of the PMOS tube P5 is connected with the second output end Out2 and also connected with the grid electrode of the PMOS tube P2 and the grid electrode of the NMOS tube N3.
The operation of the sense amplifier 10 mainly includes a precharge phase and a sampling phase.
In the precharge stage, the clock signal CLK is at a low level, and the PMOS transistor P4 and the PMOS transistor P5 are turned on, so that the first output terminal Out1 and the second output terminal Out2 output the same high level, and the sense amplifier 10 completes the precharge process.
In the sampling phase, the clock signal CLK is high, and the PMOS transistors P4 and P5 are turned off. The gate of the NMOS transistor N1 receives the first input signal In1 (e.g., the signal to be compared) to turn on, and the gate of the NMOS transistor N2 receives the second input signal In2 (e.g., the reference signal) to turn on.
It should be noted that, in the sampling phase, due to the difference In the voltages of the first input signal In1 and the second input signal In2, the rates of voltage reduction of the first output terminal Out1 and the second output terminal Out2 are different, so that a voltage difference exists between the first output terminal Out1 and the second output terminal Out 2. In some embodiments, if the first input signal In1 is higher than the second input signal In2, so that the voltage of the first output terminal Out1 is reduced faster than the voltage of the second output terminal Out2, the PMOS transistor P3 is turned on first, the voltage of the second output terminal Out2 is pulled up to the power supply voltage VDD, the high voltage of the second output terminal Out2 further opens the NMOS transistor N3, and thus the voltage of the first output terminal Out1 is pulled down further to the ground voltage GND. In other embodiments, if the first input signal In1 is smaller than the second input signal In2, so that the voltage of the first output terminal Out1 is reduced more slowly than the voltage of the second output terminal Out2, the PMOS transistor P2 is turned on first, the first output terminal Out1 is pulled up to the power supply voltage VDD, the high voltage of the first output terminal Out1 further opens the NMOS transistor N4, and the voltage of the second output terminal Out2 is pulled down to the ground voltage GND. That is, the voltage difference between the first input signal In1 and the second input signal In2 can be sensed and amplified through the NMOS transistor N3, the NMOS transistor N4, the PMOS transistor P2, and the PMOS transistor P3 until the first output terminal Out1 and the second output terminal Out2 output the ground voltage GND and the power voltage VDD, respectively.
In summary, if the first input signal In1 is higher than the second input signal In2, the first output terminal Out1 is at a low level, and the second output terminal Out2 is at a high level.
Similarly, if the first input signal In1 is lower than the second input signal In2, the first output terminal Out1 forms a high level, and the second output terminal Out2 forms a low level.
According to the level of the first output end Out1 or the second output end Out2 after the sampling stage, the magnitude relation between the first input signal In1 and the second input signal In2 can be judged.
The time used by the sense amplifier 10 in the sampling stage is a key index of the sense amplifier 10, and the less the time used by the sense amplifier 10 in the sampling stage, the faster the response speed of the sense amplifier is, the easier the comparison result is output, and how to reduce the time of the sense amplifier 10 in the sampling stage becomes a problem to be solved urgently.
An embodiment of the present disclosure provides a sense amplifier, as shown in fig. 2, a sense amplifier 1000 includes:
first amplification module 100, comprising: a first-stage input unit 110; a first terminal of the first stage input unit 110 is configured to receive a first stage input signal IN1, and a second terminal of the first stage input unit 110 is configured to output a second stage input signal IN2;
a second amplification module 200, comprising: a second-stage input unit 210; a first terminal of the second stage input unit 210 is configured to receive a second stage input signal IN2; the second end of the second amplifying block 200 is configured to output a sensing amplified signal OUT; the first end of the second-stage input unit 210 is the first end of the second amplification module 200;
a third terminal of the feedback module 300 is connected to the third terminal of the first-stage input unit 110, a first terminal of the feedback module 300 is configured to receive the first-stage input signal IN1, and a second terminal of the feedback module 300 is connected to the second terminal of the second-stage input unit and outputs a complementary signal C1 to the second terminal of the second-stage input unit.
The sense amplifier 1000 in the embodiment of the present disclosure includes a first-stage amplification block 100 and a second-stage amplification block 200. When the circuit needs to work at a higher speed, the first-stage amplification module 100 (which can function as a current integrator) is needed to pre-amplify the signal, the first-stage amplification module 100 provides some gains for the input small-swing signal (i.e., the first-stage input signal) and outputs a second-stage input signal IN2, and the second-stage amplification module 200 senses the second-stage input signal IN2 and outputs a sensing amplification signal OUT. Without the first stage amplification module, when it is necessary to amplify a small swing signal at a higher speed, the size of the second stage input module of the sense amplifier 10 needs to be increased, which may result in an increase in the total size of the sense amplifier 10 and an increase in the occupied area. The embodiment of the present disclosure further includes a feedback module 300, where the feedback module 300 also receives the first-stage input signal IN1 and feeds back the result to the inside of the second-stage amplification module 200, for example, the output end of the second-stage input unit, instead of the input end of the second-stage amplification module 200, so as to accelerate the sensing speed of the second-stage amplification module 200, save the time of the sense amplifier 1000 IN the sampling phase, and thus improve the sensing margin.
In some embodiments, as shown in FIG. 3, sense amplifier 1000 further comprises:
a Decision Feedback Equalization module (DFE) 400, an Equalization signal B1 output terminal of the DFE400 is connected to a first terminal of the second stage input unit 210 for equalizing the second stage input signal IN2.
The DFE400 can be implemented by a digital high frequency filter, so the DFE400 can choose to amplify only the signal and not the noise. The DFE400 is applied to an input terminal of the second stage input unit 210 for performing the argument compensation of the second stage input signal IN2 of the second stage input unit 210, and the second stage input signal IN2 is generated according to the first stage input signal IN1, so that the argument compensation of the first stage input signal IN1 of the first stage input unit 110 is equivalent, the first stage input signal IN1 may include the first input signal and the second input signal, and the DFE400 may reduce the intersymbol interference between the two signals.
IN some embodiments, if the DFE module is used, the processing capability of the DFE400 to eliminate the inter-symbol interference between the first stage input signals IN1 (e.g., the first input signal and the second input signal) will be reduced if the input pair area of the first stage input unit 110 is directly increased. The second-stage input signal IN2 cannot be increased by directly increasing the area of the input pair transistors of the first-stage input unit 110.
In some embodiments, as shown in fig. 2, the second amplification module 200 further comprises:
a sensing amplification unit 220, the sensing amplification unit 220 being connected to a second end of the second-stage input unit 210; a first terminal of the sense amplifying unit 220 is configured to receive a signal of a second terminal of the second-stage input unit 210, and a second terminal of the sense amplifying unit 220 is configured to output a sense amplified signal OUT; the second end of the sense amplifying unit 220 is a second end of the second amplifying module 200.
In some embodiments, the second amplifying block 200 further includes a sensing amplifying unit 220, a first terminal (e.g., an input terminal) of the sensing amplifying unit receives a signal of a second terminal (e.g., an output terminal) of the second stage input unit 210, the signal of the second terminal of the second stage input unit 210 includes an output signal of the second stage input unit 210 itself and a complementary signal C1 of the output of the feedback block 300, which both serve to charge the second terminal of the second stage input unit 210, so that the sensing amplifying unit 220 rapidly reaches a responsive condition and outputs a sensing amplifying signal OUT.
In some embodiments, as shown in fig. 4, the sense amplifying unit 1000 includes:
a first P type transistor P2, a second P type transistor P3, a first N type transistor N3 and a second N type transistor N4; the second terminal of the second amplification block 200 includes a first output node OUT1 and a second output node OUT2; a second end of the first P-type transistor P2 is connected with a second end of the first N-type transistor N3 to serve as a first output node OUT1; a second end of the second P-type transistor P3 is connected to a second end of the second N-type transistor N4 as a second output node OUT2; the first end of the first P-type transistor P2 and the first end of the first N-type transistor N3 are both connected to the second output node OUT2; a first end of the second P-type transistor P3 and a first end of the second N-type transistor N3 are both connected to the first output node OUT1; a third end of the first N-type transistor N3 and a third end of the second N-type transistor N4 are respectively connected to a second end of the second-stage input unit 210; the third terminal of the first P-type transistor P2 and the third terminal of the second P-type transistor P3 are both connected to a first power supply terminal (e.g., VDD).
The P-type transistors in the embodiments of the present disclosure include, but are not limited to, PMOS transistors, P-channel junction field effect transistors, etc., and the N-type transistors include, but are not limited to, NMOS transistors, N-channel junction field effect transistors, etc. The present disclosure will be described below by taking PMOS transistors and NMOS transistors as examples. The first terminal of each transistor may be a gate of the transistor, and the gate may be used as a control terminal for receiving a control signal of the transistor.
The second terminal of each transistor may be a source or a drain of the transistor, and the third terminal of each transistor may be a source or a drain of the transistor. In the embodiment of the present disclosure, the second terminal of each transistor may be a drain, and the third terminal of each transistor may be a source.
The sense amplifying unit 1000 includes a first inverter formed by a PMOS transistor P2 and an NMOS transistor N3, and a second inverter formed by a PMOS transistor P3 and an NMOS transistor N4, which are coupled to each other. Specifically, the input end of the first inverter is connected with the output end of the second inverter, the input end of the second inverter is connected with the output end of the first inverter, the output end of the first inverter is the first output node OUT1, namely, the value of the first output node OUT1 is determined by the output of the first inverter, and the output end of the second inverter is the second output node OUT2, namely, the value of the second output node OUT2 is determined by the output of the second inverter.
The operation of sense amplifier 1000 includes a precharge phase and a sampling phase.
In the precharge phase, the first output node OUT1 and the second output node OUT2 both output the same high level.
In the sampling phase, the source of the NMOS transistor N3 and the source of the NMOS transistor N4 are respectively connected to the second end of the second-stage input unit 210, and the voltage signal of the second end of the second-stage input unit 210 can pull down the high levels of the reset first output node OUT1 and second output node OUT2, so that when any output node is pulled down to a certain value at first, the PMOS transistor P2 or P3 is switched to the on state, and the corresponding output node is pulled up to the high level again, thereby outputting the sampling result in the sampling phase.
In some embodiments, as shown in fig. 4, a balancing unit 230 is further connected between the third terminal of the first N-type transistor N3 and the third terminal of the second N-type transistor N4; when the balancing unit 230 is in a conducting state, the third terminal of the first N-type transistor N3 and the third terminal N4 of the second N-type transistor are at the same potential.
In the embodiment of the present disclosure, the source of the NMOS transistor N3 and the source of the NMOS transistor N4 further have a balancing unit 230, and the balancing unit 230 is configured to balance the potentials of the source of the NMOS transistor N3 and the source of the NMOS transistor N4 in the pre-charge state, so that there is no potential difference therebetween, i.e. the potentials are equal. The balancing unit 230 may also reduce mismatch problems between the second stage input units.
In some embodiments, the balancing unit 230 includes a third P-type transistor P1, and the third P-type transistor P1 is in a conducting state when the sense amplifier is in a pre-charging state, in order to reduce the mismatch problem between the pair of input transistors N1 and N2 during the sampling phase.
In some embodiments, the balancing unit 230 includes a PMOS transistor P1. In other embodiments, the balancing unit 230 may further include a plurality of PMOS transistors P1 connected in series, and control terminals of the plurality of PMOS transistors P1 are connected together for receiving the precharge signal DqsampN.
In some embodiments, the source and the drain of the PMOS transistor P1 may be further connected to the same voltage divider respectively connected to the source of the NMOS transistor N3 and the source of the NMOS transistor N4. The voltage divider may be used to adjust the voltages output to the source of the NMOS transistor N3 and the source of the NMOS transistor N4, so as to affect the operating speed of the sense amplifier 1000.
In some embodiments, as shown in fig. 4, the second amplification module 200 further includes:
the first state control unit is connected between the first power supply end and the second end of the second amplification module; the first end of the first state control unit is used for receiving a first control signal; the first control signal is used for enabling the first state control unit to be switched on or switched off;
the first state control unit is in a conducting state, and the sensitive amplifier is in a pre-charging state.
In the embodiment of the present disclosure, the first control signal may be at a high level or a low level, and when the sense amplifier 1000 receives the first control signal at the low level, the first control unit is turned on, and the sense amplifier is in a precharge state.
When the sense amplifier 1000 receives the first control signal of the high level, the first control unit is turned off, and the sense amplifier is in a sampling state.
In some embodiments, the first state control unit includes a first state transistor P4 and a second state transistor P5;
the third terminal of the first state transistor P4 is connected to a first power supply terminal (e.g., VDD); a second end of the first state transistor P4 is connected with a second end of the first N-type transistor N3; the second end of the first state transistor P4 is also connected with the first end of the second N-type tube N4; a first terminal of the first state transistor P4 is configured to receive a first control signal;
the third terminal of the second state transistor P5 is connected to a first power supply terminal (e.g., VDD); a second end of the second state transistor P5 is connected with a second end of the second N-type transistor N4; the second end of the second state transistor N4 is also connected with the first end of the first N-type pipe N3; the first terminal of the second state transistor P5 is configured to receive the first control signal.
In some embodiments, when the control terminals of the PMOS transistors P4 and P5 receive the first control signal with a low level, the PMOS transistors P4 and P5 are turned on.
The source of the PMOS transistor P4 and the source of the PMOS transistor P5 are commonly connected to a first power supply terminal (e.g., VDD). In the embodiment of the disclosure, the PMOS transistors P4 and P5 may be the same type of transistors. When the PMOS transistors P4 and P5 are turned on, the currents flowing through the transistors are the same, and the voltage drops generated in the transistors are also the same, so that the output values of the first output node OUT1 and the second output node OUT2 are the same.
In some embodiments, as shown in fig. 4, the first amplification module 100 further includes:
a second state control unit connected between the first-stage input unit 110 and the first power terminal VDD; the first end of the second state control unit is used for receiving a second control signal; the second control signal is used for enabling the second state control unit to be switched on or switched off;
in the on state of the second state control unit, the sense amplifier 1000 is in the sampling state.
The second control signal can be high level or low level, and the first control signal and the second control signal are always opposite. For example, the second control signal is at a low level when the first control signal is at a high level, and at a high level when the first control signal is at a low level.
In some embodiments, when the second control signal is high, the second state control unit is turned off, and the sense amplifier 1000 is in a precharge state. When the second control signal is at a low level, the second state control unit is turned on, and the sense amplifier 1000 is in a sampling state.
When the sense amplifier 1000 is in the sampling state, the second state control unit may transmit the power supply voltage VDD to the source of the first stage input unit 110, and when the first stage input unit 110 receives the first stage input signal, the power supply voltage VDD may be transmitted to the input terminal of the second stage input unit.
In some embodiments, as shown in fig. 4, the first amplification module 100 further includes:
a third state control unit connected between the first-stage input unit 110 and a second power source terminal (e.g., GND); the first end of the third state control unit is used for receiving a second control signal; the second control signal is also used for enabling the third state control unit to be switched on or switched off;
the third state controls the transistor to be in a conducting state, and the sense amplifier 1000 is in a pre-charging state; the second state control unit and the third state control unit are not conducted at the same time.
Since the input signal of the first stage input unit 110 is in a normally low state relative to the threshold voltage of the first stage input unit 110, the first stage input unit 110 can be in a conducting state in both the pre-charge state and the sampling state.
In the precharge state, the third state control unit to which the first stage input unit 110 is connected is in an off state, and the source voltage of the first stage input unit is not supplied from the first power source terminal to which the third state control unit is connected but is supplied from the second terminal of the second stage input unit 210 to charge the first stage input unit 110. When the first-stage input unit is charged completely, the source of the first-stage input unit is denoted as a Vcm terminal, and when the third-state control unit is turned on, a conductive path from the Vcm terminal to the third-state control unit and then to the second power supply terminal (e.g., GND) is formed.
In some embodiments, the third state control unit comprises: a third state transistor N5 and a fourth state transistor N6;
a first terminal of the third state transistor N5 is connected to a first terminal of the fourth state transistor N6;
a second terminal of the third state transistor N5 is connected to a second terminal of the first stage input unit 110;
a second terminal of the fourth state transistor N6 is connected to a second terminal of the first stage input unit 110.
In some embodiments, the third state control unit comprises: and the control end of the NMOS transistor N5 is connected with the control end of the NMOS transistor N6, and the NMOS transistor N5 and the NMOS transistor N6 receive a second control signal Dqsamp together. In some embodiments, when the second control signal Dqsamp is high, the NMOS transistor N5 and the NMOS transistor N6 are turned on, so as to allow the voltages at the drains of the NMOS transistors N5 and N6 to flow to the ground.
In some embodiments, the first stage input signal comprises: sensing an input signal DQ and a reference signal Vref;
the first-stage input unit 110 includes: a first input transistor P7 and a second input transistor P8;
a first terminal of the first input transistor P7 is for receiving a sensing input signal DQ; the first terminal P8 of the second input transistor is for receiving the reference signal Vref.
The first-stage input signal may include two input signals, one of which may be a reference signal Vref, and the signal may be a fixed value or may vary according to a known rule. The other input signal may be a sensing input signal DQ, and in some embodiments, the sensing input signal DQ may be a digital signal that is sent out through a Channel by a signal collected by an SOC (System on Chip), where the collected signal is attenuated to some extent due to a Channel medium and the like, so that the digital signal is an attenuated signal. Therefore, if the digital signal is directly compared with the reference signal, the difference may not be large, and it is difficult to distinguish. The above is just one example of the sensing input signal DQ, which may be a digital signal or an analog signal.
In some embodiments, the sense input signal DQ is determined to be binary data "1" if the sense input signal DQ is greater than the reference signal Vref. If the sense input signal DQ is less than the reference signal Vref, the sense input signal DQ is determined as binary data "0".
In some embodiments, the second-level input unit 210 includes: a third input transistor N1 and a fourth input transistor N2;
a first terminal of the third input transistor N1 is connected to a second terminal of the first input transistor P7;
a first terminal of the fourth input transistor N2 is connected to a second terminal of the second input transistor P8.
The second-stage input unit 210 may include an NMOS transistor N1 and an NMOS transistor N2, an input end of the second-stage input unit 210 is an input end of the second amplification module 200, and specifically, the input end of the second-stage input unit 210 may be a control end of the NMOS transistor N1 and a control end of the NMOS transistor N2. Which is used to receive the output terminals of the first-stage input unit 110, i.e. the drain voltages of the PMOS transistors P7 and P8.
In some embodiments, the feedback module 300 includes:
a first feedback transistor P9 and a second feedback transistor P10;
a first end of the first feedback transistor P9 is used for receiving the sensing input signal DQ, and a second end of the first feedback transistor P9 is connected to a second end of the fourth input transistor N2;
a first terminal of the second feedback transistor P10 is configured to receive the reference signal Vref, and a second terminal of the second feedback transistor P10 is connected to a second terminal of the third input transistor N1.
In some embodiments, the feedback module 300 includes a PMOS transistor P9 and a PMOS transistor P10. In some embodiments, the feedback module 300 includes a plurality of PMOS transistors P9 connected in parallel and a plurality of PMOS transistors P10 connected in parallel.
The channel width of the PMOS transistor used by the feedback module 300 may be smaller than that of the PMOS transistor used by the first-stage input unit of the sense amplifier 1000. To avoid impairing the processing power of the DFE400 on the first stage input signal.
The feedback module 300 is used for feeding back the influence of the first-stage input signal to the second amplification module, so as to speed up the response speed of the sense amplifier to the first-stage input signal.
The PMOS transistors P9 and P10 have an inverting effect, which is a concept applied to the situation where the drains of the PMOS transistors are connected to the load, the drains are used as signal outputs, and the gates (or control terminals) are used as signal inputs. When the input signal (e.g., voltage signal) of the gate of the PMOS transistor increases, the current of the branch where the PMOS transistor is located increases, the voltage drop of the load on the branch increases, and the voltage output by the drain of the PMOS transistor decreases on the premise that the potential (e.g., power voltage VDD) connected to the source of the PMOS transistor is not changed, which is expressed as the signal inversion effect of the gate and the drain.
Due to the existence of the phase inversion effect, the drain of the PMOS transistor P9 receiving the sensing input signal DQ needs to be connected to the drain of the NMOS transistor N2 connected to the PMOS transistor P8 receiving the reference signal Vref, and the drain of the PMOS transistor P10 receiving the reference signal Vref needs to be connected to the drain of the NMOS transistor N1 connected to the PMOS transistor P7 receiving the sensing input signal DQ.
The feedback module 300 and the second terminal of the second stage input unit may be connected by a wire, so as to avoid the influence of the wire on the voltage output by the drains of the PMOS transistor P9 and the PMOS transistor P10, the distance between the feedback module 300 and the second terminal of the second stage input unit may be reduced as much as possible, i.e. a short metal connection wire is used to connect the feedback module 300 and the second terminal of the second stage input unit.
The embodiment of the present disclosure further provides a memory 1100 including the sense amplifier 1000 according to any one of the above embodiments.
The sense amplifier 1000 according to the embodiment of the present disclosure may also be applied to various memories 1100, for example, when applied to a DRAM, the sense amplifier 1000 may be turned on at a suitable time point, and the sense amplifier 1000 may amplify a weak voltage difference between a bit line and a complementary bit line, so that data stored in a memory cell may be correctly read.
The working process of the embodiment of the present disclosure includes a pre-charging phase and a sampling phase, which will be described in detail with reference to fig. 4.
A pre-charging stage:
in the pre-charging stage, the first control signal Dqsamp is at a high level, the second control signal DqsampN is at a low level, so that the PMOS transistor P6 is in a cut-off state, the NMOS transistor N5 and the NMOS transistor N6 are in a conduction state, the PMOS transistor P4 and the PMOS transistor P5 are in a conduction state, the PMOS transistor P1 is also in a conduction state, and the PMOS transistor P1 is conducted so that the first NODE1 and the second NODE2 have an equal potential, which can reduce the mismatch problem between the NMOS transistor N1 and the NMOS transistor N2 of the second-stage input unit. For the PMOS transistors P7 and P8, the sensing input signal DQ and the reference signal Vref received by the control terminals are both in a normally low state, so the PMOS transistors P7 and P8 are in a normally on state.
The source electrodes of the PMOS transistors P4 and P5 receive a power supply voltage VDD, and the power supply voltage VDD has a certain voltage drop respectively through the PMOS transistors P4 and P5, and is marked as V p4 And V p5 So that the drain voltages of the PMOS transistors P4 and P5 are distributed to (VDD-V) p4 ) And (VDD-V) p5 ) Since PMOS transistors P4 and P5 can be transistors of the same type, V p4 And V p5 Equal and for PMOS transistor, the voltage drop V p4 And V p5 Is a very small voltage value, therefore (VDD-V) p4 ) And (VDD-V) p5 ) Still high voltage, it can conduct NMOS transistor N4 and NMOS transistor N3 separately, NMOS transistor N4 and NMOS transistor N3 can also be transistors of the same type, so the source electrodes of NMOS transistor N4 and NMOS transistor N3 can also have the same voltage (VDD-V) p4 -V N4 ) And (VDD-V) p3 -V N3 ). The source voltages of the NMOS transistor N4 and the NMOS transistor N3 may charge the PMOS transistor P9 and the PMOS transistor P10 (the source of the PMOS transistor P9 is connected to the source of the PMOS transistor P10 is a Vcm terminal), so that the Vcm terminal has a high voltage, and since the NMOS transistor N5 and the NMOS transistor N6 are in a conducting state, there is a conductive path from the Vcm terminal to the ground terminal.
In the embodiment of the present disclosure, the PMOS transistor P1 is connected between the source of the NMOS transistor N4 and the source of the NMOS transistor N3, so as to further ensure that the voltages of the source of the NMOS transistor N4 and the source of the NMOS transistor N3 are the same in the pre-charging stage.
In the pre-charge stage, the voltages of the first output node OUT1 and the second output node OUT2 are the same and are both high.
A sampling stage:
in the sampling stage, the first control signal Dqsamp is at a low level, and the second control signal DqsampN is at a high level, such that the PMOS transistor P6 is in a conducting state, the NMOS transistor N5 and the NMOS transistor N6 are in a blocking state, the PMOS transistor P4 and the PMOS transistor P5 are in a blocking state, and the PMOS transistor P1 is also in a blocking state. For the PMOS transistors P7 and P8, the sensing input signal Dq and the reference signal Vref received by the control terminals are both in a normally low state, so that the PMOS transistors P7 and P8 are in a normally on state.
Since the PMOS transistor P6 is in the on state, the Vcm end receives the power voltage VDD, the voltage drop of the PMOS transistor P6 can be ignored here, and the voltage at the Vcm end is recorded as the power voltage VDD.
The PMOS tube P7, the PMOS tube P8, the PMOS tube P9 and the PMOS tube P10 are all IN a conducting state, when the value of the sensing input signal DQ is smaller than the reference signal Vref, the drain voltage of the PMOS tube P7 is larger than the drain voltage of the PMOS tube P8, so that for the NMOS tube N1 and the NMOS tube N2, the first second input voltage IN11 received by the control end of the NMOS tube N1 is larger than the second input voltage IN12 received by the control end of the NMOS tube N2, the NMOS tube N1 and the NMOS tube N2 are conducted, and then the high voltage of the first output end OUT1 and the high voltage of the second output end OUT2 are gradually reduced to a low level due to the influence of the first second input signal IN11 and the second input signal IN 12. The PMOS transistor P2 may be triggered to be in a conducting state by a low level of the first output terminal OUT1, and the PMOS transistor P3 may be triggered to be in a conducting state by a low level of the second output terminal OUT 2.
The disclosed embodiment further includes a DFE400 that connects the first second input signal IN11 and the second input signal IN12 to reduce inter-symbol crosstalk between the sensing input signal DQ and the reference signal Vref.
It should be noted that, IN the sampling phase, due to the difference between the voltages of the first second input signal IN11 and the second input signal IN12, the voltage reduction rates of the first output terminal OUT1 and the second output terminal OUT2 are different, so that a voltage difference exists between the first output terminal OUT1 and the second output terminal OUT 2. IN some embodiments, if the first second input signal IN11 is higher than the second input signal IN12, the voltage of the first output terminal OUT1 is reduced faster than the voltage of the second output terminal OUT2, so that the voltage of the first output terminal OUT1 is lower than the voltage of the second output terminal OUT 2. When the voltage of the first output end OUT1 is lower than the starting voltage of the PMOS tube P3, the PMOS tube P3 is conducted in a pilot mode, the power supply voltage VDD is transmitted to the second output end OUT2 through the PMOS tube P3, the NMOS tube N3 is further opened by the high voltage of the second output end OUT2, the low voltage of the first output end is further pulled down to the ground voltage GND, and therefore the sampling process of the sensing input signal DQ and the reference signal Vref is completed.
In other embodiments, if the sensing input signal DQ is less than the reference signal Vref, the voltage of the first output terminal OUT1 is decreased more slowly than the voltage of the second output terminal OUT2, so that the voltage of the first output terminal OUT1 is higher than the voltage of the second output terminal OUT 2. When the voltage of the second output end OUT2 is lower than the starting voltage of the PMOS tube P2, the PMOS tube P2 is firstly conducted, the power supply voltage VDD is transmitted to the first output end OUT1 through the PMOS tube P2, the NMOS tube N4 is further opened by the high voltage of the first output end OUT1, the low voltage of the second output end is further pulled down to the ground voltage GND, and therefore the sampling process of the sensing input signal DQ and the reference signal Vref is completed.
The feedback module 300 includes a PMOS transistor P9 and a PMOS transistor P10, which are respectively conducted by the input signal DQ and the reference signal Vref, and drains of the PMOS transistor P9 and the PMOS transistor P10 are directly connected to the NODE2 terminal and the NODE1 terminal, so that a voltage is applied to the NODE1 and the NODE2, and the voltage can generate a pull-up action on the NODE1 and the NODE2. If the sense input signal DQ is greater than the reference signal Vref, the pull-up of the voltage on NODE2 by PMOS transistor P9 is stronger than the pull-up of the voltage on NODE1 by PMOS transistor P10. When the combined sensing input signal DQ is larger than the reference signal Vref, the pull-down action of the NMOS transistor N1 on NODE1 is stronger than the pull-down action of the NMOS transistor N2 on NODE2. The potential difference between NODE1 and NODE2 is further amplified and the sensing result that the second output terminal OUT2 is at the high level and the first output terminal OUT1 is at the low level can be obtained more quickly.
Similarly, if the sense input signal DQ is less than the reference signal Vref, the pull-up of the voltage on NODE2 by the PMOS transistor P9 is weaker than the pull-up of the voltage on NODE1 by the PMOS transistor P10. When the combined sensing input signal DQ is smaller than the reference signal Vref, the pull-down action of the NMOS transistor N1 on NODE1 is weaker than the pull-down action of the NMOS transistor N2 on NODE2. The potential difference between NODE1 and NODE2 is further amplified, and the sensing result that the second output terminal OUT2 is at a low level and the first output terminal OUT1 is at a high level can be obtained more quickly.
It can be seen that the sense amplifier 1000 can have a faster sensing speed by adding the feedback module 300, thereby saving the time of the sampling phase and increasing the sensing margin.
In summary, if the sensing input signal DQ is higher than the reference signal Vref, the first output terminal OUT1 is at a low level, and the second output terminal OUT2 is at a high level.
Similarly, if the sensing input signal DQ is higher than the reference signal Vref, the first output terminal OUT1 forms a high level, and the second output terminal OUT2 forms a low level.
Thus, the sense amplifier 1000 performs the functions of sensing and amplifying the sensing input signal DQ and the reference signal Vref.
The magnitude relationship between the sensing input signal DQ and the reference signal Vref can be determined according to the output result of the second output terminal OUT2 or the first output terminal OUT 1.
The result of the eye pattern test performed on the embodiment of the present disclosure is: the stronger the on effect of the DFE400, the larger the area of the eye pattern, which is manifested as a smaller error rate.
The results of the time margin test performed on the embodiment of the present disclosure are: under the same on condition of the DFE400, the disclosed embodiments have more time margin, which is reflected in a smaller error rate.
That is, the feedback unit used in the embodiment of the present disclosure may replace the DFE400 to some extent, and the DFE400 with a smaller area may be used to achieve the same effect of reducing the error rate.
The embodiment of the disclosure is particularly suitable for being used under the condition that the transmission rate is 7500 Mbps.
It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (15)

1. A sense amplifier, comprising:
a first amplification module comprising: a first-stage input unit; the first end of the first-stage input unit is used for receiving a first-stage input signal, and the second end of the first-stage input unit is used for outputting a second-stage input signal;
a second amplification module comprising: a second-stage input unit; the first end of the second-stage input unit is used for receiving the second-stage input signal; the first end of the second amplifying module is used for receiving the second-stage input signal, and the second end of the second amplifying module is used for outputting a sensing amplifying signal; the first end of the second-stage input unit is the first end of the second amplification module;
and the third end of the feedback module is connected with the third end of the first-stage input unit, the first end of the feedback module is used for receiving the first-stage input signal, and the second end of the feedback module is connected with the second end of the second-stage input unit and outputs a supplementary signal to the second end of the second-stage input unit.
2. The sense amplifier of claim 1, further comprising:
and the equalizing signal output end of the decision feedback equalizing module is connected with the first end of the second-stage input unit and is used for equalizing the second-stage input signal.
3. The sense amplifier of claim 1, wherein the second amplification block further comprises:
the sensing amplification unit is connected with the second end of the second-stage input unit; the first end of the sensing amplification unit is used for receiving a signal of the second end of the second-stage input unit, and the second end of the sensing amplification unit is used for outputting the sensing amplification signal; the second end of the sensing amplification unit is the second end of the second amplification module.
4. The sense amplifier of claim 3, wherein the sense amplifying unit comprises:
a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; the second end of the second amplification module comprises a first output node and a second output node;
a second end of the first P-type transistor is connected with a second end of the first N-type transistor to serve as the first output node;
a second end of the second P-type transistor is connected with a second end of the second N-type transistor to serve as the second output node;
the first end of the first P-type transistor and the first end of the first N-type transistor are both connected to the second output node;
a first end of the second P-type transistor and a first end of the second N-type transistor are both connected to the first output node;
the third end of the first N-type transistor and the third end of the second N-type transistor are respectively connected with the second end of the second-stage input unit;
and the third ends of the first P-type transistor and the second P-type transistor are both connected with a first power supply end.
5. The sense amplifier of claim 4, wherein a balancing unit is further connected between the third terminal of the first N-type transistor and the third terminal of the second N-type transistor; and when the balancing unit is in a conducting state, the third end of the first N-type transistor and the third end of the second N-type transistor are equipotential.
6. The sense amplifier of claim 5 wherein the balancing unit comprises a third P-type transistor, the third P-type transistor being in a conducting state when the sense amplifier is in a pre-charge state.
7. The sense amplifier of claim 4, wherein the second amplification module further comprises:
the first state control unit is connected between the first power supply end and the second end of the second amplification module; the first end of the first state control unit is used for receiving a first control signal; the first control signal is used for enabling the first state control unit to be switched on or switched off;
when the first state control unit is in a conducting state, the sensitive amplifier is in a pre-charging state.
8. The sense amplifier of claim 7, wherein the first state control unit comprises a first state transistor and a second state transistor;
the third end of the first state transistor is connected with the first power supply end; the second end of the first state transistor is connected with the second end of the first N-type transistor; the second end of the first state transistor is also connected with the first end of the second N-type tube; the first end of the first state transistor is used for receiving the first control signal;
the third end of the second state transistor is connected with the first power supply end; a second end of the second state transistor is connected with a second end of the second N-type transistor; the second end of the second state transistor is also connected with the first end of the first N-type tube; the first end of the second state transistor is used for receiving the first control signal.
9. The sense amplifier of claim 1, wherein the first amplification module further comprises:
a second state control unit connected between the first-stage input unit and a first power source terminal; the first end of the second state control unit is used for receiving a second control signal; the second control signal is used for enabling the second state control unit to be switched on or switched off;
and when the second state control unit is in a conducting state, the sensitive amplifier is in a sampling state.
10. The sense amplifier of claim 9, wherein the first amplification block further comprises:
a third state control unit connected between the first-stage input unit and a second power supply terminal; the first end of the third state control unit is used for receiving the second control signal; the second control signal is also used for enabling the third state control unit to be switched on or switched off;
the third state controls the transistor to be in a conducting state, and the sensitive amplifier is in a pre-charging state; the second state control unit and the third state control unit are not conducted at the same time.
11. The sense amplifier of claim 10, wherein the third state control unit comprises: a third state transistor and a fourth state transistor;
a first end of the third state transistor is connected with a first end of the fourth state transistor;
a second end of the third state transistor is connected with a second end of the first stage input unit;
a second terminal of the fourth state transistor is connected to a second terminal of the first stage input unit.
12. The sense amplifier of any of claims 1 to 11, wherein the first stage input signal comprises: sensing an input signal and a reference signal;
the first stage input unit includes: a first input transistor and a second input transistor;
a first terminal of the first input transistor is to receive the sense input signal; the first terminal of the second input transistor is used for receiving the reference signal.
13. The sense amplifier of claim 12, wherein the second stage input unit comprises: a third input transistor and a fourth input transistor;
a first terminal of the third input transistor is connected with a second terminal of the first input transistor;
a first terminal of the fourth input transistor is connected to a second terminal of the second input transistor.
14. The sense amplifier of claim 13, wherein the feedback module comprises:
a first feedback transistor and a second feedback transistor;
the first end of the first feedback transistor is used for receiving the sensing input signal, and the second end of the first feedback transistor is connected with the second end of the fourth input transistor;
the first end of the second feedback transistor is used for receiving the reference signal, and the second end of the second feedback transistor is connected with the second end of the third input transistor.
15. A memory comprising a sense amplifier as claimed in any one of claims 1 to 14.
CN202210901507.9A 2022-07-28 2022-07-28 Sense amplifier and memory Pending CN115206358A (en)

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